1 /* 2 * Copyright (c) 2025, Mediatek Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <arch_def.h> 11 12 #define PLAT_PRIMARY_CPU (0x0) 13 14 #define MT_GIC_BASE (0x0C000000) 15 #define MCUCFG_BASE (0x0C530000) 16 #define MCUCFG_REG_SIZE (0x10000) 17 #define IO_PHYS (0x10000000) 18 19 /* Aggregate of all devices for MMU mapping */ 20 #define MTK_DEV_RNG0_BASE (MT_GIC_BASE) 21 #define MTK_DEV_RNG0_SIZE (0x600000) 22 #define MTK_DEV_RNG1_BASE (IO_PHYS) 23 #define MTK_DEV_RNG1_SIZE (0x10000000) 24 25 #define TOPCKGEN_BASE (IO_PHYS) 26 27 /******************************************************************************* 28 * GPIO related constants 29 ******************************************************************************/ 30 #define GPIO_BASE (IO_PHYS + 0x00005000) 31 #define IOCFG_LM_BASE (IO_PHYS + 0x01B50000) 32 #define IOCFG_RB0_BASE (IO_PHYS + 0x01C50000) 33 #define IOCFG_RB1_BASE (IO_PHYS + 0x01C60000) 34 #define IOCFG_BM0_BASE (IO_PHYS + 0x01D20000) 35 #define IOCFG_BM1_BASE (IO_PHYS + 0x01D30000) 36 #define IOCFG_BM2_BASE (IO_PHYS + 0x01D40000) 37 #define IOCFG_LT0_BASE (IO_PHYS + 0x01E20000) 38 #define IOCFG_LT1_BASE (IO_PHYS + 0x01E30000) 39 #define IOCFG_RT_BASE (IO_PHYS + 0x01F20000) 40 41 /******************************************************************************* 42 * UART related constants 43 ******************************************************************************/ 44 #define UART0_BASE (IO_PHYS + 0x01002000) 45 #define UART_BAUDRATE (115200) 46 47 /******************************************************************************* 48 * System counter frequency related constants 49 ******************************************************************************/ 50 #define SYS_COUNTER_FREQ_IN_HZ (13000000) 51 #define SYS_COUNTER_FREQ_IN_MHZ (13) 52 53 /******************************************************************************* 54 * Platform binary types for linking 55 ******************************************************************************/ 56 #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" 57 #define PLATFORM_LINKER_ARCH aarch64 58 59 /******************************************************************************* 60 * Generic platform constants 61 ******************************************************************************/ 62 #define PLATFORM_STACK_SIZE (0x800) 63 #define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" 64 #define SOC_CHIP_ID U(0x8189) 65 66 /******************************************************************************* 67 * Platform memory map related constants 68 ******************************************************************************/ 69 #define TZRAM_BASE (0x54600000) 70 #define TZRAM_SIZE (0x00200000) 71 72 /******************************************************************************* 73 * BL31 specific defines. 74 ******************************************************************************/ 75 /* 76 * Put BL3-1 at the top of the Trusted SRAM (just below the shared memory, if 77 * present). BL31_BASE is calculated using the current BL3-1 debug size plus a 78 * little space for growth. 79 */ 80 #define BL31_BASE (TZRAM_BASE + 0x1000) 81 #define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE) 82 83 /******************************************************************************* 84 * Platform specific page table and MMU setup constants 85 ******************************************************************************/ 86 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 87 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 88 #define MAX_XLAT_TABLES (16) 89 #define MAX_MMAP_REGIONS (16) 90 91 /******************************************************************************* 92 * SYSTIMER related definitions 93 ******************************************************************************/ 94 #define SYSTIMER_BASE (IO_PHYS + 0x0CC10000) 95 96 #endif /* PLATFORM_DEF_H */ 97