1/* 2 * Copyright (c) 2022-2023, Google LLC. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <asm_macros.S> 8#include <cortex_x1.h> 9#include <cpu_macros.S> 10#include "wa_cve_2022_23960_bhb_vector.S" 11 12/* Hardware handled coherency */ 13#if HW_ASSISTED_COHERENCY == 0 14#error "Cortex-X1 must be compiled with HW_ASSISTED_COHERENCY enabled" 15#endif 16 17/* 64-bit only core */ 18#if CTX_INCLUDE_AARCH32_REGS == 1 19#error "Cortex-X1 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 20#endif 21 22#if WORKAROUND_CVE_2022_23960 23 wa_cve_2022_23960_bhb_vector_table CORTEX_X1_BHB_LOOP_COUNT, cortex_x1 24#endif /* WORKAROUND_CVE_2022_23960 */ 25 26workaround_reset_start cortex_x1, ERRATUM(1688305), ERRATA_X1_1688305 27 sysreg_bit_set CORTEX_X1_ACTLR2_EL1, BIT(1) 28workaround_reset_end cortex_x1, ERRATUM(1688305) 29 30check_erratum_ls cortex_x1, ERRATUM(1688305), CPU_REV(1, 0) 31 32workaround_reset_start cortex_x1, ERRATUM(1821534), ERRATA_X1_1821534 33 sysreg_bit_set CORTEX_X1_ACTLR2_EL1, BIT(2) 34workaround_reset_end cortex_x1, ERRATUM(1821534) 35 36check_erratum_ls cortex_x1, ERRATUM(1821534), CPU_REV(1, 0) 37 38workaround_reset_start cortex_x1, ERRATUM(1827429), ERRATA_X1_1827429 39 sysreg_bit_set CORTEX_X1_CPUECTLR_EL1, BIT(53) 40workaround_reset_end cortex_x1, ERRATUM(1827429) 41 42check_erratum_ls cortex_x1, ERRATUM(1827429), CPU_REV(1, 0) 43 44check_erratum_chosen cortex_x1, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 45 46workaround_reset_start cortex_x1, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 47#if IMAGE_BL31 48 /* 49 * The Cortex-X1 generic vectors are overridden to apply errata 50 * mitigation on exception entry from lower ELs. 51 */ 52 override_vector_table wa_cve_vbar_cortex_x1 53#endif /* IMAGE_BL31 */ 54workaround_reset_end cortex_x1, CVE(2022, 23960) 55 56cpu_reset_func_start cortex_x1 57cpu_reset_func_end cortex_x1 58 59 /* --------------------------------------------- 60 * HW will do the cache maintenance while powering down 61 * --------------------------------------------- 62 */ 63func cortex_x1_core_pwr_dwn 64 sysreg_bit_set CORTEX_X1_CPUPWRCTLR_EL1, CORTEX_X1_CORE_PWRDN_EN_MASK 65 isb 66 ret 67endfunc cortex_x1_core_pwr_dwn 68 69 /* --------------------------------------------- 70 * This function provides Cortex X1 specific 71 * register information for crash reporting. 72 * It needs to return with x6 pointing to 73 * a list of register names in ascii and 74 * x8 - x15 having values of registers to be 75 * reported. 76 * --------------------------------------------- 77 */ 78.section .rodata.cortex_x1_regs, "aS" 79cortex_x1_regs: /* The ascii list of register names to be reported */ 80 .asciz "cpuectlr_el1", "" 81 82func cortex_x1_cpu_reg_dump 83 adr x6, cortex_x1_regs 84 mrs x8, CORTEX_X1_CPUECTLR_EL1 85 ret 86endfunc cortex_x1_cpu_reg_dump 87 88declare_cpu_ops cortex_x1, CORTEX_X1_MIDR, \ 89 cortex_x1_reset_func, \ 90 cortex_x1_core_pwr_dwn 91