1 /* 2 * Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <string.h> 9 10 #include <arch.h> 11 #include <arch_helpers.h> 12 #include <common/debug.h> 13 #include <drivers/arm/cci.h> 14 #include <drivers/arm/ccn.h> 15 #include <drivers/arm/gicv2.h> 16 #include <drivers/arm/sp804_delay_timer.h> 17 #include <drivers/arm/smmu_v3.h> 18 #include <drivers/generic_delay_timer.h> 19 #include <fconf_hw_config_getter.h> 20 #include <lib/mmio.h> 21 #include <lib/smccc.h> 22 #include <lib/xlat_tables/xlat_tables_compat.h> 23 #include <platform_def.h> 24 #include <services/arm_arch_svc.h> 25 #include <services/rmm_core_manifest.h> 26 #if SPM_MM 27 #include <services/spm_mm_partition.h> 28 #endif 29 30 #include <plat/arm/common/arm_config.h> 31 #include <plat/arm/common/plat_arm.h> 32 #include <plat/common/platform.h> 33 34 #include "fvp_private.h" 35 36 /* Defines for GIC Driver build time selection */ 37 #define FVP_GICV2 1 38 #define FVP_GICV3 2 39 40 /* Defines for RMM Console */ 41 #define FVP_RMM_CONSOLE_BASE UL(0x1c0c0000) 42 #define FVP_RMM_CONSOLE_BAUD UL(115200) 43 #define FVP_RMM_CONSOLE_CLK_IN_HZ UL(14745600) 44 #define FVP_RMM_CONSOLE_NAME "pl011" 45 #define FVP_RMM_CONSOLE_COUNT UL(1) 46 47 /* Defines for RMM PCIe ECAM */ 48 #define FVP_RMM_ECAM_BASE PCIE_EXP_BASE 49 #define FVP_RMM_ECAM_SEGMENT UL(0x0) 50 #define FVP_RMM_ECAM_BDF UL(0x0) 51 52 /* Defines for RMM SMMUv3 */ 53 #define FVP_RMM_SMMU_BASE PLAT_FVP_SMMUV3_BASE 54 #define FVP_RMM_SMMU_COUNT UL(1) 55 56 /******************************************************************************* 57 * arm_config holds the characteristics of the differences between the three FVP 58 * platforms (Base, A53_A57 & Foundation). It will be populated during cold boot 59 * at each boot stage by the primary before enabling the MMU (to allow 60 * interconnect configuration) & used thereafter. Each BL will have its own copy 61 * to allow independent operation. 62 ******************************************************************************/ 63 arm_config_t arm_config; 64 65 #define MAP_DEVICE0 MAP_REGION_FLAT(DEVICE0_BASE, \ 66 DEVICE0_SIZE, \ 67 MT_DEVICE | MT_RW | EL3_PAS) 68 69 #define MAP_DEVICE1 MAP_REGION_FLAT(DEVICE1_BASE, \ 70 DEVICE1_SIZE, \ 71 MT_DEVICE | MT_RW | EL3_PAS) 72 73 #define MAP_CCN MAP_REGION_FLAT(CCN_BASE, \ 74 CCN_SIZE, \ 75 MT_DEVICE | MT_RW | MT_SECURE) 76 77 #if FVP_GICR_REGION_PROTECTION 78 #define MAP_GICD_MEM MAP_REGION_FLAT(BASE_GICD_BASE, \ 79 BASE_GICD_SIZE, \ 80 MT_DEVICE | MT_RW | MT_SECURE) 81 82 /* Map all core's redistributor memory as read-only. After boots up, 83 * per-core map its redistributor memory as read-write */ 84 #define MAP_GICR_MEM MAP_REGION_FLAT(BASE_GICR_BASE, \ 85 (BASE_GICR_SIZE * PLATFORM_CORE_COUNT),\ 86 MT_DEVICE | MT_RO | MT_SECURE) 87 #endif /* FVP_GICR_REGION_PROTECTION */ 88 89 /* 90 * Need to be mapped with write permissions in order to set a new non-volatile 91 * counter value. 92 */ 93 #define MAP_DEVICE2 MAP_REGION_FLAT(DEVICE2_BASE, \ 94 DEVICE2_SIZE, \ 95 MT_DEVICE | MT_RW | MT_SECURE) 96 97 #if TRANSFER_LIST 98 #ifdef FW_NS_HANDOFF_BASE 99 #define MAP_FW_NS_HANDOFF \ 100 MAP_REGION_FLAT(FW_NS_HANDOFF_BASE, PLAT_ARM_FW_HANDOFF_SIZE, \ 101 MT_MEMORY | MT_RW | MT_NS) 102 #endif 103 #ifdef PLAT_ARM_EL3_FW_HANDOFF_BASE 104 #define MAP_EL3_FW_HANDOFF \ 105 MAP_REGION_FLAT(PLAT_ARM_EL3_FW_HANDOFF_BASE, \ 106 PLAT_ARM_FW_HANDOFF_SIZE, MT_MEMORY | MT_RW | EL3_PAS) 107 #endif 108 #endif 109 110 /* 111 * Table of memory regions for various BL stages to map using the MMU. 112 * This doesn't include Trusted SRAM as setup_page_tables() already takes care 113 * of mapping it. 114 */ 115 #ifdef IMAGE_BL1 116 const mmap_region_t plat_arm_mmap[] = { 117 ARM_MAP_SHARED_RAM, 118 V2M_MAP_FLASH0_RO, 119 V2M_MAP_IOFPGA, 120 MAP_DEVICE0, 121 #if FVP_INTERCONNECT_DRIVER == FVP_CCN 122 MAP_CCN, 123 #endif 124 #if TRUSTED_BOARD_BOOT 125 /* To access the Root of Trust Public Key registers. */ 126 MAP_DEVICE2, 127 /* Map DRAM to authenticate NS_BL2U image. */ 128 ARM_MAP_NS_DRAM1, 129 #endif 130 {0} 131 }; 132 #endif 133 #ifdef IMAGE_BL2 134 const mmap_region_t plat_arm_mmap[] = { 135 ARM_MAP_SHARED_RAM, 136 V2M_MAP_FLASH0_RW, 137 V2M_MAP_IOFPGA, 138 MAP_DEVICE0, 139 #if FVP_INTERCONNECT_DRIVER == FVP_CCN 140 MAP_CCN, 141 #endif 142 ARM_MAP_NS_DRAM1, 143 #ifdef __aarch64__ 144 ARM_MAP_DRAM2, 145 #endif 146 /* 147 * Required to load HW_CONFIG, SPMC and SPs to trusted DRAM. 148 */ 149 ARM_MAP_TRUSTED_DRAM, 150 151 /* 152 * Required to load Event Log in TZC secured memory 153 */ 154 #if MEASURED_BOOT && (defined(SPD_tspd) || defined(SPD_opteed) || \ 155 defined(SPD_spmd)) 156 ARM_MAP_EVENT_LOG_DRAM1, 157 #endif /* MEASURED_BOOT && (SPD_tspd || SPD_opteed || SPD_spmd) */ 158 159 #if ENABLE_RME 160 ARM_MAP_RMM_DRAM, 161 ARM_MAP_GPT_L1_DRAM, 162 #endif /* ENABLE_RME */ 163 #ifdef SPD_tspd 164 ARM_MAP_TSP_SEC_MEM, 165 #endif 166 #if TRUSTED_BOARD_BOOT 167 /* To access the Root of Trust Public Key registers. */ 168 MAP_DEVICE2, 169 #endif /* TRUSTED_BOARD_BOOT */ 170 171 #if CRYPTO_SUPPORT && !RESET_TO_BL2 172 /* 173 * To access shared the Mbed TLS heap while booting the 174 * system with Crypto support 175 */ 176 ARM_MAP_BL1_RW, 177 #endif /* CRYPTO_SUPPORT && !RESET_TO_BL2 */ 178 #if SPM_MM || SPMC_AT_EL3 179 ARM_SP_IMAGE_MMAP, 180 #endif 181 #if ARM_BL31_IN_DRAM 182 ARM_MAP_BL31_SEC_DRAM, 183 #endif 184 #ifdef SPD_opteed 185 ARM_MAP_OPTEE_CORE_MEM, 186 ARM_OPTEE_PAGEABLE_LOAD_MEM, 187 #endif 188 #ifdef MAP_EL3_FW_HANDOFF 189 MAP_EL3_FW_HANDOFF, 190 #endif 191 { 0 } 192 }; 193 #endif 194 #ifdef IMAGE_BL2U 195 const mmap_region_t plat_arm_mmap[] = { 196 MAP_DEVICE0, 197 V2M_MAP_IOFPGA, 198 {0} 199 }; 200 #endif 201 #ifdef IMAGE_BL31 202 const mmap_region_t plat_arm_mmap[] = { 203 ARM_MAP_SHARED_RAM, 204 #if USE_DEBUGFS 205 /* Required by devfip, can be removed if devfip is not used */ 206 V2M_MAP_FLASH0_RW, 207 #endif /* USE_DEBUGFS */ 208 ARM_MAP_EL3_TZC_DRAM, 209 V2M_MAP_IOFPGA, 210 MAP_DEVICE0, 211 #if FVP_GICR_REGION_PROTECTION 212 MAP_GICD_MEM, 213 MAP_GICR_MEM, 214 #else 215 #if FVP_INTERCONNECT_DRIVER == FVP_CCN 216 MAP_CCN, 217 #endif 218 MAP_DEVICE1, 219 #endif /* FVP_GICR_REGION_PROTECTION */ 220 ARM_V2M_MAP_MEM_PROTECT, 221 #if SPM_MM 222 ARM_SPM_BUF_EL3_MMAP, 223 #endif 224 #if ENABLE_RME 225 ARM_MAP_GPT_L1_DRAM, 226 ARM_MAP_EL3_RMM_SHARED_MEM, 227 #endif 228 #ifdef MAP_FW_NS_HANDOFF 229 MAP_FW_NS_HANDOFF, 230 #endif 231 #if defined(MAP_EL3_FW_HANDOFF) && !RESET_TO_BL31 232 MAP_EL3_FW_HANDOFF, 233 #endif 234 { 0 } 235 }; 236 237 #if defined(IMAGE_BL31) && SPM_MM 238 const mmap_region_t plat_arm_secure_partition_mmap[] = { 239 V2M_MAP_IOFPGA_EL0, /* for the UART */ 240 V2M_MAP_SECURE_SYSTEMREG_EL0, /* for initializing flash */ 241 #if PSA_FWU_SUPPORT 242 V2M_MAP_FLASH0_RW_EL0, /* for firmware update service in standalone mm */ 243 #endif 244 V2M_MAP_FLASH1_RW_EL0, /* for secure variable service in standalone mm */ 245 MAP_REGION_FLAT(DEVICE0_BASE, 246 DEVICE0_SIZE, 247 MT_DEVICE | MT_RO | MT_SECURE | MT_USER), 248 ARM_SP_IMAGE_MMAP, 249 ARM_SP_IMAGE_NS_BUF_MMAP, 250 ARM_SP_IMAGE_RW_MMAP, 251 ARM_SPM_BUF_EL0_MMAP, 252 {0} 253 }; 254 #endif 255 #endif 256 #ifdef IMAGE_BL32 257 const mmap_region_t plat_arm_mmap[] = { 258 #ifndef __aarch64__ 259 ARM_MAP_SHARED_RAM, 260 ARM_V2M_MAP_MEM_PROTECT, 261 #endif 262 V2M_MAP_IOFPGA, 263 MAP_DEVICE0, 264 #if FVP_INTERCONNECT_DRIVER == FVP_CCN 265 MAP_CCN, 266 #endif 267 MAP_DEVICE1, 268 {0} 269 }; 270 #endif 271 272 #ifdef IMAGE_RMM 273 const mmap_region_t plat_arm_mmap[] = { 274 V2M_MAP_IOFPGA, 275 MAP_DEVICE0, 276 MAP_DEVICE1, 277 {0} 278 }; 279 #endif 280 281 ARM_CASSERT_MMAP 282 283 #if FVP_INTERCONNECT_DRIVER != FVP_CCN 284 static const int fvp_cci400_map[] = { 285 PLAT_FVP_CCI400_CLUS0_SL_PORT, 286 PLAT_FVP_CCI400_CLUS1_SL_PORT, 287 }; 288 289 static const int fvp_cci5xx_map[] = { 290 PLAT_FVP_CCI5XX_CLUS0_SL_PORT, 291 PLAT_FVP_CCI5XX_CLUS1_SL_PORT, 292 }; 293 294 static unsigned int get_interconnect_master(void) 295 { 296 unsigned int master; 297 u_register_t mpidr; 298 299 mpidr = read_mpidr_el1(); 300 master = ((arm_config.flags & ARM_CONFIG_FVP_SHIFTED_AFF) != 0U) ? 301 MPIDR_AFFLVL2_VAL(mpidr) : MPIDR_AFFLVL1_VAL(mpidr); 302 303 assert(master < FVP_CLUSTER_COUNT); 304 return master; 305 } 306 #endif 307 308 #if defined(IMAGE_BL31) && SPM_MM 309 /* 310 * Boot information passed to a secure partition during initialisation. Linear 311 * indices in MP information will be filled at runtime. 312 */ 313 static spm_mm_mp_info_t sp_mp_info[] = { 314 [0] = {0x80000000, 0}, 315 [1] = {0x80000001, 0}, 316 [2] = {0x80000002, 0}, 317 [3] = {0x80000003, 0}, 318 [4] = {0x80000100, 0}, 319 [5] = {0x80000101, 0}, 320 [6] = {0x80000102, 0}, 321 [7] = {0x80000103, 0}, 322 }; 323 324 const spm_mm_boot_info_t plat_arm_secure_partition_boot_info = { 325 .h.type = PARAM_SP_IMAGE_BOOT_INFO, 326 .h.version = VERSION_1, 327 .h.size = sizeof(spm_mm_boot_info_t), 328 .h.attr = 0, 329 .sp_mem_base = ARM_SP_IMAGE_BASE, 330 .sp_mem_limit = ARM_SP_IMAGE_LIMIT, 331 .sp_image_base = ARM_SP_IMAGE_BASE, 332 .sp_stack_base = PLAT_SP_IMAGE_STACK_BASE, 333 .sp_heap_base = ARM_SP_IMAGE_HEAP_BASE, 334 .sp_ns_comm_buf_base = PLAT_SP_IMAGE_NS_BUF_BASE, 335 .sp_shared_buf_base = PLAT_SPM_BUF_BASE, 336 .sp_image_size = ARM_SP_IMAGE_SIZE, 337 .sp_pcpu_stack_size = PLAT_SP_IMAGE_STACK_PCPU_SIZE, 338 .sp_heap_size = ARM_SP_IMAGE_HEAP_SIZE, 339 .sp_ns_comm_buf_size = PLAT_SP_IMAGE_NS_BUF_SIZE, 340 .sp_shared_buf_size = PLAT_SPM_BUF_SIZE, 341 .num_sp_mem_regions = ARM_SP_IMAGE_NUM_MEM_REGIONS, 342 .num_cpus = PLATFORM_CORE_COUNT, 343 .mp_info = &sp_mp_info[0], 344 }; 345 346 const struct mmap_region *plat_get_secure_partition_mmap(void *cookie) 347 { 348 return plat_arm_secure_partition_mmap; 349 } 350 351 const struct spm_mm_boot_info *plat_get_secure_partition_boot_info( 352 void *cookie) 353 { 354 return &plat_arm_secure_partition_boot_info; 355 } 356 #endif 357 358 /******************************************************************************* 359 * A single boot loader stack is expected to work on both the Foundation FVP 360 * models and the two flavours of the Base FVP models (AEMv8 & Cortex). The 361 * SYS_ID register provides a mechanism for detecting the differences between 362 * these platforms. This information is stored in a per-BL array to allow the 363 * code to take the correct path.Per BL platform configuration. 364 ******************************************************************************/ 365 void __init fvp_config_setup(void) 366 { 367 unsigned int rev, hbi, bld, arch, sys_id; 368 369 sys_id = mmio_read_32(V2M_SYSREGS_BASE + V2M_SYS_ID); 370 rev = (sys_id >> V2M_SYS_ID_REV_SHIFT) & V2M_SYS_ID_REV_MASK; 371 hbi = (sys_id >> V2M_SYS_ID_HBI_SHIFT) & V2M_SYS_ID_HBI_MASK; 372 bld = (sys_id >> V2M_SYS_ID_BLD_SHIFT) & V2M_SYS_ID_BLD_MASK; 373 arch = (sys_id >> V2M_SYS_ID_ARCH_SHIFT) & V2M_SYS_ID_ARCH_MASK; 374 375 if (arch != ARCH_MODEL) { 376 ERROR("This firmware is for FVP models\n"); 377 panic(); 378 } 379 380 /* 381 * The build field in the SYS_ID tells which variant of the GIC 382 * memory is implemented by the model. 383 */ 384 switch (bld) { 385 case BLD_GIC_VE_MMAP: 386 ERROR("Legacy Versatile Express memory map for GIC peripheral" 387 " is not supported\n"); 388 panic(); 389 break; 390 case BLD_GIC_A53A57_MMAP: 391 break; 392 default: 393 ERROR("Unsupported board build %x\n", bld); 394 panic(); 395 } 396 397 /* 398 * The hbi field in the SYS_ID is 0x020 for the Base FVP & 0x010 399 * for the Foundation FVP. 400 */ 401 switch (hbi) { 402 case HBI_FOUNDATION_FVP: 403 arm_config.flags = 0; 404 405 /* 406 * Check for supported revisions of Foundation FVP 407 * Allow future revisions to run but emit warning diagnostic 408 */ 409 switch (rev) { 410 case REV_FOUNDATION_FVP_V2_0: 411 case REV_FOUNDATION_FVP_V2_1: 412 case REV_FOUNDATION_FVP_v9_1: 413 case REV_FOUNDATION_FVP_v9_6: 414 break; 415 default: 416 WARN("Unrecognized Foundation FVP revision %x\n", rev); 417 break; 418 } 419 break; 420 case HBI_BASE_FVP: 421 arm_config.flags |= (ARM_CONFIG_BASE_MMAP | ARM_CONFIG_HAS_TZC); 422 423 /* 424 * Check for supported revisions 425 * Allow future revisions to run but emit warning diagnostic 426 */ 427 switch (rev) { 428 case REV_BASE_FVP_V0: 429 arm_config.flags |= ARM_CONFIG_FVP_HAS_CCI400; 430 break; 431 case REV_BASE_FVP_REVC: 432 arm_config.flags |= (ARM_CONFIG_FVP_HAS_SMMUV3 | 433 ARM_CONFIG_FVP_HAS_CCI5XX); 434 break; 435 default: 436 WARN("Unrecognized Base FVP revision %x\n", rev); 437 break; 438 } 439 break; 440 default: 441 ERROR("Unsupported board HBI number 0x%x\n", hbi); 442 panic(); 443 } 444 445 /* 446 * We assume that the presence of MT bit, and therefore shifted 447 * affinities, is uniform across the platform: either all CPUs, or no 448 * CPUs implement it. 449 */ 450 if ((read_mpidr_el1() & MPIDR_MT_MASK) != 0U) 451 arm_config.flags |= ARM_CONFIG_FVP_SHIFTED_AFF; 452 } 453 454 455 void __init fvp_interconnect_init(void) 456 { 457 #if FVP_INTERCONNECT_DRIVER == FVP_CCN 458 if (ccn_get_part0_id(PLAT_ARM_CCN_BASE) != CCN_502_PART0_ID) { 459 ERROR("Unrecognized CCN variant detected. Only CCN-502 is supported"); 460 panic(); 461 } 462 463 plat_arm_interconnect_init(); 464 #else 465 uintptr_t cci_base = 0U; 466 const int *cci_map = NULL; 467 unsigned int map_size = 0U; 468 469 /* Initialize the right interconnect */ 470 if ((arm_config.flags & ARM_CONFIG_FVP_HAS_CCI5XX) != 0U) { 471 cci_base = PLAT_FVP_CCI5XX_BASE; 472 cci_map = fvp_cci5xx_map; 473 map_size = ARRAY_SIZE(fvp_cci5xx_map); 474 } else if ((arm_config.flags & ARM_CONFIG_FVP_HAS_CCI400) != 0U) { 475 cci_base = PLAT_FVP_CCI400_BASE; 476 cci_map = fvp_cci400_map; 477 map_size = ARRAY_SIZE(fvp_cci400_map); 478 } else { 479 return; 480 } 481 482 assert(cci_base != 0U); 483 assert(cci_map != NULL); 484 cci_init(cci_base, cci_map, map_size); 485 #endif 486 } 487 488 void fvp_interconnect_enable(void) 489 { 490 #if FVP_INTERCONNECT_DRIVER == FVP_CCN 491 plat_arm_interconnect_enter_coherency(); 492 #else 493 unsigned int master; 494 495 if ((arm_config.flags & (ARM_CONFIG_FVP_HAS_CCI400 | 496 ARM_CONFIG_FVP_HAS_CCI5XX)) != 0U) { 497 master = get_interconnect_master(); 498 cci_enable_snoop_dvm_reqs(master); 499 } 500 #endif 501 } 502 503 void fvp_interconnect_disable(void) 504 { 505 #if FVP_INTERCONNECT_DRIVER == FVP_CCN 506 plat_arm_interconnect_exit_coherency(); 507 #else 508 unsigned int master; 509 510 if ((arm_config.flags & (ARM_CONFIG_FVP_HAS_CCI400 | 511 ARM_CONFIG_FVP_HAS_CCI5XX)) != 0U) { 512 master = get_interconnect_master(); 513 cci_disable_snoop_dvm_reqs(master); 514 } 515 #endif 516 } 517 518 #if CRYPTO_SUPPORT 519 int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size) 520 { 521 assert(heap_addr != NULL); 522 assert(heap_size != NULL); 523 524 return arm_get_mbedtls_heap(heap_addr, heap_size); 525 } 526 #endif /* CRYPTO_SUPPORT */ 527 528 void fvp_timer_init(void) 529 { 530 #if USE_SP804_TIMER 531 /* Enable the clock override for SP804 timer 0, which means that no 532 * clock dividers are applied and the raw (35MHz) clock will be used. 533 */ 534 mmio_write_32(V2M_SP810_BASE, FVP_SP810_CTRL_TIM0_OV); 535 536 /* Initialize delay timer driver using SP804 dual timer 0 */ 537 sp804_timer_init(V2M_SP804_TIMER0_BASE, 538 SP804_TIMER_CLKMULT, SP804_TIMER_CLKDIV); 539 #else 540 generic_delay_timer_init(); 541 542 /* Enable System level generic timer */ 543 mmio_write_32(ARM_SYS_CNTCTL_BASE + CNTCR_OFF, 544 CNTCR_FCREQ(0U) | CNTCR_EN); 545 #endif /* USE_SP804_TIMER */ 546 } 547 548 /***************************************************************************** 549 * plat_is_smccc_feature_available() - This function checks whether SMCCC 550 * feature is availabile for platform. 551 * @fid: SMCCC function id 552 * 553 * Return SMC_ARCH_CALL_SUCCESS if SMCCC feature is available and 554 * SMC_ARCH_CALL_NOT_SUPPORTED otherwise. 555 *****************************************************************************/ 556 int32_t plat_is_smccc_feature_available(u_register_t fid) 557 { 558 switch (fid) { 559 case SMCCC_ARCH_SOC_ID: 560 return SMC_ARCH_CALL_SUCCESS; 561 default: 562 return SMC_ARCH_CALL_NOT_SUPPORTED; 563 } 564 } 565 566 /* Get SOC version */ 567 int32_t plat_get_soc_version(void) 568 { 569 return (int32_t) 570 (SOC_ID_SET_JEP_106(ARM_SOC_CONTINUATION_CODE, 571 ARM_SOC_IDENTIFICATION_CODE) | 572 (FVP_SOC_ID & SOC_ID_IMPL_DEF_MASK)); 573 } 574 575 /* Get SOC revision */ 576 int32_t plat_get_soc_revision(void) 577 { 578 unsigned int sys_id; 579 580 sys_id = mmio_read_32(V2M_SYSREGS_BASE + V2M_SYS_ID); 581 return (int32_t)(((sys_id >> V2M_SYS_ID_REV_SHIFT) & 582 V2M_SYS_ID_REV_MASK) & SOC_ID_REV_MASK); 583 } 584 585 #if ENABLE_RME 586 587 /* BDF mappings for RP0 RC0 */ 588 const struct bdf_mapping_info rc0rp0_bdf_data[] = { 589 /* BDF0 */ 590 {0U, /* mapping_base */ 591 0x8000U, /* mapping_top */ 592 0U, /* mapping_off */ 593 0U /* smmu_idx */ 594 } 595 }; 596 597 /* Root ports for RC0 */ 598 const struct root_port_info rc0rp_data[] = { 599 /* RP0 */ 600 {0U, /* root_port_id */ 601 0U, /* padding */ 602 ARRAY_SIZE(rc0rp0_bdf_data), /* num_bdf_mappings */ 603 (struct bdf_mapping_info *)rc0rp0_bdf_data /* bdf_mappings */ 604 } 605 }; 606 607 /* Root complexes */ 608 const struct root_complex_info rc_data[] = { 609 /* RC0 */ 610 {PCIE_EXP_BASE, /* ecam_base */ 611 0U, /* segment */ 612 {0U, 0U, 0U}, /* padding */ 613 ARRAY_SIZE(rc0rp_data), /* num_root_ports */ 614 (struct root_port_info *)rc0rp_data /* root_ports */ 615 } 616 }; 617 618 /* Number of PCIe Root Complexes */ 619 #define FVP_RMM_RC_COUNT ARRAY_SIZE(rc_data) 620 621 /* 622 * Get a pointer to the RMM-EL3 Shared buffer and return it 623 * through the pointer passed as parameter. 624 * 625 * This function returns the size of the shared buffer. 626 */ 627 size_t plat_rmmd_get_el3_rmm_shared_mem(uintptr_t *shared) 628 { 629 *shared = (uintptr_t)RMM_SHARED_BASE; 630 631 return (size_t)RMM_SHARED_SIZE; 632 } 633 634 /* 635 * Calculate checksum of 64-bit words @buffer with @size length 636 */ 637 static uint64_t checksum_calc(uint64_t *buffer, size_t size) 638 { 639 uint64_t sum = 0UL; 640 641 assert(((uintptr_t)buffer & (sizeof(uint64_t) - 1UL)) == 0UL); 642 assert((size & (sizeof(uint64_t) - 1UL)) == 0UL); 643 644 for (unsigned long i = 0UL; i < (size / sizeof(uint64_t)); i++) { 645 sum += buffer[i]; 646 } 647 648 return sum; 649 } 650 /* 651 * Boot Manifest v0.5 structure illustration, with two DRAM banks, 652 * a single console and one device memory with two PCIe device 653 * non-coherent address ranges. 654 * 655 * +--------------------------------------------------+ 656 * | offset | field | comment | 657 * +--------+--------------------+--------------------+ 658 * | 0 | version | 0x00000005 | 659 * +--------+--------------------+--------------------+ 660 * | 4 | padding | 0x00000000 | 661 * +--------+--------------------+--------------------+ 662 * | 8 | plat_data | NULL | 663 * +--------+--------------------+--------------------+ 664 * | 16 | num_banks | | 665 * +--------+--------------------+ | 666 * | 24 | banks | plat_dram +--+ 667 * +--------+--------------------+ | | 668 * | 32 | checksum | | | 669 * +--------+--------------------+--------------------+ | 670 * | 40 | num_consoles | | | 671 * +--------+--------------------+ | | 672 * | 48 | consoles | plat_console +--|--+ 673 * +--------+--------------------+ | | | 674 * | 56 | checksum | | | | 675 * +--------+--------------------+--------------------+ | | 676 * | 64 | num_banks | | | | 677 * +--------+--------------------+ | | | 678 * | 72 | banks | plat_ncoh_region +--|--|--+ 679 * +--------+--------------------+ | | | | 680 * | 80 | checksum | | | | | 681 * +--------+--------------------+--------------------+ | | | 682 * | 88 | num_banks | | | | | 683 * +--------+--------------------+ | | | | 684 * | 96 | banks | plat_coh_region | | | | 685 * +--------+--------------------+ | | | | 686 * | 104 | checksum | | | | | 687 * +--------+--------------------+--------------------+ | | | 688 * | 112 | num_smmus | | | | | 689 * +--------+--------------------+ | | | | 690 * | 120 | smmus | plat_smmu +--|--|--|--+ 691 * +--------+--------------------+ | | | | | 692 * | 128 | checksum | | | | | | 693 * +--------+--------------------+--------------------+ | | | | 694 * | 136 | num_root_complex | | | | | | 695 * +--------+--------------------+ | | | | | 696 * | 144 | rc_info_version | | | | | | 697 * +--------+--------------------+ | | | | | 698 * | 148 | padding | plat_root_complex +--|--|--|--|--+ 699 * +--------+--------------------+ | | | | | | 700 * | 152 | root_complex | | | | | | | 701 * +--------+--------------------+ | | | | | | 702 * | 160 | checksum | | | | | | | 703 * +--------+--------------------+--------------------+<-+ | | | | 704 * | 168 | base 0 | | | | | | 705 * +--------+--------------------+ mem_bank[0] | | | | | 706 * | 176 | size 0 | | | | | | 707 * +--------+--------------------+--------------------+ | | | | 708 * | 184 | base 1 | | | | | | 709 * +--------+--------------------+ mem_bank[1] | | | | | 710 * | 192 | size 1 | | | | | | 711 * +--------+--------------------+--------------------+<----+ | | | 712 * | 200 | base | | | | | 713 * +--------+--------------------+ | | | | 714 * | 208 | map_pages | | | | | 715 * +--------+--------------------+ | | | | 716 * | 216 | name | | | | | 717 * +--------+--------------------+ consoles[0] | | | | 718 * | 224 | clk_in_hz | | | | | 719 * +--------+--------------------+ | | | | 720 * | 232 | baud_rate | | | | | 721 * +--------+--------------------+ | | | | 722 * | 240 | flags | | | | | 723 * +--------+--------------------+--------------------+<-------+ | | 724 * | 248 | base 0 | | | | 725 * +--------+--------------------+ ncoh_region[0] | | | 726 * | 256 | size 0 | | | | 727 * +--------+--------------------+--------------------+ | | 728 * | 264 | base 1 | | | | 729 * +--------+--------------------+ ncoh_region[1] | | | 730 * | 272 | size 1 | | | | 731 * +--------+--------------------+--------------------+<----------+ | 732 * | 280 | smmu_base | | | 733 * +--------+--------------------+ smmus[0] | | 734 * | 288 | smmu_r_base | | | 735 * +--------+--------------------+--------------------+<-------------+ 736 * | 296 | ecam_base | | 737 * +--------+--------------------+ | 738 * | 304 | segment | | 739 * +--------+--------------------+ | 740 * | 305 | padding | root_complex[0] +--+ 741 * +--------+--------------------+ | | 742 * | 308 | num_root_ports | | | 743 * +--------+--------------------+ | | 744 * | 312 | root_ports | | | 745 * +--------+--------------------+--------------------+<-+ 746 * | 320 | root_port_id | | 747 * +--------+--------------------+ | 748 * | 322 | padding | | 749 * +--------+--------------------+ root_ports[0] +--+ 750 * | 324 | num_bdf_mappings | | | 751 * +--------+--------------------+ | | 752 * | 328 | bdf_mappings | | | 753 * +--------+--------------------+--------------------+<-+ 754 * | 336 | mapping_base | | 755 * +--------+--------------------+ | 756 * | 338 | mapping_top | | 757 * +--------+--------------------+ bdf_mappings[0] | 758 * | 340 | mapping_off | | 759 * +--------+--------------------+ | 760 * | 342 | smmu_idx | | 761 * +--------+--------------------+--------------------+ 762 */ 763 int plat_rmmd_load_manifest(struct rmm_manifest *manifest) 764 { 765 uint64_t checksum, num_banks, num_consoles; 766 uint64_t num_ncoh_regions, num_coh_regions; 767 uint64_t num_smmus, num_root_complex; 768 unsigned int num_root_ports, num_bdf_mappings; 769 uint32_t o_realm; 770 struct memory_bank *bank_ptr, *ncoh_region_ptr, *coh_region_ptr; 771 struct console_info *console_ptr; 772 struct smmu_info *smmu_ptr; 773 struct root_complex_info *root_complex_ptr, *rc_ptr; 774 struct root_port_info *root_port_ptr, *rp_ptr; 775 struct bdf_mapping_info *bdf_mapping_ptr, *bdf_ptr; 776 777 assert(manifest != NULL); 778 779 /* Get number of DRAM banks */ 780 num_banks = FCONF_GET_PROPERTY(hw_config, dram_layout, num_banks); 781 assert(num_banks <= ARM_DRAM_NUM_BANKS); 782 783 /* Set number of consoles */ 784 num_consoles = FVP_RMM_CONSOLE_COUNT; 785 786 /* Set number of device non-coherent address ranges for FVP RevC */ 787 num_ncoh_regions = 2; 788 789 /* Set number of SMMUs */ 790 num_smmus = FVP_RMM_SMMU_COUNT; 791 792 /* Set number of PCIe root complexes */ 793 num_root_complex = FVP_RMM_RC_COUNT; 794 795 /* Calculate and set number of all PCIe root ports and BDF mappings */ 796 num_root_ports = 0U; 797 num_bdf_mappings = 0U; 798 799 /* Scan all root complex entries */ 800 for (unsigned long i = 0UL; i < num_root_complex; i++) { 801 num_root_ports += rc_data[i].num_root_ports; 802 803 /* Scan all root ports entries in root complex */ 804 for (unsigned int j = 0U; j < rc_data[i].num_root_ports; j++) { 805 num_bdf_mappings += rc_data[i].root_ports[j].num_bdf_mappings; 806 } 807 } 808 809 manifest->version = RMMD_MANIFEST_VERSION; 810 manifest->padding = 0U; /* RES0 */ 811 manifest->plat_data = 0UL; 812 manifest->plat_dram.num_banks = num_banks; 813 manifest->plat_console.num_consoles = num_consoles; 814 manifest->plat_ncoh_region.num_banks = num_ncoh_regions; 815 manifest->plat_smmu.num_smmus = num_smmus; 816 manifest->plat_root_complex.num_root_complex = num_root_complex; 817 manifest->plat_root_complex.rc_info_version = PCIE_RC_INFO_VERSION; 818 manifest->plat_root_complex.padding = 0U; /* RES0 */ 819 820 /* FVP does not support device coherent address ranges */ 821 num_coh_regions = 0UL; 822 manifest->plat_coh_region.num_banks = num_coh_regions; 823 manifest->plat_coh_region.banks = NULL; 824 manifest->plat_coh_region.checksum = 0UL; 825 826 bank_ptr = (struct memory_bank *) 827 (((uintptr_t)manifest) + sizeof(struct rmm_manifest)); 828 console_ptr = (struct console_info *) 829 ((uintptr_t)bank_ptr + (num_banks * 830 sizeof(struct memory_bank))); 831 ncoh_region_ptr = (struct memory_bank *) 832 ((uintptr_t)console_ptr + (num_consoles * 833 sizeof(struct console_info))); 834 coh_region_ptr = (struct memory_bank *) 835 ((uintptr_t)ncoh_region_ptr + (num_ncoh_regions * 836 sizeof(struct memory_bank))); 837 smmu_ptr = (struct smmu_info *) 838 ((uintptr_t)coh_region_ptr + (num_coh_regions * 839 sizeof(struct memory_bank))); 840 root_complex_ptr = (struct root_complex_info *) 841 ((uintptr_t)smmu_ptr + (num_smmus * 842 sizeof(struct smmu_info))); 843 root_port_ptr = (struct root_port_info *) 844 ((uintptr_t)root_complex_ptr + (num_root_complex * 845 sizeof(struct root_complex_info))); 846 bdf_mapping_ptr = (struct bdf_mapping_info *) 847 ((uintptr_t)root_port_ptr + (num_root_ports * 848 sizeof(struct root_port_info))); 849 850 manifest->plat_dram.banks = bank_ptr; 851 manifest->plat_console.consoles = console_ptr; 852 manifest->plat_ncoh_region.banks = ncoh_region_ptr; 853 manifest->plat_smmu.smmus = smmu_ptr; 854 manifest->plat_root_complex.root_complex = root_complex_ptr; 855 856 /* Ensure the manifest is not larger than the shared buffer */ 857 assert((sizeof(struct rmm_manifest) + 858 (sizeof(struct memory_bank) * 859 manifest->plat_dram.num_banks) + 860 (sizeof(struct console_info) * 861 manifest->plat_console.num_consoles) + 862 (sizeof(struct memory_bank) * 863 manifest->plat_ncoh_region.num_banks) + 864 (sizeof(struct memory_bank) * 865 manifest->plat_coh_region.num_banks) + 866 (sizeof(struct smmu_info) * 867 manifest->plat_smmu.num_smmus) + 868 (sizeof(struct root_complex_info) * 869 manifest->plat_root_complex.num_root_complex) + 870 (sizeof(struct root_port_info) * num_root_ports) + 871 (sizeof(struct bdf_mapping_info) * num_bdf_mappings)) 872 <= ARM_EL3_RMM_SHARED_SIZE); 873 874 /* Calculate checksum of plat_dram structure */ 875 checksum = num_banks + (uint64_t)bank_ptr; 876 877 /* Store FVP DRAM banks data in Boot Manifest */ 878 for (unsigned long i = 0UL; i < num_banks; i++) { 879 bank_ptr[i].base = FCONF_GET_PROPERTY(hw_config, dram_layout, dram_bank[i].base); 880 bank_ptr[i].size = FCONF_GET_PROPERTY(hw_config, dram_layout, dram_bank[i].size); 881 } 882 883 /* Update checksum */ 884 checksum += checksum_calc((uint64_t *)bank_ptr, sizeof(struct memory_bank) * num_banks); 885 886 /* Checksum must be 0 */ 887 manifest->plat_dram.checksum = ~checksum + 1UL; 888 889 /* Calculate the checksum of plat_consoles structure */ 890 checksum = num_consoles + (uint64_t)console_ptr; 891 892 /* Zero out the console info struct */ 893 (void)memset((void *)console_ptr, '\0', 894 sizeof(struct console_info) * num_consoles); 895 896 console_ptr[0].base = FVP_RMM_CONSOLE_BASE; 897 console_ptr[0].map_pages = 1UL; 898 console_ptr[0].clk_in_hz = FVP_RMM_CONSOLE_CLK_IN_HZ; 899 console_ptr[0].baud_rate = FVP_RMM_CONSOLE_BAUD; 900 901 (void)strlcpy(console_ptr[0].name, FVP_RMM_CONSOLE_NAME, 902 RMM_CONSOLE_MAX_NAME_LEN - 1UL); 903 904 /* Update checksum */ 905 checksum += checksum_calc((uint64_t *)console_ptr, 906 sizeof(struct console_info) * num_consoles); 907 /* Checksum must be 0 */ 908 manifest->plat_console.checksum = ~checksum + 1UL; 909 910 /* 911 * Calculate the checksum of device non-coherent address ranges 912 * info structure 913 */ 914 checksum = num_ncoh_regions + (uint64_t)ncoh_region_ptr; 915 916 /* Zero out the PCIe region info struct */ 917 (void)memset((void *)ncoh_region_ptr, 0, 918 sizeof(struct memory_bank) * num_ncoh_regions); 919 920 /* Set number of device non-coherent address ranges based on DT */ 921 num_ncoh_regions = FCONF_GET_PROPERTY(hw_config, pci_props, num_ncoh_regions); 922 /* At least 1 PCIe region need to be described in DT */ 923 assert((num_ncoh_regions > 0) && (num_ncoh_regions <= 2)); 924 925 for (unsigned long i = 0UL; i < num_ncoh_regions; i++) { 926 ncoh_region_ptr[i].base = 927 FCONF_GET_PROPERTY(hw_config, pci_props, ncoh_regions[i].base); 928 ncoh_region_ptr[i].size = 929 FCONF_GET_PROPERTY(hw_config, pci_props, ncoh_regions[i].size); 930 } 931 932 /* 933 * Workaround if the DT does not specify the 2nd PCIe region. This code can be 934 * removed when upstream DT is updated to have 2nd PCIe region. 935 */ 936 if (num_ncoh_regions == 1) { 937 num_ncoh_regions++; 938 /* Add 3GB of 2nd PCIe region */ 939 ncoh_region_ptr[1].base = 0x4000000000; 940 ncoh_region_ptr[1].size = 0xc0000000; 941 } 942 943 /* Update checksum */ 944 checksum += checksum_calc((uint64_t *)ncoh_region_ptr, 945 sizeof(struct memory_bank) * num_ncoh_regions); 946 947 /* Checksum must be 0 */ 948 manifest->plat_ncoh_region.checksum = ~checksum + 1UL; 949 950 /* Calculate the checksum of the plat_smmu structure */ 951 checksum = num_smmus + (uint64_t)smmu_ptr; 952 953 smmu_ptr[0].smmu_base = FVP_RMM_SMMU_BASE; 954 955 /* Read SMMU_ROOT_IDR0.BA_REALM[31:22] register field */ 956 o_realm = mmio_read_32(FVP_RMM_SMMU_BASE + SMMU_ROOT_IDR0) & 957 SMMU_ROOT_IDR0_BA_REALM_MASK; 958 /* 959 * Calculate the base address offset of Realm Register Page 0. 960 * O_REALM = 0x20000 + (BA_REALM * 0x10000) 961 * SMMU_REALM_BASE = SMMU_PAGE_0_BASE + O_REALM 962 */ 963 o_realm = 0x20000 + (o_realm >> (SMMU_ROOT_IDR0_BA_REALM_SHIFT - 16U)); 964 965 smmu_ptr[0].smmu_r_base = FVP_RMM_SMMU_BASE + o_realm; 966 967 /* Update checksum */ 968 checksum += checksum_calc((uint64_t *)smmu_ptr, 969 sizeof(struct smmu_info) * num_smmus); 970 /* Checksum must be 0 */ 971 manifest->plat_smmu.checksum = ~checksum + 1UL; 972 973 /* Calculate the checksum of the plat_root_complex structure */ 974 checksum = num_root_complex + (uint64_t)root_complex_ptr; 975 976 /* Zero out PCIe root complex info structures */ 977 (void)memset((void *)root_complex_ptr, 0, 978 sizeof(struct root_complex_info) * num_root_complex); 979 980 /* Set pointers for data in manifest */ 981 rc_ptr = root_complex_ptr; 982 rp_ptr = root_port_ptr; 983 bdf_ptr = bdf_mapping_ptr; 984 985 /* Fill PCIe root complex info structures */ 986 for (unsigned long i = 0U; i < num_root_complex; i++) { 987 const struct root_complex_info *rc_info = &rc_data[i]; 988 const struct root_port_info *rp_info = rc_info->root_ports; 989 990 /* Copy root complex data, except root_ports pointer */ 991 (void)memcpy((void *)rc_ptr, (void *)rc_info, 992 sizeof(struct root_complex_info) - sizeof(struct root_port_info *)); 993 994 /* Set root_ports for root complex */ 995 rc_ptr->root_ports = rp_ptr; 996 997 /* Scan root ports */ 998 for (unsigned int j = 0U; j < rc_ptr->num_root_ports; j++) { 999 const struct bdf_mapping_info *bdf_info = rp_info->bdf_mappings; 1000 1001 /* Copy root port data, except bdf_mappings pointer */ 1002 (void)memcpy((void *)rp_ptr, (void *)rp_info, 1003 sizeof(struct root_port_info) - sizeof(struct bdf_mapping_info *)); 1004 1005 /* Set bdf_mappings for root port */ 1006 rp_ptr->bdf_mappings = bdf_ptr; 1007 1008 /* Copy all BDF mappings for root port */ 1009 (void)memcpy((void *)bdf_ptr, (void *)bdf_info, 1010 sizeof(struct bdf_mapping_info) * rp_ptr->num_bdf_mappings); 1011 1012 bdf_ptr += rp_ptr->num_bdf_mappings; 1013 rp_ptr++; 1014 rp_info++; 1015 } 1016 rc_ptr++; 1017 } 1018 1019 /* Check that all data are written in manifest */ 1020 assert(rc_ptr == (root_complex_ptr + num_root_complex)); 1021 assert(rp_ptr == (root_port_ptr + num_root_ports)); 1022 assert(bdf_ptr == (bdf_mapping_ptr + num_bdf_mappings)); 1023 1024 /* Update checksum for all PCIe data */ 1025 checksum += checksum_calc((uint64_t *)root_complex_ptr, 1026 (uintptr_t)bdf_ptr - (uintptr_t)root_complex_ptr); 1027 1028 /* Checksum must be 0 */ 1029 manifest->plat_root_complex.checksum = ~checksum + 1UL; 1030 1031 return 0; 1032 } 1033 1034 /* 1035 * Update encryption key associated with @mecid. 1036 */ 1037 int plat_rmmd_mecid_key_update(uint16_t mecid) 1038 { 1039 /* 1040 * FVP does not provide an interface to change the encryption key associated 1041 * with MECID. Hence always return success. 1042 */ 1043 return 0; 1044 } 1045 #endif /* ENABLE_RME */ 1046