1# 2# Copyright (c) 2023-2024, Linaro Limited and Contributors. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7include lib/libfdt/libfdt.mk 8include common/fdt_wrappers.mk 9 10PLAT_INCLUDES := -Iinclude/plat/arm/common/ \ 11 -I${PLAT_QEMU_COMMON_PATH}/ \ 12 -I${PLAT_QEMU_COMMON_PATH}/include \ 13 -I${PLAT_QEMU_PATH}/include \ 14 -Iinclude/common/tbbr 15 16ifeq (${ARCH},aarch32) 17QEMU_CPU_LIBS := lib/cpus/${ARCH}/cortex_a15.S 18else 19QEMU_CPU_LIBS := lib/cpus/aarch64/aem_generic.S \ 20 lib/cpus/aarch64/cortex_a53.S \ 21 lib/cpus/aarch64/cortex_a55.S \ 22 lib/cpus/aarch64/cortex_a57.S \ 23 lib/cpus/aarch64/cortex_a72.S \ 24 lib/cpus/aarch64/cortex_a76.S \ 25 lib/cpus/aarch64/cortex_a710.S \ 26 lib/cpus/aarch64/neoverse_n_common.S \ 27 lib/cpus/aarch64/neoverse_n1.S \ 28 lib/cpus/aarch64/neoverse_v1.S \ 29 lib/cpus/aarch64/neoverse_n2.S \ 30 lib/cpus/aarch64/qemu_max.S 31 32PLAT_INCLUDES += -Iinclude/plat/arm/common/${ARCH} 33endif 34 35PLAT_BL_COMMON_SOURCES := ${PLAT_QEMU_COMMON_PATH}/qemu_common.c \ 36 ${PLAT_QEMU_COMMON_PATH}/qemu_console.c \ 37 drivers/arm/pl011/${ARCH}/pl011_console.S 38 39include lib/xlat_tables_v2/xlat_tables.mk 40PLAT_BL_COMMON_SOURCES += ${XLAT_TABLES_LIB_SRCS} 41 42ifneq ($(ENABLE_STACK_PROTECTOR), 0) 43 PLAT_BL_COMMON_SOURCES += ${PLAT_QEMU_COMMON_PATH}/qemu_stack_protector.c 44endif 45 46BL1_SOURCES += drivers/io/io_semihosting.c \ 47 drivers/io/io_storage.c \ 48 drivers/io/io_fip.c \ 49 drivers/io/io_memmap.c \ 50 lib/semihosting/semihosting.c \ 51 lib/semihosting/${ARCH}/semihosting_call.S \ 52 ${PLAT_QEMU_COMMON_PATH}/qemu_io_storage.c \ 53 ${PLAT_QEMU_COMMON_PATH}/${ARCH}/plat_helpers.S \ 54 ${PLAT_QEMU_COMMON_PATH}/qemu_bl1_setup.c \ 55 ${QEMU_CPU_LIBS} 56 57BL2_SOURCES += drivers/io/io_semihosting.c \ 58 drivers/io/io_storage.c \ 59 drivers/io/io_fip.c \ 60 drivers/io/io_memmap.c \ 61 lib/semihosting/semihosting.c \ 62 lib/semihosting/${ARCH}/semihosting_call.S \ 63 ${PLAT_QEMU_COMMON_PATH}/qemu_io_storage.c \ 64 ${PLAT_QEMU_COMMON_PATH}/${ARCH}/plat_helpers.S \ 65 ${PLAT_QEMU_COMMON_PATH}/qemu_bl2_setup.c \ 66 ${PLAT_QEMU_COMMON_PATH}/qemu_bl2_mem_params_desc.c \ 67 ${PLAT_QEMU_COMMON_PATH}/qemu_image_load.c \ 68 common/desc_image_load.c \ 69 common/fdt_fixup.c \ 70 ${FDT_WRAPPERS_SOURCES} 71 72BL31_SOURCES += ${QEMU_CPU_LIBS} \ 73 lib/semihosting/semihosting.c \ 74 lib/semihosting/${ARCH}/semihosting_call.S \ 75 plat/common/plat_psci_common.c \ 76 ${PLAT_QEMU_COMMON_PATH}/aarch64/plat_helpers.S \ 77 ${PLAT_QEMU_COMMON_PATH}/qemu_bl31_setup.c \ 78 common/fdt_fixup.c \ 79 ${QEMU_GIC_SOURCES} 80 81# CPU flag enablement 82ifeq (${ARCH},aarch64) 83 84# Cpu core architecture level: 85# v8.0: a53, a57, a72 86# v8.2: a55, a76, n1 87# v8.4: v1 88# v9.0: a710, n2 89# 90# 91# We go v8.0 by default and will enable all features we want 92 93ARM_ARCH_MAJOR ?= 8 94ARM_ARCH_MINOR ?= 0 95 96# 8.0 97ENABLE_FEAT_CSV2_2 := 2 98 99# 8.1 100ENABLE_FEAT_PAN := 2 101ENABLE_FEAT_VHE := 2 102 103# 8.2 104# TF-A currently does not permit dynamic detection of FEAT_RAS 105# so this is the only safe setting 106ENABLE_FEAT_RAS := 0 107 108# 8.4 109ENABLE_FEAT_SEL2 := 2 110ENABLE_FEAT_DIT := 2 111ENABLE_TRF_FOR_NS := 2 112 113# 8.5 114ENABLE_FEAT_RNG := 2 115# TF-A currently does not do dynamic detection of FEAT_SB. 116# Compiler puts SB instruction when it is enabled. 117ENABLE_FEAT_SB := 0 118 119# 8.6 120ENABLE_FEAT_ECV := 2 121ENABLE_FEAT_FGT := 2 122 123# 8.7 124ENABLE_FEAT_HCX := 2 125 126# SPM_MM is not compatible with ENABLE_SVE_FOR_NS (build breaks) 127ifeq (${SPM_MM},1) 128 ENABLE_SVE_FOR_NS := 0 129 ENABLE_SME_FOR_NS := 0 130else 131 ENABLE_SVE_FOR_NS := 2 132 ENABLE_SME_FOR_NS := 2 133endif 134 135ifeq (${ENABLE_RME},1) 136BL31_SOURCES += plat/qemu/common/qemu_plat_attest_token.c \ 137 plat/qemu/common/qemu_realm_attest_key.c 138endif 139 140# Treating this as a memory-constrained port for now 141USE_COHERENT_MEM := 0 142 143# This can be overridden depending on CPU(s) used in the QEMU image 144HW_ASSISTED_COHERENCY := 1 145 146CTX_INCLUDE_AARCH32_REGS := 0 147ifeq (${CTX_INCLUDE_AARCH32_REGS}, 1) 148$(error "This is an AArch64-only port; CTX_INCLUDE_AARCH32_REGS must be disabled") 149endif 150 151# Pointer Authentication sources 152ifeq ($(BRANCH_PROTECTION),$(filter $(BRANCH_PROTECTION),1 2 3)) 153PLAT_BL_COMMON_SOURCES += plat/arm/common/aarch64/arm_pauth.c 154endif 155 156endif 157