1 /* 2 * Copyright (C) 2021-2024, STMicroelectronics - All Rights Reserved 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef DDRPHY_PHYINIT_USERCUSTOM_H 8 #define DDRPHY_PHYINIT_USERCUSTOM_H 9 10 #include <stdbool.h> 11 #include <stdint.h> 12 13 #include <ddrphy_csr_all_cdefines.h> 14 15 #include <drivers/st/stm32mp2_ddr.h> 16 17 /* Message Block Structure Definitions */ 18 #if STM32MP_DDR3_TYPE 19 #include <mnpmusrammsgblock_ddr3.h> 20 #elif STM32MP_DDR4_TYPE 21 #include <mnpmusrammsgblock_ddr4.h> 22 #else /* STM32MP_LPDDR4_TYPE */ 23 #include <mnpmusrammsgblock_lpddr4.h> 24 #endif /* STM32MP_DDR3_TYPE */ 25 26 /* 27 * ------------------------------------------------------------- 28 * Defines for Firmware Images 29 * - indicate IMEM/DMEM address, size (bytes) and offsets. 30 * ------------------------------------------------------------- 31 * 32 * IMEM_SIZE max size of instruction memory. 33 * DMEM_SIZE max size of data memory. 34 * 35 * IMEM_ST_ADDR start of IMEM address in memory. 36 * DMEM_ST_ADDR start of DMEM address in memory. 37 * DMEM_BIN_OFFSET start offset in DMEM memory (message block). 38 */ 39 #if STM32MP_DDR3_TYPE 40 #define IMEM_SIZE 0x4C28U 41 #define DMEM_SIZE 0x6C8U 42 #elif STM32MP_DDR4_TYPE 43 #define IMEM_SIZE 0x6D24U 44 #define DMEM_SIZE 0x6CCU 45 #else /* STM32MP_LPDDR4_TYPE */ 46 #define IMEM_SIZE 0x7E50U 47 #define DMEM_SIZE 0x67CU 48 #endif /* STM32MP_DDR3_TYPE */ 49 #define IMEM_ST_ADDR 0x50000U 50 #define DMEM_ST_ADDR 0x54000U 51 #define DMEM_BIN_OFFSET 0x200U 52 53 /* 54 * ------------------ 55 * Type definitions 56 * ------------------ 57 */ 58 59 /* A structure used to SRAM memory address space */ 60 enum return_offset_lastaddr { 61 RETURN_OFFSET, 62 RETURN_LASTADDR 63 }; 64 65 /* Enumeration of instructions for PhyInit Register Interface */ 66 enum reginstr { 67 STARTTRACK, /* Start register tracking */ 68 STOPTRACK, /* Stop register tracking */ 69 SAVEREGS, /* Save(read) tracked register values */ 70 RESTOREREGS, /* Restore (write) saved register values */ 71 }; 72 73 /* Data structure to store register address/value pairs */ 74 struct reg_addr_val { 75 uint32_t address; /* Register address */ 76 uint16_t value; /* Register value */ 77 }; 78 79 /* Target CSR for the impedance value for ddrphy_phyinit_mapdrvstren() */ 80 enum drvtype { 81 DRVSTRENFSDQP, 82 DRVSTRENFSDQN, 83 ODTSTRENP, 84 ODTSTRENN, 85 ADRVSTRENP, 86 ADRVSTRENN 87 }; 88 89 /* 90 * ------------------------------------------------------------- 91 * Fixed Function prototypes 92 * ------------------------------------------------------------- 93 */ 94 int ddrphy_phyinit_sequence(struct stm32mp_ddr_config *config, bool skip_training, bool reten); 95 int ddrphy_phyinit_restore_sequence(void); 96 int ddrphy_phyinit_c_initphyconfig(struct stm32mp_ddr_config *config, 97 struct pmu_smb_ddr_1d *mb_ddr_1d, uint32_t *ardptrinitval); 98 void ddrphy_phyinit_d_loadimem(void); 99 void ddrphy_phyinit_progcsrskiptrain(struct stm32mp_ddr_config *config, 100 struct pmu_smb_ddr_1d *mb_ddr_1d, uint32_t ardptrinitval); 101 int ddrphy_phyinit_f_loaddmem(struct stm32mp_ddr_config *config, struct pmu_smb_ddr_1d *mb_ddr_1d); 102 int ddrphy_phyinit_g_execfw(void); 103 void ddrphy_phyinit_i_loadpieimage(struct stm32mp_ddr_config *config, bool skip_training); 104 void ddrphy_phyinit_loadpieprodcode(void); 105 int ddrphy_phyinit_mapdrvstren(uint32_t drvstren_ohm, enum drvtype targetcsr); 106 int ddrphy_phyinit_calcmb(struct stm32mp_ddr_config *config, struct pmu_smb_ddr_1d *mb_ddr_1d); 107 void ddrphy_phyinit_writeoutmem(uint32_t *mem, uint32_t mem_offset, uint32_t mem_size); 108 void ddrphy_phyinit_writeoutmsgblk(uint16_t *mem, uint32_t mem_offset, uint32_t mem_size); 109 int ddrphy_phyinit_isdbytedisabled(struct stm32mp_ddr_config *config, 110 struct pmu_smb_ddr_1d *mb_ddr_1d, uint32_t dbytenumber); 111 int ddrphy_phyinit_trackreg(uint32_t adr); 112 int ddrphy_phyinit_reginterface(enum reginstr myreginstr, uint32_t adr, uint16_t dat); 113 114 void ddrphy_phyinit_usercustom_custompretrain(struct stm32mp_ddr_config *config); 115 int ddrphy_phyinit_usercustom_g_waitfwdone(void); 116 int ddrphy_phyinit_usercustom_saveretregs(struct stm32mp_ddr_config *config); 117 118 #endif /* DDRPHY_PHYINIT_USERCUSTOM_H */ 119