1 /* 2 * Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved. 4 * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #include <common/debug.h> 10 #include <common/runtime_svc.h> 11 #include <drivers/generic_delay_timer.h> 12 #include <lib/mmio.h> 13 #include <lib/xlat_tables/xlat_tables_v2.h> 14 #include <plat/common/platform.h> 15 16 #include <def.h> 17 #include <plat_common.h> 18 #include <plat_ipi.h> 19 #include <plat_private.h> 20 21 uint32_t platform_id, platform_version; 22 23 /* 24 * Table of regions to map using the MMU. 25 * This doesn't include TZRAM as the 'mem_layout' argument passed to 26 * configure_mmu_elx() will give the available subset of that, 27 */ 28 const mmap_region_t plat_mmap[] = { 29 MAP_REGION_FLAT(DEVICE0_BASE, DEVICE0_SIZE, MT_DEVICE | MT_RW | MT_SECURE), 30 MAP_REGION_FLAT(DEVICE1_BASE, DEVICE1_SIZE, MT_DEVICE | MT_RW | MT_SECURE), 31 MAP_REGION_FLAT(DEVICE2_BASE, DEVICE2_SIZE, MT_DEVICE | MT_RW | MT_SECURE), 32 MAP_REGION_FLAT(CRF_BASE, CRF_SIZE, MT_DEVICE | MT_RW | MT_SECURE), 33 MAP_REGION_FLAT(IPI_BASE, IPI_SIZE, MT_DEVICE | MT_RW | MT_SECURE), 34 #if TRANSFER_LIST 35 MAP_REGION_FLAT(FW_HANDOFF_BASE, FW_HANDOFF_BASE + FW_HANDOFF_SIZE, 36 MT_MEMORY | MT_RW | MT_NS), 37 #endif 38 { 0 } 39 }; 40 41 const mmap_region_t *plat_get_mmap(void) 42 { 43 return plat_mmap; 44 } 45 46 /* For saving cpu clock for certain platform */ 47 uint32_t cpu_clock; 48 49 const char *board_name_decode(void) 50 { 51 const char *platform; 52 53 switch (platform_id) { 54 case SPP: 55 platform = "IPP"; 56 break; 57 case EMU: 58 platform = "EMU"; 59 break; 60 case SILICON: 61 platform = "Silicon"; 62 break; 63 case QEMU: 64 platform = "QEMU"; 65 break; 66 default: 67 platform = "Unknown"; 68 } 69 70 return platform; 71 } 72 73 void board_detection(void) 74 { 75 uint32_t version_type; 76 77 version_type = mmio_read_32(PMC_TAP_VERSION); 78 platform_id = FIELD_GET(PLATFORM_MASK, version_type); 79 platform_version = FIELD_GET(PLATFORM_VERSION_MASK, version_type); 80 81 if (platform_id == QEMU_COSIM) { 82 platform_id = QEMU; 83 } 84 85 /* Make sure that console is setup to see this message */ 86 VERBOSE("Platform id: %d version: %d.%d\n", platform_id, 87 platform_version / 10U, platform_version % 10U); 88 } 89 90 uint32_t get_uart_clk(void) 91 { 92 uint32_t uart_clock = 0; 93 94 switch (platform_id) { 95 case SPP: 96 case SPP_MMD: 97 uart_clock = cpu_clock; 98 break; 99 case EMU: 100 case EMU_MMD: 101 uart_clock = 25000000; 102 break; 103 case QEMU: 104 /* Random values now */ 105 uart_clock = 25000000; 106 break; 107 case SILICON: 108 uart_clock = 100000000; 109 break; 110 default: 111 panic(); 112 } 113 114 return uart_clock; 115 } 116 117 void config_setup(void) 118 { 119 uint32_t val; 120 uintptr_t crl_base, iou_scntrs_base, psx_base; 121 122 crl_base = CRL; 123 iou_scntrs_base = IOU_SCNTRS; 124 psx_base = PSX_CRF; 125 126 /* Reset for system timestamp generator in FPX */ 127 mmio_write_32(psx_base + PSX_CRF_RST_TIMESTAMP_OFFSET, 0); 128 129 /* Global timer init - Program time stamp reference clk */ 130 val = mmio_read_32(crl_base + CRL_TIMESTAMP_REF_CTRL_OFFSET); 131 val |= CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT; 132 mmio_write_32(crl_base + CRL_TIMESTAMP_REF_CTRL_OFFSET, val); 133 134 /* Clear reset of timestamp reg */ 135 mmio_write_32(crl_base + CRL_RST_TIMESTAMP_OFFSET, 0); 136 137 /* Program freq register in System counter and enable system counter. */ 138 mmio_write_32(iou_scntrs_base + IOU_SCNTRS_BASE_FREQ_OFFSET, 139 cpu_clock); 140 mmio_write_32(iou_scntrs_base + IOU_SCNTRS_COUNTER_CONTROL_REG_OFFSET, 141 IOU_SCNTRS_CONTROL_EN); 142 143 generic_delay_timer_init(); 144 145 /* Configure IPI data */ 146 soc_ipi_config_table_init(); 147 } 148 149 uint32_t plat_get_syscnt_freq2(void) 150 { 151 return cpu_clock; 152 } 153