1 /* 2 * Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2022, NVIDIA Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <assert.h> 9 #include <stdbool.h> 10 #include <string.h> 11 12 #include <platform_def.h> 13 14 #include <arch.h> 15 #include <arch_helpers.h> 16 #include <arch_features.h> 17 #include <bl31/interrupt_mgmt.h> 18 #include <common/bl_common.h> 19 #include <common/debug.h> 20 #include <context.h> 21 #include <drivers/arm/gicv3.h> 22 #include <lib/cpus/cpu_ops.h> 23 #include <lib/cpus/errata.h> 24 #include <lib/el3_runtime/context_mgmt.h> 25 #include <lib/el3_runtime/cpu_data.h> 26 #include <lib/el3_runtime/pubsub_events.h> 27 #include <lib/extensions/amu.h> 28 #include <lib/extensions/brbe.h> 29 #include <lib/extensions/debug_v8p9.h> 30 #include <lib/extensions/fgt2.h> 31 #include <lib/extensions/mpam.h> 32 #include <lib/extensions/pmuv3.h> 33 #include <lib/extensions/sme.h> 34 #include <lib/extensions/spe.h> 35 #include <lib/extensions/sve.h> 36 #include <lib/extensions/sysreg128.h> 37 #include <lib/extensions/sys_reg_trace.h> 38 #include <lib/extensions/tcr2.h> 39 #include <lib/extensions/trbe.h> 40 #include <lib/extensions/trf.h> 41 #include <lib/utils.h> 42 43 #if ENABLE_FEAT_TWED 44 /* Make sure delay value fits within the range(0-15) */ 45 CASSERT(((TWED_DELAY & ~SCR_TWEDEL_MASK) == 0U), assert_twed_delay_value_check); 46 #endif /* ENABLE_FEAT_TWED */ 47 48 per_world_context_t per_world_context[CPU_DATA_CONTEXT_NUM]; 49 static bool has_secure_perworld_init; 50 51 static void manage_extensions_common(cpu_context_t *ctx); 52 static void manage_extensions_nonsecure(cpu_context_t *ctx); 53 static void manage_extensions_secure(cpu_context_t *ctx); 54 static void manage_extensions_secure_per_world(void); 55 56 #if ((IMAGE_BL1) || (IMAGE_BL31 && (!CTX_INCLUDE_EL2_REGS))) 57 static void setup_el1_context(cpu_context_t *ctx, const struct entry_point_info *ep) 58 { 59 u_register_t sctlr_elx, actlr_elx; 60 61 /* 62 * Initialise SCTLR_EL1 to the reset value corresponding to the target 63 * execution state setting all fields rather than relying on the hw. 64 * Some fields have architecturally UNKNOWN reset values and these are 65 * set to zero. 66 * 67 * SCTLR.EE: Endianness is taken from the entrypoint attributes. 68 * 69 * SCTLR.M, SCTLR.C and SCTLR.I: These fields must be zero (as 70 * required by PSCI specification) 71 */ 72 sctlr_elx = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0UL; 73 if (GET_RW(ep->spsr) == MODE_RW_64) { 74 sctlr_elx |= SCTLR_EL1_RES1; 75 } else { 76 /* 77 * If the target execution state is AArch32 then the following 78 * fields need to be set. 79 * 80 * SCTRL_EL1.nTWE: Set to one so that EL0 execution of WFE 81 * instructions are not trapped to EL1. 82 * 83 * SCTLR_EL1.nTWI: Set to one so that EL0 execution of WFI 84 * instructions are not trapped to EL1. 85 * 86 * SCTLR_EL1.CP15BEN: Set to one to enable EL0 execution of the 87 * CP15DMB, CP15DSB, and CP15ISB instructions. 88 */ 89 sctlr_elx |= SCTLR_AARCH32_EL1_RES1 | SCTLR_CP15BEN_BIT 90 | SCTLR_NTWI_BIT | SCTLR_NTWE_BIT; 91 } 92 93 /* 94 * If workaround of errata 764081 for Cortex-A75 is used then set 95 * SCTLR_EL1.IESB to enable Implicit Error Synchronization Barrier. 96 */ 97 if (errata_a75_764081_applies()) { 98 sctlr_elx |= SCTLR_IESB_BIT; 99 } 100 101 /* Store the initialised SCTLR_EL1 value in the cpu_context */ 102 write_ctx_sctlr_el1_reg_errata(ctx, sctlr_elx); 103 104 /* 105 * Base the context ACTLR_EL1 on the current value, as it is 106 * implementation defined. The context restore process will write 107 * the value from the context to the actual register and can cause 108 * problems for processor cores that don't expect certain bits to 109 * be zero. 110 */ 111 actlr_elx = read_actlr_el1(); 112 write_el1_ctx_common(get_el1_sysregs_ctx(ctx), actlr_el1, actlr_elx); 113 } 114 #endif /* (IMAGE_BL1) || (IMAGE_BL31 && (!CTX_INCLUDE_EL2_REGS)) */ 115 116 /****************************************************************************** 117 * This function performs initializations that are specific to SECURE state 118 * and updates the cpu context specified by 'ctx'. 119 *****************************************************************************/ 120 static void setup_secure_context(cpu_context_t *ctx, const struct entry_point_info *ep) 121 { 122 u_register_t scr_el3; 123 el3_state_t *state; 124 125 state = get_el3state_ctx(ctx); 126 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 127 128 #if defined(IMAGE_BL31) && !defined(SPD_spmd) 129 /* 130 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 131 * indicated by the interrupt routing model for BL31. 132 */ 133 scr_el3 |= get_scr_el3_from_routing_model(SECURE); 134 #endif 135 136 /* Allow access to Allocation Tags when FEAT_MTE2 is implemented and enabled. */ 137 if (is_feat_mte2_supported()) { 138 scr_el3 |= SCR_ATA_BIT; 139 } 140 141 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 142 143 /* 144 * Initialize EL1 context registers unless SPMC is running 145 * at S-EL2. 146 */ 147 #if (!SPMD_SPM_AT_SEL2) 148 setup_el1_context(ctx, ep); 149 #endif 150 151 manage_extensions_secure(ctx); 152 153 /** 154 * manage_extensions_secure_per_world api has to be executed once, 155 * as the registers getting initialised, maintain constant value across 156 * all the cpus for the secure world. 157 * Henceforth, this check ensures that the registers are initialised once 158 * and avoids re-initialization from multiple cores. 159 */ 160 if (!has_secure_perworld_init) { 161 manage_extensions_secure_per_world(); 162 } 163 } 164 165 #if ENABLE_RME 166 /****************************************************************************** 167 * This function performs initializations that are specific to REALM state 168 * and updates the cpu context specified by 'ctx'. 169 *****************************************************************************/ 170 static void setup_realm_context(cpu_context_t *ctx, const struct entry_point_info *ep) 171 { 172 u_register_t scr_el3; 173 el3_state_t *state; 174 175 state = get_el3state_ctx(ctx); 176 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 177 178 scr_el3 |= SCR_NS_BIT | SCR_NSE_BIT; 179 180 /* CSV2 version 2 and above */ 181 if (is_feat_csv2_2_supported()) { 182 /* Enable access to the SCXTNUM_ELx registers. */ 183 scr_el3 |= SCR_EnSCXT_BIT; 184 } 185 186 if (is_feat_sctlr2_supported()) { 187 /* Set the SCTLR2En bit in SCR_EL3 to enable access to 188 * SCTLR2_ELx registers. 189 */ 190 scr_el3 |= SCR_SCTLR2En_BIT; 191 } 192 193 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 194 } 195 #endif /* ENABLE_RME */ 196 197 /****************************************************************************** 198 * This function performs initializations that are specific to NON-SECURE state 199 * and updates the cpu context specified by 'ctx'. 200 *****************************************************************************/ 201 static void setup_ns_context(cpu_context_t *ctx, const struct entry_point_info *ep) 202 { 203 u_register_t scr_el3; 204 el3_state_t *state; 205 206 state = get_el3state_ctx(ctx); 207 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 208 209 /* SCR_NS: Set the NS bit */ 210 scr_el3 |= SCR_NS_BIT; 211 212 /* Allow access to Allocation Tags when FEAT_MTE2 is implemented and enabled. */ 213 if (is_feat_mte2_supported()) { 214 scr_el3 |= SCR_ATA_BIT; 215 } 216 217 #if !CTX_INCLUDE_PAUTH_REGS 218 /* 219 * Pointer Authentication feature, if present, is always enabled by default 220 * for Non secure lower exception levels. We do not have an explicit 221 * flag to set it. 222 * CTX_INCLUDE_PAUTH_REGS flag, is explicitly used to enable for lower 223 * exception levels of secure and realm worlds. 224 * 225 * To prevent the leakage between the worlds during world switch, 226 * we enable it only for the non-secure world. 227 * 228 * If the Secure/realm world wants to use pointer authentication, 229 * CTX_INCLUDE_PAUTH_REGS must be explicitly set to 1, in which case 230 * it will be enabled globally for all the contexts. 231 * 232 * SCR_EL3.API: Set to one to not trap any PAuth instructions at ELs 233 * other than EL3 234 * 235 * SCR_EL3.APK: Set to one to not trap any PAuth key values at ELs other 236 * than EL3 237 */ 238 scr_el3 |= SCR_API_BIT | SCR_APK_BIT; 239 240 #endif /* CTX_INCLUDE_PAUTH_REGS */ 241 242 #if HANDLE_EA_EL3_FIRST_NS 243 /* SCR_EL3.EA: Route External Abort and SError Interrupt to EL3. */ 244 scr_el3 |= SCR_EA_BIT; 245 #endif 246 247 #if RAS_TRAP_NS_ERR_REC_ACCESS 248 /* 249 * SCR_EL3.TERR: Trap Error record accesses. Accesses to the RAS ERR 250 * and RAS ERX registers from EL1 and EL2(from any security state) 251 * are trapped to EL3. 252 * Set here to trap only for NS EL1/EL2 253 * 254 */ 255 scr_el3 |= SCR_TERR_BIT; 256 #endif 257 258 /* CSV2 version 2 and above */ 259 if (is_feat_csv2_2_supported()) { 260 /* Enable access to the SCXTNUM_ELx registers. */ 261 scr_el3 |= SCR_EnSCXT_BIT; 262 } 263 264 #ifdef IMAGE_BL31 265 /* 266 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 267 * indicated by the interrupt routing model for BL31. 268 */ 269 scr_el3 |= get_scr_el3_from_routing_model(NON_SECURE); 270 #endif 271 272 if (is_feat_the_supported()) { 273 /* Set the RCWMASKEn bit in SCR_EL3 to enable access to 274 * RCWMASK_EL1 and RCWSMASK_EL1 registers. 275 */ 276 scr_el3 |= SCR_RCWMASKEn_BIT; 277 } 278 279 if (is_feat_sctlr2_supported()) { 280 /* Set the SCTLR2En bit in SCR_EL3 to enable access to 281 * SCTLR2_ELx registers. 282 */ 283 scr_el3 |= SCR_SCTLR2En_BIT; 284 } 285 286 if (is_feat_d128_supported()) { 287 /* Set the D128En bit in SCR_EL3 to enable access to 128-bit 288 * versions of TTBR0_EL1, TTBR1_EL1, RCWMASK_EL1, RCWSMASK_EL1, 289 * PAR_EL1 and TTBR1_EL2, TTBR0_EL2 and VTTBR_EL2 registers. 290 */ 291 scr_el3 |= SCR_D128En_BIT; 292 } 293 294 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 295 296 /* Initialize EL2 context registers */ 297 #if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) 298 299 /* 300 * Initialize SCTLR_EL2 context register with reset value. 301 */ 302 write_el2_ctx_common(get_el2_sysregs_ctx(ctx), sctlr_el2, SCTLR_EL2_RES1); 303 304 if (is_feat_hcx_supported()) { 305 /* 306 * Initialize register HCRX_EL2 with its init value. 307 * As the value of HCRX_EL2 is UNKNOWN on reset, there is a 308 * chance that this can lead to unexpected behavior in lower 309 * ELs that have not been updated since the introduction of 310 * this feature if not properly initialized, especially when 311 * it comes to those bits that enable/disable traps. 312 */ 313 write_el2_ctx_hcx(get_el2_sysregs_ctx(ctx), hcrx_el2, 314 HCRX_EL2_INIT_VAL); 315 } 316 317 if (is_feat_fgt_supported()) { 318 /* 319 * Initialize HFG*_EL2 registers with a default value so legacy 320 * systems unaware of FEAT_FGT do not get trapped due to their lack 321 * of initialization for this feature. 322 */ 323 write_el2_ctx_fgt(get_el2_sysregs_ctx(ctx), hfgitr_el2, 324 HFGITR_EL2_INIT_VAL); 325 write_el2_ctx_fgt(get_el2_sysregs_ctx(ctx), hfgrtr_el2, 326 HFGRTR_EL2_INIT_VAL); 327 write_el2_ctx_fgt(get_el2_sysregs_ctx(ctx), hfgwtr_el2, 328 HFGWTR_EL2_INIT_VAL); 329 } 330 #else 331 /* Initialize EL1 context registers */ 332 setup_el1_context(ctx, ep); 333 #endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */ 334 335 manage_extensions_nonsecure(ctx); 336 } 337 338 /******************************************************************************* 339 * The following function performs initialization of the cpu_context 'ctx' 340 * for first use that is common to all security states, and sets the 341 * initial entrypoint state as specified by the entry_point_info structure. 342 * 343 * The EE and ST attributes are used to configure the endianness and secure 344 * timer availability for the new execution context. 345 ******************************************************************************/ 346 static void setup_context_common(cpu_context_t *ctx, const entry_point_info_t *ep) 347 { 348 u_register_t scr_el3; 349 u_register_t mdcr_el3; 350 el3_state_t *state; 351 gp_regs_t *gp_regs; 352 353 state = get_el3state_ctx(ctx); 354 355 /* Clear any residual register values from the context */ 356 zeromem(ctx, sizeof(*ctx)); 357 358 /* 359 * The lower-EL context is zeroed so that no stale values leak to a world. 360 * It is assumed that an all-zero lower-EL context is good enough for it 361 * to boot correctly. However, there are very few registers where this 362 * is not true and some values need to be recreated. 363 */ 364 #if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) 365 el2_sysregs_t *el2_ctx = get_el2_sysregs_ctx(ctx); 366 367 /* 368 * These bits are set in the gicv3 driver. Losing them (especially the 369 * SRE bit) is problematic for all worlds. Henceforth recreate them. 370 */ 371 u_register_t icc_sre_el2_val = ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT | 372 ICC_SRE_EN_BIT | ICC_SRE_SRE_BIT; 373 write_el2_ctx_common(el2_ctx, icc_sre_el2, icc_sre_el2_val); 374 375 /* 376 * The actlr_el2 register can be initialized in platform's reset handler 377 * and it may contain access control bits (e.g. CLUSTERPMUEN bit). 378 */ 379 write_el2_ctx_common(el2_ctx, actlr_el2, read_actlr_el2()); 380 #endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */ 381 382 /* Start with a clean SCR_EL3 copy as all relevant values are set */ 383 scr_el3 = SCR_RESET_VAL; 384 385 /* 386 * SCR_EL3.TWE: Set to zero so that execution of WFE instructions at 387 * EL2, EL1 and EL0 are not trapped to EL3. 388 * 389 * SCR_EL3.TWI: Set to zero so that execution of WFI instructions at 390 * EL2, EL1 and EL0 are not trapped to EL3. 391 * 392 * SCR_EL3.SMD: Set to zero to enable SMC calls at EL1 and above, from 393 * both Security states and both Execution states. 394 * 395 * SCR_EL3.SIF: Set to one to disable secure instruction execution from 396 * Non-secure memory. 397 */ 398 scr_el3 &= ~(SCR_TWE_BIT | SCR_TWI_BIT | SCR_SMD_BIT); 399 400 scr_el3 |= SCR_SIF_BIT; 401 402 /* 403 * SCR_EL3.RW: Set the execution state, AArch32 or AArch64, for next 404 * Exception level as specified by SPSR. 405 */ 406 if (GET_RW(ep->spsr) == MODE_RW_64) { 407 scr_el3 |= SCR_RW_BIT; 408 } 409 410 /* 411 * SCR_EL3.ST: Traps Secure EL1 accesses to the Counter-timer Physical 412 * Secure timer registers to EL3, from AArch64 state only, if specified 413 * by the entrypoint attributes. If SEL2 is present and enabled, the ST 414 * bit always behaves as 1 (i.e. secure physical timer register access 415 * is not trapped) 416 */ 417 if (EP_GET_ST(ep->h.attr) != 0U) { 418 scr_el3 |= SCR_ST_BIT; 419 } 420 421 /* 422 * If FEAT_HCX is enabled, enable access to HCRX_EL2 by setting 423 * SCR_EL3.HXEn. 424 */ 425 if (is_feat_hcx_supported()) { 426 scr_el3 |= SCR_HXEn_BIT; 427 } 428 429 /* 430 * If FEAT_LS64_ACCDATA is enabled, enable access to ACCDATA_EL1 by 431 * setting SCR_EL3.ADEn and allow the ST64BV0 instruction by setting 432 * SCR_EL3.EnAS0. 433 */ 434 if (is_feat_ls64_accdata_supported()) { 435 scr_el3 |= SCR_ADEn_BIT | SCR_EnAS0_BIT; 436 } 437 438 /* 439 * If FEAT_RNG_TRAP is enabled, all reads of the RNDR and RNDRRS 440 * registers are trapped to EL3. 441 */ 442 #if ENABLE_FEAT_RNG_TRAP 443 scr_el3 |= SCR_TRNDR_BIT; 444 #endif 445 446 #if FAULT_INJECTION_SUPPORT 447 /* Enable fault injection from lower ELs */ 448 scr_el3 |= SCR_FIEN_BIT; 449 #endif 450 451 #if CTX_INCLUDE_PAUTH_REGS 452 /* 453 * Enable Pointer Authentication globally for all the worlds. 454 * 455 * SCR_EL3.API: Set to one to not trap any PAuth instructions at ELs 456 * other than EL3 457 * 458 * SCR_EL3.APK: Set to one to not trap any PAuth key values at ELs other 459 * than EL3 460 */ 461 scr_el3 |= SCR_API_BIT | SCR_APK_BIT; 462 #endif /* CTX_INCLUDE_PAUTH_REGS */ 463 464 /* 465 * SCR_EL3.TCR2EN: Enable access to TCR2_ELx for AArch64 if present. 466 */ 467 if (is_feat_tcr2_supported() && (GET_RW(ep->spsr) == MODE_RW_64)) { 468 scr_el3 |= SCR_TCR2EN_BIT; 469 } 470 471 /* 472 * SCR_EL3.PIEN: Enable permission indirection and overlay 473 * registers for AArch64 if present. 474 */ 475 if (is_feat_sxpie_supported() || is_feat_sxpoe_supported()) { 476 scr_el3 |= SCR_PIEN_BIT; 477 } 478 479 /* 480 * SCR_EL3.GCSEn: Enable GCS registers for AArch64 if present. 481 */ 482 if ((is_feat_gcs_supported()) && (GET_RW(ep->spsr) == MODE_RW_64)) { 483 scr_el3 |= SCR_GCSEn_BIT; 484 } 485 486 /* 487 * SCR_EL3.HCE: Enable HVC instructions if next execution state is 488 * AArch64 and next EL is EL2, or if next execution state is AArch32 and 489 * next mode is Hyp. 490 * SCR_EL3.FGTEn: Enable Fine Grained Virtualization Traps under the 491 * same conditions as HVC instructions and when the processor supports 492 * ARMv8.6-FGT. 493 * SCR_EL3.ECVEn: Enable Enhanced Counter Virtualization (ECV) 494 * CNTPOFF_EL2 register under the same conditions as HVC instructions 495 * and when the processor supports ECV. 496 */ 497 if (((GET_RW(ep->spsr) == MODE_RW_64) && (GET_EL(ep->spsr) == MODE_EL2)) 498 || ((GET_RW(ep->spsr) != MODE_RW_64) 499 && (GET_M32(ep->spsr) == MODE32_hyp))) { 500 scr_el3 |= SCR_HCE_BIT; 501 502 if (is_feat_fgt_supported()) { 503 scr_el3 |= SCR_FGTEN_BIT; 504 } 505 506 if (is_feat_ecv_supported()) { 507 scr_el3 |= SCR_ECVEN_BIT; 508 } 509 } 510 511 /* Enable WFE trap delay in SCR_EL3 if supported and configured */ 512 if (is_feat_twed_supported()) { 513 /* Set delay in SCR_EL3 */ 514 scr_el3 &= ~(SCR_TWEDEL_MASK << SCR_TWEDEL_SHIFT); 515 scr_el3 |= ((TWED_DELAY & SCR_TWEDEL_MASK) 516 << SCR_TWEDEL_SHIFT); 517 518 /* Enable WFE delay */ 519 scr_el3 |= SCR_TWEDEn_BIT; 520 } 521 522 #if IMAGE_BL31 && defined(SPD_spmd) && SPMD_SPM_AT_SEL2 523 /* Enable S-EL2 if FEAT_SEL2 is implemented for all the contexts. */ 524 if (is_feat_sel2_supported()) { 525 scr_el3 |= SCR_EEL2_BIT; 526 } 527 #endif /* (IMAGE_BL31 && defined(SPD_spmd) && SPMD_SPM_AT_SEL2) */ 528 529 /* 530 * Populate EL3 state so that we've the right context 531 * before doing ERET 532 */ 533 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 534 write_ctx_reg(state, CTX_ELR_EL3, ep->pc); 535 write_ctx_reg(state, CTX_SPSR_EL3, ep->spsr); 536 537 /* Start with a clean MDCR_EL3 copy as all relevant values are set */ 538 mdcr_el3 = MDCR_EL3_RESET_VAL; 539 540 /* --------------------------------------------------------------------- 541 * Initialise MDCR_EL3, setting all fields rather than relying on hw. 542 * Some fields are architecturally UNKNOWN on reset. 543 * 544 * MDCR_EL3.SDD: Set to one to disable AArch64 Secure self-hosted debug. 545 * Debug exceptions, other than Breakpoint Instruction exceptions, are 546 * disabled from all ELs in Secure state. 547 * 548 * MDCR_EL3.SPD32: Set to 0b10 to disable AArch32 Secure self-hosted 549 * privileged debug from S-EL1. 550 * 551 * MDCR_EL3.TDOSA: Set to zero so that EL2 and EL2 System register 552 * access to the powerdown debug registers do not trap to EL3. 553 * 554 * MDCR_EL3.TDA: Set to zero to allow EL0, EL1 and EL2 access to the 555 * debug registers, other than those registers that are controlled by 556 * MDCR_EL3.TDOSA. 557 */ 558 mdcr_el3 |= ((MDCR_SDD_BIT | MDCR_SPD32(MDCR_SPD32_DISABLE)) 559 & ~(MDCR_TDA_BIT | MDCR_TDOSA_BIT)) ; 560 write_ctx_reg(state, CTX_MDCR_EL3, mdcr_el3); 561 562 /* 563 * Configure MDCR_EL3 register as applicable for each world 564 * (NS/Secure/Realm) context. 565 */ 566 manage_extensions_common(ctx); 567 568 /* 569 * Store the X0-X7 value from the entrypoint into the context 570 * Use memcpy as we are in control of the layout of the structures 571 */ 572 gp_regs = get_gpregs_ctx(ctx); 573 memcpy(gp_regs, (void *)&ep->args, sizeof(aapcs64_params_t)); 574 } 575 576 /******************************************************************************* 577 * Context management library initialization routine. This library is used by 578 * runtime services to share pointers to 'cpu_context' structures for secure 579 * non-secure and realm states. Management of the structures and their associated 580 * memory is not done by the context management library e.g. the PSCI service 581 * manages the cpu context used for entry from and exit to the non-secure state. 582 * The Secure payload dispatcher service manages the context(s) corresponding to 583 * the secure state. It also uses this library to get access to the non-secure 584 * state cpu context pointers. 585 * Lastly, this library provides the API to make SP_EL3 point to the cpu context 586 * which will be used for programming an entry into a lower EL. The same context 587 * will be used to save state upon exception entry from that EL. 588 ******************************************************************************/ 589 void __init cm_init(void) 590 { 591 /* 592 * The context management library has only global data to initialize, but 593 * that will be done when the BSS is zeroed out. 594 */ 595 } 596 597 /******************************************************************************* 598 * This is the high-level function used to initialize the cpu_context 'ctx' for 599 * first use. It performs initializations that are common to all security states 600 * and initializations specific to the security state specified in 'ep' 601 ******************************************************************************/ 602 void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep) 603 { 604 unsigned int security_state; 605 606 assert(ctx != NULL); 607 608 /* 609 * Perform initializations that are common 610 * to all security states 611 */ 612 setup_context_common(ctx, ep); 613 614 security_state = GET_SECURITY_STATE(ep->h.attr); 615 616 /* Perform security state specific initializations */ 617 switch (security_state) { 618 case SECURE: 619 setup_secure_context(ctx, ep); 620 break; 621 #if ENABLE_RME 622 case REALM: 623 setup_realm_context(ctx, ep); 624 break; 625 #endif 626 case NON_SECURE: 627 setup_ns_context(ctx, ep); 628 break; 629 default: 630 ERROR("Invalid security state\n"); 631 panic(); 632 break; 633 } 634 } 635 636 /******************************************************************************* 637 * Enable architecture extensions for EL3 execution. This function only updates 638 * registers in-place which are expected to either never change or be 639 * overwritten by el3_exit. 640 ******************************************************************************/ 641 #if IMAGE_BL31 642 void cm_manage_extensions_el3(void) 643 { 644 if (is_feat_amu_supported()) { 645 amu_init_el3(); 646 } 647 648 if (is_feat_sme_supported()) { 649 sme_init_el3(); 650 } 651 652 pmuv3_init_el3(); 653 } 654 #endif /* IMAGE_BL31 */ 655 656 /****************************************************************************** 657 * Function to initialise the registers with the RESET values in the context 658 * memory, which are maintained per world. 659 ******************************************************************************/ 660 #if IMAGE_BL31 661 void cm_el3_arch_init_per_world(per_world_context_t *per_world_ctx) 662 { 663 /* 664 * Initialise CPTR_EL3, setting all fields rather than relying on hw. 665 * 666 * CPTR_EL3.TFP: Set to zero so that accesses to the V- or Z- registers 667 * by Advanced SIMD, floating-point or SVE instructions (if 668 * implemented) do not trap to EL3. 669 * 670 * CPTR_EL3.TCPAC: Set to zero so that accesses to CPACR_EL1, 671 * CPTR_EL2,CPACR, or HCPTR do not trap to EL3. 672 */ 673 uint64_t cptr_el3 = CPTR_EL3_RESET_VAL & ~(TCPAC_BIT | TFP_BIT); 674 675 per_world_ctx->ctx_cptr_el3 = cptr_el3; 676 677 /* 678 * Initialize MPAM3_EL3 to its default reset value 679 * 680 * MPAM3_EL3_RESET_VAL sets the MPAM3_EL3.TRAPLOWER bit that forces 681 * all lower ELn MPAM3_EL3 register access to, trap to EL3 682 */ 683 684 per_world_ctx->ctx_mpam3_el3 = MPAM3_EL3_RESET_VAL; 685 } 686 #endif /* IMAGE_BL31 */ 687 688 /******************************************************************************* 689 * Initialise per_world_context for Non-Secure world. 690 * This function enables the architecture extensions, which have same value 691 * across the cores for the non-secure world. 692 ******************************************************************************/ 693 #if IMAGE_BL31 694 void manage_extensions_nonsecure_per_world(void) 695 { 696 cm_el3_arch_init_per_world(&per_world_context[CPU_CONTEXT_NS]); 697 698 if (is_feat_sme_supported()) { 699 sme_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 700 } 701 702 if (is_feat_sve_supported()) { 703 sve_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 704 } 705 706 if (is_feat_amu_supported()) { 707 amu_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 708 } 709 710 if (is_feat_sys_reg_trace_supported()) { 711 sys_reg_trace_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 712 } 713 714 if (is_feat_mpam_supported()) { 715 mpam_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 716 } 717 } 718 #endif /* IMAGE_BL31 */ 719 720 /******************************************************************************* 721 * Initialise per_world_context for Secure world. 722 * This function enables the architecture extensions, which have same value 723 * across the cores for the secure world. 724 ******************************************************************************/ 725 static void manage_extensions_secure_per_world(void) 726 { 727 #if IMAGE_BL31 728 cm_el3_arch_init_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 729 730 if (is_feat_sme_supported()) { 731 732 if (ENABLE_SME_FOR_SWD) { 733 /* 734 * Enable SME, SVE, FPU/SIMD in secure context, SPM must ensure 735 * SME, SVE, and FPU/SIMD context properly managed. 736 */ 737 sme_enable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 738 } else { 739 /* 740 * Disable SME, SVE, FPU/SIMD in secure context so non-secure 741 * world can safely use the associated registers. 742 */ 743 sme_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 744 } 745 } 746 if (is_feat_sve_supported()) { 747 if (ENABLE_SVE_FOR_SWD) { 748 /* 749 * Enable SVE and FPU in secure context, SPM must ensure 750 * that the SVE and FPU register contexts are properly managed. 751 */ 752 sve_enable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 753 } else { 754 /* 755 * Disable SVE and FPU in secure context so non-secure world 756 * can safely use them. 757 */ 758 sve_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 759 } 760 } 761 762 /* NS can access this but Secure shouldn't */ 763 if (is_feat_sys_reg_trace_supported()) { 764 sys_reg_trace_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 765 } 766 767 has_secure_perworld_init = true; 768 #endif /* IMAGE_BL31 */ 769 } 770 771 /******************************************************************************* 772 * Enable architecture extensions on first entry to Non-secure world only 773 * and disable for secure world. 774 * 775 * NOTE: Arch features which have been provided with the capability of getting 776 * enabled only for non-secure world and being disabled for secure world are 777 * grouped here, as the MDCR_EL3 context value remains same across the worlds. 778 ******************************************************************************/ 779 static void manage_extensions_common(cpu_context_t *ctx) 780 { 781 #if IMAGE_BL31 782 if (is_feat_spe_supported()) { 783 /* 784 * Enable FEAT_SPE for Non-Secure and prohibit for Secure state. 785 */ 786 spe_enable(ctx); 787 } 788 789 if (is_feat_trbe_supported()) { 790 /* 791 * Enable FEAT_TRBE for Non-Secure and prohibit for Secure and 792 * Realm state. 793 */ 794 trbe_enable(ctx); 795 } 796 797 if (is_feat_trf_supported()) { 798 /* 799 * Enable FEAT_TRF for Non-Secure and prohibit for Secure state. 800 */ 801 trf_enable(ctx); 802 } 803 #endif /* IMAGE_BL31 */ 804 } 805 806 /******************************************************************************* 807 * Enable architecture extensions on first entry to Non-secure world. 808 ******************************************************************************/ 809 static void manage_extensions_nonsecure(cpu_context_t *ctx) 810 { 811 #if IMAGE_BL31 812 if (is_feat_amu_supported()) { 813 amu_enable(ctx); 814 } 815 816 if (is_feat_sme_supported()) { 817 sme_enable(ctx); 818 } 819 820 if (is_feat_fgt2_supported()) { 821 fgt2_enable(ctx); 822 } 823 824 if (is_feat_debugv8p9_supported()) { 825 debugv8p9_extended_bp_wp_enable(ctx); 826 } 827 828 if (is_feat_brbe_supported()) { 829 brbe_enable(ctx); 830 } 831 832 pmuv3_enable(ctx); 833 #endif /* IMAGE_BL31 */ 834 } 835 836 /* TODO: move to lib/extensions/pauth when it has been ported to FEAT_STATE */ 837 static __unused void enable_pauth_el2(void) 838 { 839 u_register_t hcr_el2 = read_hcr_el2(); 840 /* 841 * For Armv8.3 pointer authentication feature, disable traps to EL2 when 842 * accessing key registers or using pointer authentication instructions 843 * from lower ELs. 844 */ 845 hcr_el2 |= (HCR_API_BIT | HCR_APK_BIT); 846 847 write_hcr_el2(hcr_el2); 848 } 849 850 #if INIT_UNUSED_NS_EL2 851 /******************************************************************************* 852 * Enable architecture extensions in-place at EL2 on first entry to Non-secure 853 * world when EL2 is empty and unused. 854 ******************************************************************************/ 855 static void manage_extensions_nonsecure_el2_unused(void) 856 { 857 #if IMAGE_BL31 858 if (is_feat_spe_supported()) { 859 spe_init_el2_unused(); 860 } 861 862 if (is_feat_amu_supported()) { 863 amu_init_el2_unused(); 864 } 865 866 if (is_feat_mpam_supported()) { 867 mpam_init_el2_unused(); 868 } 869 870 if (is_feat_trbe_supported()) { 871 trbe_init_el2_unused(); 872 } 873 874 if (is_feat_sys_reg_trace_supported()) { 875 sys_reg_trace_init_el2_unused(); 876 } 877 878 if (is_feat_trf_supported()) { 879 trf_init_el2_unused(); 880 } 881 882 pmuv3_init_el2_unused(); 883 884 if (is_feat_sve_supported()) { 885 sve_init_el2_unused(); 886 } 887 888 if (is_feat_sme_supported()) { 889 sme_init_el2_unused(); 890 } 891 892 #if ENABLE_PAUTH 893 enable_pauth_el2(); 894 #endif /* ENABLE_PAUTH */ 895 #endif /* IMAGE_BL31 */ 896 } 897 #endif /* INIT_UNUSED_NS_EL2 */ 898 899 /******************************************************************************* 900 * Enable architecture extensions on first entry to Secure world. 901 ******************************************************************************/ 902 static void manage_extensions_secure(cpu_context_t *ctx) 903 { 904 #if IMAGE_BL31 905 if (is_feat_sme_supported()) { 906 if (ENABLE_SME_FOR_SWD) { 907 /* 908 * Enable SME, SVE, FPU/SIMD in secure context, secure manager 909 * must ensure SME, SVE, and FPU/SIMD context properly managed. 910 */ 911 sme_init_el3(); 912 sme_enable(ctx); 913 } else { 914 /* 915 * Disable SME, SVE, FPU/SIMD in secure context so non-secure 916 * world can safely use the associated registers. 917 */ 918 sme_disable(ctx); 919 } 920 } 921 #endif /* IMAGE_BL31 */ 922 } 923 924 #if !IMAGE_BL1 925 /******************************************************************************* 926 * The following function initializes the cpu_context for a CPU specified by 927 * its `cpu_idx` for first use, and sets the initial entrypoint state as 928 * specified by the entry_point_info structure. 929 ******************************************************************************/ 930 void cm_init_context_by_index(unsigned int cpu_idx, 931 const entry_point_info_t *ep) 932 { 933 cpu_context_t *ctx; 934 ctx = cm_get_context_by_index(cpu_idx, GET_SECURITY_STATE(ep->h.attr)); 935 cm_setup_context(ctx, ep); 936 } 937 #endif /* !IMAGE_BL1 */ 938 939 /******************************************************************************* 940 * The following function initializes the cpu_context for the current CPU 941 * for first use, and sets the initial entrypoint state as specified by the 942 * entry_point_info structure. 943 ******************************************************************************/ 944 void cm_init_my_context(const entry_point_info_t *ep) 945 { 946 cpu_context_t *ctx; 947 ctx = cm_get_context(GET_SECURITY_STATE(ep->h.attr)); 948 cm_setup_context(ctx, ep); 949 } 950 951 /* EL2 present but unused, need to disable safely. SCTLR_EL2 can be ignored */ 952 static void init_nonsecure_el2_unused(cpu_context_t *ctx) 953 { 954 #if INIT_UNUSED_NS_EL2 955 u_register_t hcr_el2 = HCR_RESET_VAL; 956 u_register_t mdcr_el2; 957 u_register_t scr_el3; 958 959 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3); 960 961 /* Set EL2 register width: Set HCR_EL2.RW to match SCR_EL3.RW */ 962 if ((scr_el3 & SCR_RW_BIT) != 0U) { 963 hcr_el2 |= HCR_RW_BIT; 964 } 965 966 write_hcr_el2(hcr_el2); 967 968 /* 969 * Initialise CPTR_EL2 setting all fields rather than relying on the hw. 970 * All fields have architecturally UNKNOWN reset values. 971 */ 972 write_cptr_el2(CPTR_EL2_RESET_VAL); 973 974 /* 975 * Initialise CNTHCTL_EL2. All fields are architecturally UNKNOWN on 976 * reset and are set to zero except for field(s) listed below. 977 * 978 * CNTHCTL_EL2.EL1PTEN: Set to one to disable traps to Hyp mode of 979 * Non-secure EL0 and EL1 accesses to the physical timer registers. 980 * 981 * CNTHCTL_EL2.EL1PCTEN: Set to one to disable traps to Hyp mode of 982 * Non-secure EL0 and EL1 accesses to the physical counter registers. 983 */ 984 write_cnthctl_el2(CNTHCTL_RESET_VAL | EL1PCEN_BIT | EL1PCTEN_BIT); 985 986 /* 987 * Initialise CNTVOFF_EL2 to zero as it resets to an architecturally 988 * UNKNOWN value. 989 */ 990 write_cntvoff_el2(0); 991 992 /* 993 * Set VPIDR_EL2 and VMPIDR_EL2 to match MIDR_EL1 and MPIDR_EL1 994 * respectively. 995 */ 996 write_vpidr_el2(read_midr_el1()); 997 write_vmpidr_el2(read_mpidr_el1()); 998 999 /* 1000 * Initialise VTTBR_EL2. All fields are architecturally UNKNOWN on reset. 1001 * 1002 * VTTBR_EL2.VMID: Set to zero. Even though EL1&0 stage 2 address 1003 * translation is disabled, cache maintenance operations depend on the 1004 * VMID. 1005 * 1006 * VTTBR_EL2.BADDR: Set to zero as EL1&0 stage 2 address translation is 1007 * disabled. 1008 */ 1009 write_vttbr_el2(VTTBR_RESET_VAL & 1010 ~((VTTBR_VMID_MASK << VTTBR_VMID_SHIFT) | 1011 (VTTBR_BADDR_MASK << VTTBR_BADDR_SHIFT))); 1012 1013 /* 1014 * Initialise MDCR_EL2, setting all fields rather than relying on hw. 1015 * Some fields are architecturally UNKNOWN on reset. 1016 * 1017 * MDCR_EL2.TDRA: Set to zero so that Non-secure EL0 and EL1 System 1018 * register accesses to the Debug ROM registers are not trapped to EL2. 1019 * 1020 * MDCR_EL2.TDOSA: Set to zero so that Non-secure EL1 System register 1021 * accesses to the powerdown debug registers are not trapped to EL2. 1022 * 1023 * MDCR_EL2.TDA: Set to zero so that System register accesses to the 1024 * debug registers do not trap to EL2. 1025 * 1026 * MDCR_EL2.TDE: Set to zero so that debug exceptions are not routed to 1027 * EL2. 1028 */ 1029 mdcr_el2 = MDCR_EL2_RESET_VAL & 1030 ~(MDCR_EL2_TDRA_BIT | MDCR_EL2_TDOSA_BIT | MDCR_EL2_TDA_BIT | 1031 MDCR_EL2_TDE_BIT); 1032 1033 write_mdcr_el2(mdcr_el2); 1034 1035 /* 1036 * Initialise HSTR_EL2. All fields are architecturally UNKNOWN on reset. 1037 * 1038 * HSTR_EL2.T<n>: Set all these fields to zero so that Non-secure EL0 or 1039 * EL1 accesses to System registers do not trap to EL2. 1040 */ 1041 write_hstr_el2(HSTR_EL2_RESET_VAL & ~(HSTR_EL2_T_MASK)); 1042 1043 /* 1044 * Initialise CNTHP_CTL_EL2. All fields are architecturally UNKNOWN on 1045 * reset. 1046 * 1047 * CNTHP_CTL_EL2:ENABLE: Set to zero to disable the EL2 physical timer 1048 * and prevent timer interrupts. 1049 */ 1050 write_cnthp_ctl_el2(CNTHP_CTL_RESET_VAL & ~(CNTHP_CTL_ENABLE_BIT)); 1051 1052 manage_extensions_nonsecure_el2_unused(); 1053 #endif /* INIT_UNUSED_NS_EL2 */ 1054 } 1055 1056 /******************************************************************************* 1057 * Prepare the CPU system registers for first entry into realm, secure, or 1058 * normal world. 1059 * 1060 * If execution is requested to EL2 or hyp mode, SCTLR_EL2 is initialized 1061 * If execution is requested to non-secure EL1 or svc mode, and the CPU supports 1062 * EL2 then EL2 is disabled by configuring all necessary EL2 registers. 1063 * For all entries, the EL1 registers are initialized from the cpu_context 1064 ******************************************************************************/ 1065 void cm_prepare_el3_exit(uint32_t security_state) 1066 { 1067 u_register_t sctlr_el2, scr_el3; 1068 cpu_context_t *ctx = cm_get_context(security_state); 1069 1070 assert(ctx != NULL); 1071 1072 if (security_state == NON_SECURE) { 1073 uint64_t el2_implemented = el_implemented(2); 1074 1075 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), 1076 CTX_SCR_EL3); 1077 1078 if (el2_implemented != EL_IMPL_NONE) { 1079 1080 /* 1081 * If context is not being used for EL2, initialize 1082 * HCRX_EL2 with its init value here. 1083 */ 1084 if (is_feat_hcx_supported()) { 1085 write_hcrx_el2(HCRX_EL2_INIT_VAL); 1086 } 1087 1088 /* 1089 * Initialize Fine-grained trap registers introduced 1090 * by FEAT_FGT so all traps are initially disabled when 1091 * switching to EL2 or a lower EL, preventing undesired 1092 * behavior. 1093 */ 1094 if (is_feat_fgt_supported()) { 1095 /* 1096 * Initialize HFG*_EL2 registers with a default 1097 * value so legacy systems unaware of FEAT_FGT 1098 * do not get trapped due to their lack of 1099 * initialization for this feature. 1100 */ 1101 write_hfgitr_el2(HFGITR_EL2_INIT_VAL); 1102 write_hfgrtr_el2(HFGRTR_EL2_INIT_VAL); 1103 write_hfgwtr_el2(HFGWTR_EL2_INIT_VAL); 1104 } 1105 1106 /* Condition to ensure EL2 is being used. */ 1107 if ((scr_el3 & SCR_HCE_BIT) != 0U) { 1108 /* Initialize SCTLR_EL2 register with reset value. */ 1109 sctlr_el2 = SCTLR_EL2_RES1; 1110 1111 /* 1112 * If workaround of errata 764081 for Cortex-A75 1113 * is used then set SCTLR_EL2.IESB to enable 1114 * Implicit Error Synchronization Barrier. 1115 */ 1116 if (errata_a75_764081_applies()) { 1117 sctlr_el2 |= SCTLR_IESB_BIT; 1118 } 1119 1120 write_sctlr_el2(sctlr_el2); 1121 } else { 1122 /* 1123 * (scr_el3 & SCR_HCE_BIT==0) 1124 * EL2 implemented but unused. 1125 */ 1126 init_nonsecure_el2_unused(ctx); 1127 } 1128 } 1129 } 1130 #if (!CTX_INCLUDE_EL2_REGS) 1131 /* Restore EL1 system registers, only when CTX_INCLUDE_EL2_REGS=0 */ 1132 cm_el1_sysregs_context_restore(security_state); 1133 #endif 1134 cm_set_next_eret_context(security_state); 1135 } 1136 1137 #if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) 1138 1139 static void el2_sysregs_context_save_fgt(el2_sysregs_t *ctx) 1140 { 1141 write_el2_ctx_fgt(ctx, hdfgrtr_el2, read_hdfgrtr_el2()); 1142 if (is_feat_amu_supported()) { 1143 write_el2_ctx_fgt(ctx, hafgrtr_el2, read_hafgrtr_el2()); 1144 } 1145 write_el2_ctx_fgt(ctx, hdfgwtr_el2, read_hdfgwtr_el2()); 1146 write_el2_ctx_fgt(ctx, hfgitr_el2, read_hfgitr_el2()); 1147 write_el2_ctx_fgt(ctx, hfgrtr_el2, read_hfgrtr_el2()); 1148 write_el2_ctx_fgt(ctx, hfgwtr_el2, read_hfgwtr_el2()); 1149 } 1150 1151 static void el2_sysregs_context_restore_fgt(el2_sysregs_t *ctx) 1152 { 1153 write_hdfgrtr_el2(read_el2_ctx_fgt(ctx, hdfgrtr_el2)); 1154 if (is_feat_amu_supported()) { 1155 write_hafgrtr_el2(read_el2_ctx_fgt(ctx, hafgrtr_el2)); 1156 } 1157 write_hdfgwtr_el2(read_el2_ctx_fgt(ctx, hdfgwtr_el2)); 1158 write_hfgitr_el2(read_el2_ctx_fgt(ctx, hfgitr_el2)); 1159 write_hfgrtr_el2(read_el2_ctx_fgt(ctx, hfgrtr_el2)); 1160 write_hfgwtr_el2(read_el2_ctx_fgt(ctx, hfgwtr_el2)); 1161 } 1162 1163 static void el2_sysregs_context_save_fgt2(el2_sysregs_t *ctx) 1164 { 1165 write_el2_ctx_fgt2(ctx, hdfgrtr2_el2, read_hdfgrtr2_el2()); 1166 write_el2_ctx_fgt2(ctx, hdfgwtr2_el2, read_hdfgwtr2_el2()); 1167 write_el2_ctx_fgt2(ctx, hfgitr2_el2, read_hfgitr2_el2()); 1168 write_el2_ctx_fgt2(ctx, hfgrtr2_el2, read_hfgrtr2_el2()); 1169 write_el2_ctx_fgt2(ctx, hfgwtr2_el2, read_hfgwtr2_el2()); 1170 } 1171 1172 static void el2_sysregs_context_restore_fgt2(el2_sysregs_t *ctx) 1173 { 1174 write_hdfgrtr2_el2(read_el2_ctx_fgt2(ctx, hdfgrtr2_el2)); 1175 write_hdfgwtr2_el2(read_el2_ctx_fgt2(ctx, hdfgwtr2_el2)); 1176 write_hfgitr2_el2(read_el2_ctx_fgt2(ctx, hfgitr2_el2)); 1177 write_hfgrtr2_el2(read_el2_ctx_fgt2(ctx, hfgrtr2_el2)); 1178 write_hfgwtr2_el2(read_el2_ctx_fgt2(ctx, hfgwtr2_el2)); 1179 } 1180 1181 static void el2_sysregs_context_save_mpam(el2_sysregs_t *ctx) 1182 { 1183 u_register_t mpam_idr = read_mpamidr_el1(); 1184 1185 write_el2_ctx_mpam(ctx, mpam2_el2, read_mpam2_el2()); 1186 1187 /* 1188 * The context registers that we intend to save would be part of the 1189 * PE's system register frame only if MPAMIDR_EL1.HAS_HCR == 1. 1190 */ 1191 if ((mpam_idr & MPAMIDR_HAS_HCR_BIT) == 0U) { 1192 return; 1193 } 1194 1195 /* 1196 * MPAMHCR_EL2, MPAMVPMV_EL2 and MPAMVPM0_EL2 are always present if 1197 * MPAMIDR_HAS_HCR_BIT == 1. 1198 */ 1199 write_el2_ctx_mpam(ctx, mpamhcr_el2, read_mpamhcr_el2()); 1200 write_el2_ctx_mpam(ctx, mpamvpm0_el2, read_mpamvpm0_el2()); 1201 write_el2_ctx_mpam(ctx, mpamvpmv_el2, read_mpamvpmv_el2()); 1202 1203 /* 1204 * The number of MPAMVPM registers is implementation defined, their 1205 * number is stored in the MPAMIDR_EL1 register. 1206 */ 1207 switch ((mpam_idr >> MPAMIDR_EL1_VPMR_MAX_SHIFT) & MPAMIDR_EL1_VPMR_MAX_MASK) { 1208 case 7: 1209 write_el2_ctx_mpam(ctx, mpamvpm7_el2, read_mpamvpm7_el2()); 1210 __fallthrough; 1211 case 6: 1212 write_el2_ctx_mpam(ctx, mpamvpm6_el2, read_mpamvpm6_el2()); 1213 __fallthrough; 1214 case 5: 1215 write_el2_ctx_mpam(ctx, mpamvpm5_el2, read_mpamvpm5_el2()); 1216 __fallthrough; 1217 case 4: 1218 write_el2_ctx_mpam(ctx, mpamvpm4_el2, read_mpamvpm4_el2()); 1219 __fallthrough; 1220 case 3: 1221 write_el2_ctx_mpam(ctx, mpamvpm3_el2, read_mpamvpm3_el2()); 1222 __fallthrough; 1223 case 2: 1224 write_el2_ctx_mpam(ctx, mpamvpm2_el2, read_mpamvpm2_el2()); 1225 __fallthrough; 1226 case 1: 1227 write_el2_ctx_mpam(ctx, mpamvpm1_el2, read_mpamvpm1_el2()); 1228 break; 1229 } 1230 } 1231 1232 static void el2_sysregs_context_restore_mpam(el2_sysregs_t *ctx) 1233 { 1234 u_register_t mpam_idr = read_mpamidr_el1(); 1235 1236 write_mpam2_el2(read_el2_ctx_mpam(ctx, mpam2_el2)); 1237 1238 if ((mpam_idr & MPAMIDR_HAS_HCR_BIT) == 0U) { 1239 return; 1240 } 1241 1242 write_mpamhcr_el2(read_el2_ctx_mpam(ctx, mpamhcr_el2)); 1243 write_mpamvpm0_el2(read_el2_ctx_mpam(ctx, mpamvpm0_el2)); 1244 write_mpamvpmv_el2(read_el2_ctx_mpam(ctx, mpamvpmv_el2)); 1245 1246 switch ((mpam_idr >> MPAMIDR_EL1_VPMR_MAX_SHIFT) & MPAMIDR_EL1_VPMR_MAX_MASK) { 1247 case 7: 1248 write_mpamvpm7_el2(read_el2_ctx_mpam(ctx, mpamvpm7_el2)); 1249 __fallthrough; 1250 case 6: 1251 write_mpamvpm6_el2(read_el2_ctx_mpam(ctx, mpamvpm6_el2)); 1252 __fallthrough; 1253 case 5: 1254 write_mpamvpm5_el2(read_el2_ctx_mpam(ctx, mpamvpm5_el2)); 1255 __fallthrough; 1256 case 4: 1257 write_mpamvpm4_el2(read_el2_ctx_mpam(ctx, mpamvpm4_el2)); 1258 __fallthrough; 1259 case 3: 1260 write_mpamvpm3_el2(read_el2_ctx_mpam(ctx, mpamvpm3_el2)); 1261 __fallthrough; 1262 case 2: 1263 write_mpamvpm2_el2(read_el2_ctx_mpam(ctx, mpamvpm2_el2)); 1264 __fallthrough; 1265 case 1: 1266 write_mpamvpm1_el2(read_el2_ctx_mpam(ctx, mpamvpm1_el2)); 1267 break; 1268 } 1269 } 1270 1271 /* --------------------------------------------------------------------------- 1272 * The following registers are not added: 1273 * ICH_AP0R<n>_EL2 1274 * ICH_AP1R<n>_EL2 1275 * ICH_LR<n>_EL2 1276 * 1277 * NOTE: For a system with S-EL2 present but not enabled, accessing 1278 * ICC_SRE_EL2 is undefined from EL3. To workaround this change the 1279 * SCR_EL3.NS = 1 before accessing this register. 1280 * --------------------------------------------------------------------------- 1281 */ 1282 static void el2_sysregs_context_save_gic(el2_sysregs_t *ctx) 1283 { 1284 #if defined(SPD_spmd) && SPMD_SPM_AT_SEL2 1285 write_el2_ctx_common(ctx, icc_sre_el2, read_icc_sre_el2()); 1286 #else 1287 u_register_t scr_el3 = read_scr_el3(); 1288 write_scr_el3(scr_el3 | SCR_NS_BIT); 1289 isb(); 1290 1291 write_el2_ctx_common(ctx, icc_sre_el2, read_icc_sre_el2()); 1292 1293 write_scr_el3(scr_el3); 1294 isb(); 1295 #endif 1296 write_el2_ctx_common(ctx, ich_hcr_el2, read_ich_hcr_el2()); 1297 write_el2_ctx_common(ctx, ich_vmcr_el2, read_ich_vmcr_el2()); 1298 } 1299 1300 static void el2_sysregs_context_restore_gic(el2_sysregs_t *ctx) 1301 { 1302 #if defined(SPD_spmd) && SPMD_SPM_AT_SEL2 1303 write_icc_sre_el2(read_el2_ctx_common(ctx, icc_sre_el2)); 1304 #else 1305 u_register_t scr_el3 = read_scr_el3(); 1306 write_scr_el3(scr_el3 | SCR_NS_BIT); 1307 isb(); 1308 1309 write_icc_sre_el2(read_el2_ctx_common(ctx, icc_sre_el2)); 1310 1311 write_scr_el3(scr_el3); 1312 isb(); 1313 #endif 1314 write_ich_hcr_el2(read_el2_ctx_common(ctx, ich_hcr_el2)); 1315 write_ich_vmcr_el2(read_el2_ctx_common(ctx, ich_vmcr_el2)); 1316 } 1317 1318 /* ----------------------------------------------------- 1319 * The following registers are not added: 1320 * AMEVCNTVOFF0<n>_EL2 1321 * AMEVCNTVOFF1<n>_EL2 1322 * ----------------------------------------------------- 1323 */ 1324 static void el2_sysregs_context_save_common(el2_sysregs_t *ctx) 1325 { 1326 write_el2_ctx_common(ctx, actlr_el2, read_actlr_el2()); 1327 write_el2_ctx_common(ctx, afsr0_el2, read_afsr0_el2()); 1328 write_el2_ctx_common(ctx, afsr1_el2, read_afsr1_el2()); 1329 write_el2_ctx_common(ctx, amair_el2, read_amair_el2()); 1330 write_el2_ctx_common(ctx, cnthctl_el2, read_cnthctl_el2()); 1331 write_el2_ctx_common(ctx, cntvoff_el2, read_cntvoff_el2()); 1332 write_el2_ctx_common(ctx, cptr_el2, read_cptr_el2()); 1333 if (CTX_INCLUDE_AARCH32_REGS) { 1334 write_el2_ctx_common(ctx, dbgvcr32_el2, read_dbgvcr32_el2()); 1335 } 1336 write_el2_ctx_common(ctx, elr_el2, read_elr_el2()); 1337 write_el2_ctx_common(ctx, esr_el2, read_esr_el2()); 1338 write_el2_ctx_common(ctx, far_el2, read_far_el2()); 1339 write_el2_ctx_common(ctx, hacr_el2, read_hacr_el2()); 1340 write_el2_ctx_common(ctx, hcr_el2, read_hcr_el2()); 1341 write_el2_ctx_common(ctx, hpfar_el2, read_hpfar_el2()); 1342 write_el2_ctx_common(ctx, hstr_el2, read_hstr_el2()); 1343 write_el2_ctx_common(ctx, mair_el2, read_mair_el2()); 1344 write_el2_ctx_common(ctx, mdcr_el2, read_mdcr_el2()); 1345 write_el2_ctx_common(ctx, sctlr_el2, read_sctlr_el2()); 1346 write_el2_ctx_common(ctx, spsr_el2, read_spsr_el2()); 1347 write_el2_ctx_common(ctx, sp_el2, read_sp_el2()); 1348 write_el2_ctx_common(ctx, tcr_el2, read_tcr_el2()); 1349 write_el2_ctx_common(ctx, tpidr_el2, read_tpidr_el2()); 1350 write_el2_ctx_common(ctx, vbar_el2, read_vbar_el2()); 1351 write_el2_ctx_common(ctx, vmpidr_el2, read_vmpidr_el2()); 1352 write_el2_ctx_common(ctx, vpidr_el2, read_vpidr_el2()); 1353 write_el2_ctx_common(ctx, vtcr_el2, read_vtcr_el2()); 1354 1355 write_el2_ctx_sysreg128(ctx, ttbr0_el2, read_ttbr0_el2()); 1356 write_el2_ctx_sysreg128(ctx, vttbr_el2, read_vttbr_el2()); 1357 } 1358 1359 static void el2_sysregs_context_restore_common(el2_sysregs_t *ctx) 1360 { 1361 write_actlr_el2(read_el2_ctx_common(ctx, actlr_el2)); 1362 write_afsr0_el2(read_el2_ctx_common(ctx, afsr0_el2)); 1363 write_afsr1_el2(read_el2_ctx_common(ctx, afsr1_el2)); 1364 write_amair_el2(read_el2_ctx_common(ctx, amair_el2)); 1365 write_cnthctl_el2(read_el2_ctx_common(ctx, cnthctl_el2)); 1366 write_cntvoff_el2(read_el2_ctx_common(ctx, cntvoff_el2)); 1367 write_cptr_el2(read_el2_ctx_common(ctx, cptr_el2)); 1368 if (CTX_INCLUDE_AARCH32_REGS) { 1369 write_dbgvcr32_el2(read_el2_ctx_common(ctx, dbgvcr32_el2)); 1370 } 1371 write_elr_el2(read_el2_ctx_common(ctx, elr_el2)); 1372 write_esr_el2(read_el2_ctx_common(ctx, esr_el2)); 1373 write_far_el2(read_el2_ctx_common(ctx, far_el2)); 1374 write_hacr_el2(read_el2_ctx_common(ctx, hacr_el2)); 1375 write_hcr_el2(read_el2_ctx_common(ctx, hcr_el2)); 1376 write_hpfar_el2(read_el2_ctx_common(ctx, hpfar_el2)); 1377 write_hstr_el2(read_el2_ctx_common(ctx, hstr_el2)); 1378 write_mair_el2(read_el2_ctx_common(ctx, mair_el2)); 1379 write_mdcr_el2(read_el2_ctx_common(ctx, mdcr_el2)); 1380 write_sctlr_el2(read_el2_ctx_common(ctx, sctlr_el2)); 1381 write_spsr_el2(read_el2_ctx_common(ctx, spsr_el2)); 1382 write_sp_el2(read_el2_ctx_common(ctx, sp_el2)); 1383 write_tcr_el2(read_el2_ctx_common(ctx, tcr_el2)); 1384 write_tpidr_el2(read_el2_ctx_common(ctx, tpidr_el2)); 1385 write_ttbr0_el2(read_el2_ctx_common(ctx, ttbr0_el2)); 1386 write_vbar_el2(read_el2_ctx_common(ctx, vbar_el2)); 1387 write_vmpidr_el2(read_el2_ctx_common(ctx, vmpidr_el2)); 1388 write_vpidr_el2(read_el2_ctx_common(ctx, vpidr_el2)); 1389 write_vtcr_el2(read_el2_ctx_common(ctx, vtcr_el2)); 1390 write_vttbr_el2(read_el2_ctx_common(ctx, vttbr_el2)); 1391 } 1392 1393 /******************************************************************************* 1394 * Save EL2 sysreg context 1395 ******************************************************************************/ 1396 void cm_el2_sysregs_context_save(uint32_t security_state) 1397 { 1398 cpu_context_t *ctx; 1399 el2_sysregs_t *el2_sysregs_ctx; 1400 1401 ctx = cm_get_context(security_state); 1402 assert(ctx != NULL); 1403 1404 el2_sysregs_ctx = get_el2_sysregs_ctx(ctx); 1405 1406 el2_sysregs_context_save_common(el2_sysregs_ctx); 1407 el2_sysregs_context_save_gic(el2_sysregs_ctx); 1408 1409 if (is_feat_mte2_supported()) { 1410 write_el2_ctx_mte2(el2_sysregs_ctx, tfsr_el2, read_tfsr_el2()); 1411 } 1412 1413 if (is_feat_mpam_supported()) { 1414 el2_sysregs_context_save_mpam(el2_sysregs_ctx); 1415 } 1416 1417 if (is_feat_fgt_supported()) { 1418 el2_sysregs_context_save_fgt(el2_sysregs_ctx); 1419 } 1420 1421 if (is_feat_fgt2_supported()) { 1422 el2_sysregs_context_save_fgt2(el2_sysregs_ctx); 1423 } 1424 1425 if (is_feat_ecv_v2_supported()) { 1426 write_el2_ctx_ecv(el2_sysregs_ctx, cntpoff_el2, read_cntpoff_el2()); 1427 } 1428 1429 if (is_feat_vhe_supported()) { 1430 write_el2_ctx_vhe(el2_sysregs_ctx, contextidr_el2, 1431 read_contextidr_el2()); 1432 write_el2_ctx_vhe_sysreg128(el2_sysregs_ctx, ttbr1_el2, read_ttbr1_el2()); 1433 } 1434 1435 if (is_feat_ras_supported()) { 1436 write_el2_ctx_ras(el2_sysregs_ctx, vdisr_el2, read_vdisr_el2()); 1437 write_el2_ctx_ras(el2_sysregs_ctx, vsesr_el2, read_vsesr_el2()); 1438 } 1439 1440 if (is_feat_nv2_supported()) { 1441 write_el2_ctx_neve(el2_sysregs_ctx, vncr_el2, read_vncr_el2()); 1442 } 1443 1444 if (is_feat_trf_supported()) { 1445 write_el2_ctx_trf(el2_sysregs_ctx, trfcr_el2, read_trfcr_el2()); 1446 } 1447 1448 if (is_feat_csv2_2_supported()) { 1449 write_el2_ctx_csv2_2(el2_sysregs_ctx, scxtnum_el2, 1450 read_scxtnum_el2()); 1451 } 1452 1453 if (is_feat_hcx_supported()) { 1454 write_el2_ctx_hcx(el2_sysregs_ctx, hcrx_el2, read_hcrx_el2()); 1455 } 1456 1457 if (is_feat_tcr2_supported()) { 1458 write_el2_ctx_tcr2(el2_sysregs_ctx, tcr2_el2, read_tcr2_el2()); 1459 } 1460 1461 if (is_feat_sxpie_supported()) { 1462 write_el2_ctx_sxpie(el2_sysregs_ctx, pire0_el2, read_pire0_el2()); 1463 write_el2_ctx_sxpie(el2_sysregs_ctx, pir_el2, read_pir_el2()); 1464 } 1465 1466 if (is_feat_sxpoe_supported()) { 1467 write_el2_ctx_sxpoe(el2_sysregs_ctx, por_el2, read_por_el2()); 1468 } 1469 1470 if (is_feat_s2pie_supported()) { 1471 write_el2_ctx_s2pie(el2_sysregs_ctx, s2pir_el2, read_s2pir_el2()); 1472 } 1473 1474 if (is_feat_gcs_supported()) { 1475 write_el2_ctx_gcs(el2_sysregs_ctx, gcscr_el2, read_gcscr_el2()); 1476 write_el2_ctx_gcs(el2_sysregs_ctx, gcspr_el2, read_gcspr_el2()); 1477 } 1478 1479 if (is_feat_sctlr2_supported()) { 1480 write_el2_ctx_sctlr2(el2_sysregs_ctx, sctlr2_el2, read_sctlr2_el2()); 1481 } 1482 } 1483 1484 /******************************************************************************* 1485 * Restore EL2 sysreg context 1486 ******************************************************************************/ 1487 void cm_el2_sysregs_context_restore(uint32_t security_state) 1488 { 1489 cpu_context_t *ctx; 1490 el2_sysregs_t *el2_sysregs_ctx; 1491 1492 ctx = cm_get_context(security_state); 1493 assert(ctx != NULL); 1494 1495 el2_sysregs_ctx = get_el2_sysregs_ctx(ctx); 1496 1497 el2_sysregs_context_restore_common(el2_sysregs_ctx); 1498 el2_sysregs_context_restore_gic(el2_sysregs_ctx); 1499 1500 if (is_feat_mte2_supported()) { 1501 write_tfsr_el2(read_el2_ctx_mte2(el2_sysregs_ctx, tfsr_el2)); 1502 } 1503 1504 if (is_feat_mpam_supported()) { 1505 el2_sysregs_context_restore_mpam(el2_sysregs_ctx); 1506 } 1507 1508 if (is_feat_fgt_supported()) { 1509 el2_sysregs_context_restore_fgt(el2_sysregs_ctx); 1510 } 1511 1512 if (is_feat_fgt2_supported()) { 1513 el2_sysregs_context_restore_fgt2(el2_sysregs_ctx); 1514 } 1515 1516 if (is_feat_ecv_v2_supported()) { 1517 write_cntpoff_el2(read_el2_ctx_ecv(el2_sysregs_ctx, cntpoff_el2)); 1518 } 1519 1520 if (is_feat_vhe_supported()) { 1521 write_contextidr_el2(read_el2_ctx_vhe(el2_sysregs_ctx, 1522 contextidr_el2)); 1523 write_ttbr1_el2(read_el2_ctx_vhe(el2_sysregs_ctx, ttbr1_el2)); 1524 } 1525 1526 if (is_feat_ras_supported()) { 1527 write_vdisr_el2(read_el2_ctx_ras(el2_sysregs_ctx, vdisr_el2)); 1528 write_vsesr_el2(read_el2_ctx_ras(el2_sysregs_ctx, vsesr_el2)); 1529 } 1530 1531 if (is_feat_nv2_supported()) { 1532 write_vncr_el2(read_el2_ctx_neve(el2_sysregs_ctx, vncr_el2)); 1533 } 1534 1535 if (is_feat_trf_supported()) { 1536 write_trfcr_el2(read_el2_ctx_trf(el2_sysregs_ctx, trfcr_el2)); 1537 } 1538 1539 if (is_feat_csv2_2_supported()) { 1540 write_scxtnum_el2(read_el2_ctx_csv2_2(el2_sysregs_ctx, 1541 scxtnum_el2)); 1542 } 1543 1544 if (is_feat_hcx_supported()) { 1545 write_hcrx_el2(read_el2_ctx_hcx(el2_sysregs_ctx, hcrx_el2)); 1546 } 1547 1548 if (is_feat_tcr2_supported()) { 1549 write_tcr2_el2(read_el2_ctx_tcr2(el2_sysregs_ctx, tcr2_el2)); 1550 } 1551 1552 if (is_feat_sxpie_supported()) { 1553 write_pire0_el2(read_el2_ctx_sxpie(el2_sysregs_ctx, pire0_el2)); 1554 write_pir_el2(read_el2_ctx_sxpie(el2_sysregs_ctx, pir_el2)); 1555 } 1556 1557 if (is_feat_sxpoe_supported()) { 1558 write_por_el2(read_el2_ctx_sxpoe(el2_sysregs_ctx, por_el2)); 1559 } 1560 1561 if (is_feat_s2pie_supported()) { 1562 write_s2pir_el2(read_el2_ctx_s2pie(el2_sysregs_ctx, s2pir_el2)); 1563 } 1564 1565 if (is_feat_gcs_supported()) { 1566 write_gcscr_el2(read_el2_ctx_gcs(el2_sysregs_ctx, gcscr_el2)); 1567 write_gcspr_el2(read_el2_ctx_gcs(el2_sysregs_ctx, gcspr_el2)); 1568 } 1569 1570 if (is_feat_sctlr2_supported()) { 1571 write_sctlr2_el2(read_el2_ctx_sctlr2(el2_sysregs_ctx, sctlr2_el2)); 1572 } 1573 } 1574 #endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */ 1575 1576 #if IMAGE_BL31 1577 /********************************************************************************* 1578 * This function allows Architecture features asymmetry among cores. 1579 * TF-A assumes that all the cores in the platform has architecture feature parity 1580 * and hence the context is setup on different core (e.g. primary sets up the 1581 * context for secondary cores).This assumption may not be true for systems where 1582 * cores are not conforming to same Arch version or there is CPU Erratum which 1583 * requires certain feature to be be disabled only on a given core. 1584 * 1585 * This function is called on secondary cores to override any disparity in context 1586 * setup by primary, this would be called during warmboot path. 1587 *********************************************************************************/ 1588 void cm_handle_asymmetric_features(void) 1589 { 1590 cpu_context_t *ctx __maybe_unused = cm_get_context(NON_SECURE); 1591 1592 assert(ctx != NULL); 1593 1594 #if ENABLE_SPE_FOR_NS == FEAT_STATE_CHECK_ASYMMETRIC 1595 if (is_feat_spe_supported()) { 1596 spe_enable(ctx); 1597 } else { 1598 spe_disable(ctx); 1599 } 1600 #endif 1601 1602 #if ERRATA_A520_2938996 || ERRATA_X4_2726228 1603 if (check_if_affected_core() == ERRATA_APPLIES) { 1604 if (is_feat_trbe_supported()) { 1605 trbe_disable(ctx); 1606 } 1607 } 1608 #endif 1609 1610 #if ENABLE_FEAT_TCR2 == FEAT_STATE_CHECK_ASYMMETRIC 1611 el3_state_t *el3_state = get_el3state_ctx(ctx); 1612 u_register_t spsr = read_ctx_reg(el3_state, CTX_SPSR_EL3); 1613 1614 if (is_feat_tcr2_supported() && (GET_RW(spsr) == MODE_RW_64)) { 1615 tcr2_enable(ctx); 1616 } else { 1617 tcr2_disable(ctx); 1618 } 1619 #endif 1620 1621 } 1622 #endif 1623 1624 /******************************************************************************* 1625 * This function is used to exit to Non-secure world. If CTX_INCLUDE_EL2_REGS 1626 * is enabled, it restores EL1 and EL2 sysreg contexts instead of directly 1627 * updating EL1 and EL2 registers. Otherwise, it calls the generic 1628 * cm_prepare_el3_exit function. 1629 ******************************************************************************/ 1630 void cm_prepare_el3_exit_ns(void) 1631 { 1632 #if IMAGE_BL31 1633 /* 1634 * Check and handle Architecture feature asymmetry among cores. 1635 * 1636 * In warmboot path secondary cores context is initialized on core which 1637 * did CPU_ON SMC call, if there is feature asymmetry in these cores handle 1638 * it in this function call. 1639 * For Symmetric cores this is an empty function. 1640 */ 1641 cm_handle_asymmetric_features(); 1642 #endif 1643 1644 #if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) 1645 #if ENABLE_ASSERTIONS 1646 cpu_context_t *ctx = cm_get_context(NON_SECURE); 1647 assert(ctx != NULL); 1648 1649 /* Assert that EL2 is used. */ 1650 u_register_t scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3); 1651 assert(((scr_el3 & SCR_HCE_BIT) != 0UL) && 1652 (el_implemented(2U) != EL_IMPL_NONE)); 1653 #endif /* ENABLE_ASSERTIONS */ 1654 1655 /* Restore EL2 sysreg contexts */ 1656 cm_el2_sysregs_context_restore(NON_SECURE); 1657 cm_set_next_eret_context(NON_SECURE); 1658 #else 1659 cm_prepare_el3_exit(NON_SECURE); 1660 #endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */ 1661 } 1662 1663 #if ((IMAGE_BL1) || (IMAGE_BL31 && (!CTX_INCLUDE_EL2_REGS))) 1664 /******************************************************************************* 1665 * The next set of six functions are used by runtime services to save and restore 1666 * EL1 context on the 'cpu_context' structure for the specified security state. 1667 ******************************************************************************/ 1668 static void el1_sysregs_context_save(el1_sysregs_t *ctx) 1669 { 1670 write_el1_ctx_common(ctx, spsr_el1, read_spsr_el1()); 1671 write_el1_ctx_common(ctx, elr_el1, read_elr_el1()); 1672 1673 #if (!ERRATA_SPECULATIVE_AT) 1674 write_el1_ctx_common(ctx, sctlr_el1, read_sctlr_el1()); 1675 write_el1_ctx_common(ctx, tcr_el1, read_tcr_el1()); 1676 #endif /* (!ERRATA_SPECULATIVE_AT) */ 1677 1678 write_el1_ctx_common(ctx, cpacr_el1, read_cpacr_el1()); 1679 write_el1_ctx_common(ctx, csselr_el1, read_csselr_el1()); 1680 write_el1_ctx_common(ctx, sp_el1, read_sp_el1()); 1681 write_el1_ctx_common(ctx, esr_el1, read_esr_el1()); 1682 write_el1_ctx_common(ctx, ttbr0_el1, read_ttbr0_el1()); 1683 write_el1_ctx_common(ctx, ttbr1_el1, read_ttbr1_el1()); 1684 write_el1_ctx_common(ctx, mair_el1, read_mair_el1()); 1685 write_el1_ctx_common(ctx, amair_el1, read_amair_el1()); 1686 write_el1_ctx_common(ctx, actlr_el1, read_actlr_el1()); 1687 write_el1_ctx_common(ctx, tpidr_el1, read_tpidr_el1()); 1688 write_el1_ctx_common(ctx, tpidr_el0, read_tpidr_el0()); 1689 write_el1_ctx_common(ctx, tpidrro_el0, read_tpidrro_el0()); 1690 write_el1_ctx_common(ctx, par_el1, read_par_el1()); 1691 write_el1_ctx_common(ctx, far_el1, read_far_el1()); 1692 write_el1_ctx_common(ctx, afsr0_el1, read_afsr0_el1()); 1693 write_el1_ctx_common(ctx, afsr1_el1, read_afsr1_el1()); 1694 write_el1_ctx_common(ctx, contextidr_el1, read_contextidr_el1()); 1695 write_el1_ctx_common(ctx, vbar_el1, read_vbar_el1()); 1696 write_el1_ctx_common(ctx, mdccint_el1, read_mdccint_el1()); 1697 write_el1_ctx_common(ctx, mdscr_el1, read_mdscr_el1()); 1698 1699 if (CTX_INCLUDE_AARCH32_REGS) { 1700 /* Save Aarch32 registers */ 1701 write_el1_ctx_aarch32(ctx, spsr_abt, read_spsr_abt()); 1702 write_el1_ctx_aarch32(ctx, spsr_und, read_spsr_und()); 1703 write_el1_ctx_aarch32(ctx, spsr_irq, read_spsr_irq()); 1704 write_el1_ctx_aarch32(ctx, spsr_fiq, read_spsr_fiq()); 1705 write_el1_ctx_aarch32(ctx, dacr32_el2, read_dacr32_el2()); 1706 write_el1_ctx_aarch32(ctx, ifsr32_el2, read_ifsr32_el2()); 1707 } 1708 1709 if (NS_TIMER_SWITCH) { 1710 /* Save NS Timer registers */ 1711 write_el1_ctx_arch_timer(ctx, cntp_ctl_el0, read_cntp_ctl_el0()); 1712 write_el1_ctx_arch_timer(ctx, cntp_cval_el0, read_cntp_cval_el0()); 1713 write_el1_ctx_arch_timer(ctx, cntv_ctl_el0, read_cntv_ctl_el0()); 1714 write_el1_ctx_arch_timer(ctx, cntv_cval_el0, read_cntv_cval_el0()); 1715 write_el1_ctx_arch_timer(ctx, cntkctl_el1, read_cntkctl_el1()); 1716 } 1717 1718 if (is_feat_mte2_supported()) { 1719 write_el1_ctx_mte2(ctx, tfsre0_el1, read_tfsre0_el1()); 1720 write_el1_ctx_mte2(ctx, tfsr_el1, read_tfsr_el1()); 1721 write_el1_ctx_mte2(ctx, rgsr_el1, read_rgsr_el1()); 1722 write_el1_ctx_mte2(ctx, gcr_el1, read_gcr_el1()); 1723 } 1724 1725 if (is_feat_ras_supported()) { 1726 write_el1_ctx_ras(ctx, disr_el1, read_disr_el1()); 1727 } 1728 1729 if (is_feat_s1pie_supported()) { 1730 write_el1_ctx_s1pie(ctx, pire0_el1, read_pire0_el1()); 1731 write_el1_ctx_s1pie(ctx, pir_el1, read_pir_el1()); 1732 } 1733 1734 if (is_feat_s1poe_supported()) { 1735 write_el1_ctx_s1poe(ctx, por_el1, read_por_el1()); 1736 } 1737 1738 if (is_feat_s2poe_supported()) { 1739 write_el1_ctx_s2poe(ctx, s2por_el1, read_s2por_el1()); 1740 } 1741 1742 if (is_feat_tcr2_supported()) { 1743 write_el1_ctx_tcr2(ctx, tcr2_el1, read_tcr2_el1()); 1744 } 1745 1746 if (is_feat_trf_supported()) { 1747 write_el1_ctx_trf(ctx, trfcr_el1, read_trfcr_el1()); 1748 } 1749 1750 if (is_feat_csv2_2_supported()) { 1751 write_el1_ctx_csv2_2(ctx, scxtnum_el0, read_scxtnum_el0()); 1752 write_el1_ctx_csv2_2(ctx, scxtnum_el1, read_scxtnum_el1()); 1753 } 1754 1755 if (is_feat_gcs_supported()) { 1756 write_el1_ctx_gcs(ctx, gcscr_el1, read_gcscr_el1()); 1757 write_el1_ctx_gcs(ctx, gcscre0_el1, read_gcscre0_el1()); 1758 write_el1_ctx_gcs(ctx, gcspr_el1, read_gcspr_el1()); 1759 write_el1_ctx_gcs(ctx, gcspr_el0, read_gcspr_el0()); 1760 } 1761 1762 if (is_feat_the_supported()) { 1763 write_el1_ctx_the(ctx, rcwmask_el1, read_rcwmask_el1()); 1764 write_el1_ctx_the(ctx, rcwsmask_el1, read_rcwsmask_el1()); 1765 } 1766 1767 if (is_feat_sctlr2_supported()) { 1768 write_el1_ctx_sctlr2(ctx, sctlr2_el1, read_sctlr2_el1()); 1769 } 1770 1771 if (is_feat_ls64_accdata_supported()) { 1772 write_el1_ctx_ls64(ctx, accdata_el1, read_accdata_el1()); 1773 } 1774 } 1775 1776 static void el1_sysregs_context_restore(el1_sysregs_t *ctx) 1777 { 1778 write_spsr_el1(read_el1_ctx_common(ctx, spsr_el1)); 1779 write_elr_el1(read_el1_ctx_common(ctx, elr_el1)); 1780 1781 #if (!ERRATA_SPECULATIVE_AT) 1782 write_sctlr_el1(read_el1_ctx_common(ctx, sctlr_el1)); 1783 write_tcr_el1(read_el1_ctx_common(ctx, tcr_el1)); 1784 #endif /* (!ERRATA_SPECULATIVE_AT) */ 1785 1786 write_cpacr_el1(read_el1_ctx_common(ctx, cpacr_el1)); 1787 write_csselr_el1(read_el1_ctx_common(ctx, csselr_el1)); 1788 write_sp_el1(read_el1_ctx_common(ctx, sp_el1)); 1789 write_esr_el1(read_el1_ctx_common(ctx, esr_el1)); 1790 write_ttbr0_el1(read_el1_ctx_common(ctx, ttbr0_el1)); 1791 write_ttbr1_el1(read_el1_ctx_common(ctx, ttbr1_el1)); 1792 write_mair_el1(read_el1_ctx_common(ctx, mair_el1)); 1793 write_amair_el1(read_el1_ctx_common(ctx, amair_el1)); 1794 write_actlr_el1(read_el1_ctx_common(ctx, actlr_el1)); 1795 write_tpidr_el1(read_el1_ctx_common(ctx, tpidr_el1)); 1796 write_tpidr_el0(read_el1_ctx_common(ctx, tpidr_el0)); 1797 write_tpidrro_el0(read_el1_ctx_common(ctx, tpidrro_el0)); 1798 write_par_el1(read_el1_ctx_common(ctx, par_el1)); 1799 write_far_el1(read_el1_ctx_common(ctx, far_el1)); 1800 write_afsr0_el1(read_el1_ctx_common(ctx, afsr0_el1)); 1801 write_afsr1_el1(read_el1_ctx_common(ctx, afsr1_el1)); 1802 write_contextidr_el1(read_el1_ctx_common(ctx, contextidr_el1)); 1803 write_vbar_el1(read_el1_ctx_common(ctx, vbar_el1)); 1804 write_mdccint_el1(read_el1_ctx_common(ctx, mdccint_el1)); 1805 write_mdscr_el1(read_el1_ctx_common(ctx, mdscr_el1)); 1806 1807 if (CTX_INCLUDE_AARCH32_REGS) { 1808 /* Restore Aarch32 registers */ 1809 write_spsr_abt(read_el1_ctx_aarch32(ctx, spsr_abt)); 1810 write_spsr_und(read_el1_ctx_aarch32(ctx, spsr_und)); 1811 write_spsr_irq(read_el1_ctx_aarch32(ctx, spsr_irq)); 1812 write_spsr_fiq(read_el1_ctx_aarch32(ctx, spsr_fiq)); 1813 write_dacr32_el2(read_el1_ctx_aarch32(ctx, dacr32_el2)); 1814 write_ifsr32_el2(read_el1_ctx_aarch32(ctx, ifsr32_el2)); 1815 } 1816 1817 if (NS_TIMER_SWITCH) { 1818 /* Restore NS Timer registers */ 1819 write_cntp_ctl_el0(read_el1_ctx_arch_timer(ctx, cntp_ctl_el0)); 1820 write_cntp_cval_el0(read_el1_ctx_arch_timer(ctx, cntp_cval_el0)); 1821 write_cntv_ctl_el0(read_el1_ctx_arch_timer(ctx, cntv_ctl_el0)); 1822 write_cntv_cval_el0(read_el1_ctx_arch_timer(ctx, cntv_cval_el0)); 1823 write_cntkctl_el1(read_el1_ctx_arch_timer(ctx, cntkctl_el1)); 1824 } 1825 1826 if (is_feat_mte2_supported()) { 1827 write_tfsre0_el1(read_el1_ctx_mte2(ctx, tfsre0_el1)); 1828 write_tfsr_el1(read_el1_ctx_mte2(ctx, tfsr_el1)); 1829 write_rgsr_el1(read_el1_ctx_mte2(ctx, rgsr_el1)); 1830 write_gcr_el1(read_el1_ctx_mte2(ctx, gcr_el1)); 1831 } 1832 1833 if (is_feat_ras_supported()) { 1834 write_disr_el1(read_el1_ctx_ras(ctx, disr_el1)); 1835 } 1836 1837 if (is_feat_s1pie_supported()) { 1838 write_pire0_el1(read_el1_ctx_s1pie(ctx, pire0_el1)); 1839 write_pir_el1(read_el1_ctx_s1pie(ctx, pir_el1)); 1840 } 1841 1842 if (is_feat_s1poe_supported()) { 1843 write_por_el1(read_el1_ctx_s1poe(ctx, por_el1)); 1844 } 1845 1846 if (is_feat_s2poe_supported()) { 1847 write_s2por_el1(read_el1_ctx_s2poe(ctx, s2por_el1)); 1848 } 1849 1850 if (is_feat_tcr2_supported()) { 1851 write_tcr2_el1(read_el1_ctx_tcr2(ctx, tcr2_el1)); 1852 } 1853 1854 if (is_feat_trf_supported()) { 1855 write_trfcr_el1(read_el1_ctx_trf(ctx, trfcr_el1)); 1856 } 1857 1858 if (is_feat_csv2_2_supported()) { 1859 write_scxtnum_el0(read_el1_ctx_csv2_2(ctx, scxtnum_el0)); 1860 write_scxtnum_el1(read_el1_ctx_csv2_2(ctx, scxtnum_el1)); 1861 } 1862 1863 if (is_feat_gcs_supported()) { 1864 write_gcscr_el1(read_el1_ctx_gcs(ctx, gcscr_el1)); 1865 write_gcscre0_el1(read_el1_ctx_gcs(ctx, gcscre0_el1)); 1866 write_gcspr_el1(read_el1_ctx_gcs(ctx, gcspr_el1)); 1867 write_gcspr_el0(read_el1_ctx_gcs(ctx, gcspr_el0)); 1868 } 1869 1870 if (is_feat_the_supported()) { 1871 write_rcwmask_el1(read_el1_ctx_the(ctx, rcwmask_el1)); 1872 write_rcwsmask_el1(read_el1_ctx_the(ctx, rcwsmask_el1)); 1873 } 1874 1875 if (is_feat_sctlr2_supported()) { 1876 write_sctlr2_el1(read_el1_ctx_sctlr2(ctx, sctlr2_el1)); 1877 } 1878 1879 if (is_feat_ls64_accdata_supported()) { 1880 write_accdata_el1(read_el1_ctx_ls64(ctx, accdata_el1)); 1881 } 1882 } 1883 1884 /******************************************************************************* 1885 * The next couple of functions are used by runtime services to save and restore 1886 * EL1 context on the 'cpu_context' structure for the specified security state. 1887 ******************************************************************************/ 1888 void cm_el1_sysregs_context_save(uint32_t security_state) 1889 { 1890 cpu_context_t *ctx; 1891 1892 ctx = cm_get_context(security_state); 1893 assert(ctx != NULL); 1894 1895 el1_sysregs_context_save(get_el1_sysregs_ctx(ctx)); 1896 1897 #if IMAGE_BL31 1898 if (security_state == SECURE) 1899 PUBLISH_EVENT(cm_exited_secure_world); 1900 else 1901 PUBLISH_EVENT(cm_exited_normal_world); 1902 #endif 1903 } 1904 1905 void cm_el1_sysregs_context_restore(uint32_t security_state) 1906 { 1907 cpu_context_t *ctx; 1908 1909 ctx = cm_get_context(security_state); 1910 assert(ctx != NULL); 1911 1912 el1_sysregs_context_restore(get_el1_sysregs_ctx(ctx)); 1913 1914 #if IMAGE_BL31 1915 if (security_state == SECURE) 1916 PUBLISH_EVENT(cm_entering_secure_world); 1917 else 1918 PUBLISH_EVENT(cm_entering_normal_world); 1919 #endif 1920 } 1921 1922 #endif /* ((IMAGE_BL1) || (IMAGE_BL31 && (!CTX_INCLUDE_EL2_REGS))) */ 1923 1924 /******************************************************************************* 1925 * This function populates ELR_EL3 member of 'cpu_context' pertaining to the 1926 * given security state with the given entrypoint 1927 ******************************************************************************/ 1928 void cm_set_elr_el3(uint32_t security_state, uintptr_t entrypoint) 1929 { 1930 cpu_context_t *ctx; 1931 el3_state_t *state; 1932 1933 ctx = cm_get_context(security_state); 1934 assert(ctx != NULL); 1935 1936 /* Populate EL3 state so that ERET jumps to the correct entry */ 1937 state = get_el3state_ctx(ctx); 1938 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 1939 } 1940 1941 /******************************************************************************* 1942 * This function populates ELR_EL3 and SPSR_EL3 members of 'cpu_context' 1943 * pertaining to the given security state 1944 ******************************************************************************/ 1945 void cm_set_elr_spsr_el3(uint32_t security_state, 1946 uintptr_t entrypoint, uint32_t spsr) 1947 { 1948 cpu_context_t *ctx; 1949 el3_state_t *state; 1950 1951 ctx = cm_get_context(security_state); 1952 assert(ctx != NULL); 1953 1954 /* Populate EL3 state so that ERET jumps to the correct entry */ 1955 state = get_el3state_ctx(ctx); 1956 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 1957 write_ctx_reg(state, CTX_SPSR_EL3, spsr); 1958 } 1959 1960 /******************************************************************************* 1961 * This function updates a single bit in the SCR_EL3 member of the 'cpu_context' 1962 * pertaining to the given security state using the value and bit position 1963 * specified in the parameters. It preserves all other bits. 1964 ******************************************************************************/ 1965 void cm_write_scr_el3_bit(uint32_t security_state, 1966 uint32_t bit_pos, 1967 uint32_t value) 1968 { 1969 cpu_context_t *ctx; 1970 el3_state_t *state; 1971 u_register_t scr_el3; 1972 1973 ctx = cm_get_context(security_state); 1974 assert(ctx != NULL); 1975 1976 /* Ensure that the bit position is a valid one */ 1977 assert(((1UL << bit_pos) & SCR_VALID_BIT_MASK) != 0U); 1978 1979 /* Ensure that the 'value' is only a bit wide */ 1980 assert(value <= 1U); 1981 1982 /* 1983 * Get the SCR_EL3 value from the cpu context, clear the desired bit 1984 * and set it to its new value. 1985 */ 1986 state = get_el3state_ctx(ctx); 1987 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 1988 scr_el3 &= ~(1UL << bit_pos); 1989 scr_el3 |= (u_register_t)value << bit_pos; 1990 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 1991 } 1992 1993 /******************************************************************************* 1994 * This function retrieves SCR_EL3 member of 'cpu_context' pertaining to the 1995 * given security state. 1996 ******************************************************************************/ 1997 u_register_t cm_get_scr_el3(uint32_t security_state) 1998 { 1999 cpu_context_t *ctx; 2000 el3_state_t *state; 2001 2002 ctx = cm_get_context(security_state); 2003 assert(ctx != NULL); 2004 2005 /* Populate EL3 state so that ERET jumps to the correct entry */ 2006 state = get_el3state_ctx(ctx); 2007 return read_ctx_reg(state, CTX_SCR_EL3); 2008 } 2009 2010 /******************************************************************************* 2011 * This function is used to program the context that's used for exception 2012 * return. This initializes the SP_EL3 to a pointer to a 'cpu_context' set for 2013 * the required security state 2014 ******************************************************************************/ 2015 void cm_set_next_eret_context(uint32_t security_state) 2016 { 2017 cpu_context_t *ctx; 2018 2019 ctx = cm_get_context(security_state); 2020 assert(ctx != NULL); 2021 2022 cm_set_next_context(ctx); 2023 } 2024