1/* 2 * Copyright (c) 2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <lib/extensions/sysreg128.h> 10 11 .global read_par_el1 12 .global write_par_el1 13 .global read_ttbr0_el1 14 .global write_ttbr0_el1 15 .global read_ttbr1_el1 16 .global write_ttbr1_el1 17 .global read_ttbr0_el2 18 .global write_ttbr0_el2 19 .global read_ttbr1_el2 20 .global write_ttbr1_el2 21 .global read_vttbr_el2 22 .global write_vttbr_el2 23 .global read_rcwmask_el1 24 .global write_rcwmask_el1 25 .global read_rcwsmask_el1 26 .global write_rcwsmask_el1 27 28/* 29 * _mrrs - Move System register to two adjacent general-purpose 30 * registers. 31 * Instruction: MRRS <Xt>, <Xt+1>, (<systemreg>|S<op0>_<op1>_<Cn>_<Cm>_<op2>) 32 * 33 * Arguments/Opcode bit field: 34 * regins: System register opcode. 35 * 36 * Clobbers: x0,x1,x2 37 */ 38.macro _mrrs regins:req 39#if ENABLE_FEAT_D128 == 2 40 is_feat_sysreg128_present_asm x0 41 bne 1f 42 /* If FEAT_SYSREG128 is not implemented then use mrs */ 43 .inst 0xD5300000 | (\regins) /* mrs x0, \regins */ 44 ret 45#endif 461: 47 .inst 0xD5700000 | (\regins) /* mrrs x0, x1, \regins */ 48 ret 49.endm 50 51/* 52 * _msrr - Move two adjacent general-purpose registers to System register. 53 * Instruction: MSRR (<systemreg>|S<op0>_<op1>_<Cn>_<Cm>_<op2>), <Xt>, <Xt+1> 54 * 55 * Arguments/Opcode bit field: 56 * regins: System register opcode. 57 * 58 * Clobbers: x0,x1,x2 59 */ 60.macro _msrr regins:req 61#if ENABLE_FEAT_D128 == 2 62 /* Don't tamper x0 and x1 as they may be used for msrr */ 63 is_feat_sysreg128_present_asm x2 64 bne 1f 65 /* If FEAT_SYSREG128 is not implemented then use msr */ 66 .inst 0xD5100000 | (\regins) /* msr \regins, x0 */ 67 ret 68#endif 691: 70 .inst 0xD5500000 | (\regins) /* msrr \regins, x0, x1 */ 71 ret 72.endm 73 74func read_par_el1 75 _mrrs 0x87400 /* S3_0_C7_C4_0 */ 76endfunc read_par_el1 77 78func write_par_el1 79 _msrr 0x87400 80endfunc write_par_el1 81 82func read_ttbr0_el1 83 _mrrs 0x82000 /* S3_0_C2_C0_0 */ 84endfunc read_ttbr0_el1 85 86func write_ttbr0_el1 87 _msrr 0x82000 88endfunc write_ttbr0_el1 89 90func read_ttbr1_el1 91 _mrrs 0x82020 /* S3_0_C2_C0_1 */ 92endfunc read_ttbr1_el1 93 94func write_ttbr1_el1 95 _msrr 0x82020 96endfunc write_ttbr1_el1 97 98func read_ttbr0_el2 99 _mrrs 0xC2000 /* S3_4_C2_C0_0 */ 100endfunc read_ttbr0_el2 101 102func write_ttbr0_el2 103 _msrr 0xC2000 104endfunc write_ttbr0_el2 105 106func read_ttbr1_el2 107 _mrrs 0xC2020 /* S3_4_C2_C0_1 */ 108endfunc read_ttbr1_el2 109 110func write_ttbr1_el2 111 _msrr 0xC2020 112endfunc write_ttbr1_el2 113 114func read_vttbr_el2 115 _mrrs 0xC2100 /* S3_4_C2_C1_0 */ 116endfunc read_vttbr_el2 117 118func write_vttbr_el2 119 _msrr 0xC2100 120endfunc write_vttbr_el2 121 122func read_rcwmask_el1 123 _mrrs 0x8D0C0 /* S3_0_C13_C0_6 */ 124endfunc read_rcwmask_el1 125 126func write_rcwmask_el1 127 _msrr 0x8D0C0 128endfunc write_rcwmask_el1 129 130func read_rcwsmask_el1 131 _mrrs 0x8D060 /* S3_0_C13_C0_3 */ 132endfunc read_rcwsmask_el1 133 134func write_rcwsmask_el1 135 _msrr 0x8D060 136endfunc write_rcwsmask_el1 137