1/* 2 * Copyright (c) 2024-2025, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <platform_def.h> 10#include <cpu_macros.S> 11 12#include <c1_pro.h> 13 14#define TC_HANDLER(rev) plat_reset_handler_tc##rev 15#define PLAT_RESET_HANDLER(rev) TC_HANDLER(rev) 16 17 .globl plat_arm_calc_core_pos 18 .globl plat_reset_handler 19 20 /* --------------------------------------------------------------------- 21 * unsigned int plat_arm_calc_core_pos(u_register_t mpidr) 22 * 23 * Function to calculate the core position on TC. 24 * 25 * (ClusterId * PLAT_MAX_CPUS_PER_CLUSTER * PLAT_MAX_PE_PER_CPU) + 26 * (CPUId * PLAT_MAX_PE_PER_CPU) + 27 * ThreadId 28 * 29 * which can be simplified as: 30 * 31 * ((ClusterId * PLAT_MAX_CPUS_PER_CLUSTER + CPUId) * PLAT_MAX_PE_PER_CPU) 32 * + ThreadId 33 * --------------------------------------------------------------------- 34 */ 35func plat_arm_calc_core_pos 36 /* 37 * Check for MT bit in MPIDR. If not set, shift MPIDR to left to make it 38 * look as if in a multi-threaded implementation. 39 */ 40 tst x0, #MPIDR_MT_MASK 41 lsl x3, x0, #MPIDR_AFFINITY_BITS 42 csel x3, x3, x0, eq 43 44 /* Extract individual affinity fields from MPIDR */ 45 ubfx x0, x3, #MPIDR_AFF0_SHIFT, #MPIDR_AFFINITY_BITS 46 ubfx x1, x3, #MPIDR_AFF1_SHIFT, #MPIDR_AFFINITY_BITS 47 ubfx x2, x3, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS 48 49 /* Compute linear position */ 50 mov x4, #PLAT_MAX_CPUS_PER_CLUSTER 51 madd x1, x2, x4, x1 52 mov x5, #PLAT_MAX_PE_PER_CPU 53 madd x0, x1, x5, x0 54 ret 55endfunc plat_arm_calc_core_pos 56 57func mark_extllc_presence 58#ifdef MCN_CONFIG_ADDR 59 mov_imm x0, (MCN_CONFIG_ADDR(0)) 60 ldr w1, [x0] 61 ubfx x1, x1, #MCN_CONFIG_SLC_PRESENT_BIT, #1 62 jump_if_cpu_midr C1_PRO_MIDR, ARM_C1_PRO 63 sysreg_bitfield_insert_from_gpr CPUECTLR_EL1, x1, CPUECTLR_EL1_EXTLLC_BIT, 1 64 ret 65ARM_C1_PRO: 66 sysreg_bitfield_insert_from_gpr C1_PRO_IMP_CPUECTLR_EL1, x1, C1_PRO_CPUECTLR2_EL1_EXTLLC_BIT, 1 67#endif 68 ret 69endfunc mark_extllc_presence 70 71func enable_dsu_pmu_el1_access 72 sysreg_bit_set actlr_el2, CPUACTLR_CLUSTERPMUEN 73 sysreg_bit_set actlr_el3, CPUACTLR_CLUSTERPMUEN 74 ret 75endfunc enable_dsu_pmu_el1_access 76 77func TC_HANDLER(3) 78 mov x9, lr 79 bl mark_extllc_presence 80 bl enable_dsu_pmu_el1_access 81 mov lr, x9 82 ret 83endfunc TC_HANDLER(3) 84 85func TC_HANDLER(4) 86 mov x9, lr 87 bl mark_extllc_presence 88 bl enable_dsu_pmu_el1_access 89 mov lr, x9 90 ret 91endfunc TC_HANDLER(4) 92 93 /* ----------------------------------------------------- 94 * void plat_reset_handler(void); 95 * ----------------------------------------------------- 96 */ 97func plat_reset_handler 98 mov x8, lr 99 bl PLAT_RESET_HANDLER(TARGET_PLATFORM) 100 mov lr, x8 101 ret 102endfunc plat_reset_handler 103