1 /* 2 * Copyright (c) 2023-2025, STMicroelectronics - All Rights Reserved 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef STM32MP2_DEF_H 8 #define STM32MP2_DEF_H 9 10 #include <common/tbbr/tbbr_img_def.h> 11 #ifndef __ASSEMBLER__ 12 #include <drivers/st/bsec.h> 13 #endif 14 #include <drivers/st/stm32mp25_rcc.h> 15 #ifndef __ASSEMBLER__ 16 #include <drivers/st/stm32mp2_clk.h> 17 #endif 18 #include <drivers/st/stm32mp2_pwr.h> 19 #include <dt-bindings/clock/stm32mp25-clks.h> 20 #include <dt-bindings/clock/stm32mp25-clksrc.h> 21 #include <dt-bindings/gpio/stm32-gpio.h> 22 #include <dt-bindings/reset/stm32mp25-resets.h> 23 24 #ifndef __ASSEMBLER__ 25 #include <boot_api.h> 26 #include <stm32mp2_private.h> 27 #include <stm32mp_common.h> 28 #include <stm32mp_dt.h> 29 #include <stm32mp_shared_resources.h> 30 #endif 31 32 /******************************************************************************* 33 * CHIP ID 34 ******************************************************************************/ 35 #define STM32MP2_CHIP_ID U(0x505) 36 37 #define STM32MP251A_PART_NB U(0x400B3E6D) 38 #define STM32MP251C_PART_NB U(0x000B306D) 39 #define STM32MP251D_PART_NB U(0xC00B3E6D) 40 #define STM32MP251F_PART_NB U(0x800B306D) 41 #define STM32MP253A_PART_NB U(0x400B3E0C) 42 #define STM32MP253C_PART_NB U(0x000B300C) 43 #define STM32MP253D_PART_NB U(0xC00B3E0C) 44 #define STM32MP253F_PART_NB U(0x800B300C) 45 #define STM32MP255A_PART_NB U(0x40082E00) 46 #define STM32MP255C_PART_NB U(0x00082000) 47 #define STM32MP255D_PART_NB U(0xC0082E00) 48 #define STM32MP255F_PART_NB U(0x80082000) 49 #define STM32MP257A_PART_NB U(0x40002E00) 50 #define STM32MP257C_PART_NB U(0x00002000) 51 #define STM32MP257D_PART_NB U(0xC0002E00) 52 #define STM32MP257F_PART_NB U(0x80002000) 53 54 #define STM32MP2_REV_A U(0x08) 55 #define STM32MP2_REV_B U(0x10) 56 #define STM32MP2_REV_X U(0x12) 57 #define STM32MP2_REV_Y U(0x11) 58 #define STM32MP2_REV_Z U(0x09) 59 60 /******************************************************************************* 61 * PACKAGE ID 62 ******************************************************************************/ 63 #define STM32MP25_PKG_CUSTOM U(0) 64 #define STM32MP25_PKG_AL_VFBGA361 U(1) 65 #define STM32MP25_PKG_AK_VFBGA424 U(3) 66 #define STM32MP25_PKG_AI_TFBGA436 U(5) 67 #define STM32MP25_PKG_UNKNOWN U(7) 68 69 /******************************************************************************* 70 * STM32MP2 memory map related constants 71 ******************************************************************************/ 72 #define STM32MP_SYSRAM_BASE U(0x0E000000) 73 #define STM32MP_SYSRAM_SIZE U(0x00040000) 74 #define SRAM1_BASE U(0x0E040000) 75 #define SRAM1_SIZE_FOR_TFA U(0x00010000) 76 #define RETRAM_BASE U(0x0E080000) 77 #define RETRAM_SIZE U(0x00020000) 78 79 /* DDR configuration */ 80 #define STM32MP_DDR_BASE U(0x80000000) 81 #define STM32MP_DDR_MAX_SIZE UL(0x100000000) /* Max 4GB */ 82 83 /* DDR power initializations */ 84 #ifndef __ASSEMBLER__ 85 enum ddr_type { 86 STM32MP_DDR3, 87 STM32MP_DDR4, 88 STM32MP_LPDDR4 89 }; 90 #endif 91 92 /* Section used inside TF binaries */ 93 #define STM32MP_PARAM_LOAD_SIZE U(0x00002400) /* 9 KB for param */ 94 /* 512 Bytes reserved for header */ 95 #define STM32MP_HEADER_SIZE U(0x00000200) 96 #define STM32MP_HEADER_BASE (STM32MP_SYSRAM_BASE + \ 97 STM32MP_PARAM_LOAD_SIZE) 98 99 /* round_up(STM32MP_PARAM_LOAD_SIZE + STM32MP_HEADER_SIZE, PAGE_SIZE) */ 100 #define STM32MP_HEADER_RESERVED_SIZE U(0x3000) 101 102 #define STM32MP_BINARY_BASE (STM32MP_SYSRAM_BASE + \ 103 STM32MP_PARAM_LOAD_SIZE + \ 104 STM32MP_HEADER_SIZE) 105 106 #define STM32MP_BINARY_SIZE (STM32MP_SYSRAM_SIZE - \ 107 (STM32MP_PARAM_LOAD_SIZE + \ 108 STM32MP_HEADER_SIZE)) 109 110 #define STM32MP_BL2_RO_SIZE U(0x00020000) /* 128 KB */ 111 #define STM32MP_BL2_SIZE U(0x00029000) /* 164 KB for BL2 */ 112 113 /* Allocate remaining sysram to BL31 Binary only */ 114 #define STM32MP_BL31_SIZE (STM32MP_SYSRAM_SIZE - \ 115 STM32MP_BL2_SIZE) 116 117 #define STM32MP_BL2_BASE (STM32MP_SYSRAM_BASE + \ 118 STM32MP_SYSRAM_SIZE - \ 119 STM32MP_BL2_SIZE) 120 121 #define STM32MP_BL2_RO_BASE STM32MP_BL2_BASE 122 123 #define STM32MP_BL2_RW_BASE (STM32MP_BL2_RO_BASE + \ 124 STM32MP_BL2_RO_SIZE) 125 126 #define STM32MP_BL2_RW_SIZE (STM32MP_SYSRAM_BASE + \ 127 STM32MP_SYSRAM_SIZE - \ 128 STM32MP_BL2_RW_BASE) 129 130 /* BL2 and BL32/sp_min require 4 tables */ 131 #define MAX_XLAT_TABLES U(4) /* 16 KB for mapping */ 132 133 /* 134 * MAX_MMAP_REGIONS is usually: 135 * BL stm32mp2_mmap size + mmap regions in *_plat_arch_setup 136 */ 137 #if defined(IMAGE_BL31) 138 #define MAX_MMAP_REGIONS 7 139 #else 140 #define MAX_MMAP_REGIONS 6 141 #endif 142 143 /* DTB initialization value */ 144 #define STM32MP_BL2_DTB_SIZE U(0x00006000) /* 24 KB for DTB */ 145 146 #define STM32MP_BL2_DTB_BASE (STM32MP_BL2_BASE - \ 147 STM32MP_BL2_DTB_SIZE) 148 149 #if defined(IMAGE_BL2) 150 #define STM32MP_DTB_SIZE STM32MP_BL2_DTB_SIZE 151 #define STM32MP_DTB_BASE STM32MP_BL2_DTB_BASE 152 #endif 153 154 #if STM32MP_DDR_FIP_IO_STORAGE 155 #define STM32MP_DDR_FW_BASE SRAM1_BASE 156 #define STM32MP_DDR_FW_DMEM_OFFSET U(0x400) 157 #define STM32MP_DDR_FW_IMEM_OFFSET U(0x800) 158 #define STM32MP_DDR_FW_MAX_SIZE U(0x8800) 159 #endif 160 161 #define STM32MP_FW_CONFIG_MAX_SIZE PAGE_SIZE 162 #define STM32MP_FW_CONFIG_BASE STM32MP_SYSRAM_BASE 163 164 #define STM32MP_BL33_BASE (STM32MP_DDR_BASE + U(0x04000000)) 165 #define STM32MP_BL33_MAX_SIZE U(0x400000) 166 #define STM32MP_HW_CONFIG_BASE (STM32MP_BL33_BASE + \ 167 STM32MP_BL33_MAX_SIZE) 168 #define STM32MP_HW_CONFIG_MAX_SIZE U(0x40000) 169 #define STM32MP_SOC_FW_CONFIG_MAX_SIZE U(0x10000) /* 64kB for BL31 DT */ 170 171 /******************************************************************************* 172 * STM32MP2 device/io map related constants (used for MMU) 173 ******************************************************************************/ 174 #define STM32MP_DEVICE_BASE U(0x40000000) 175 #define STM32MP_DEVICE_SIZE U(0x40000000) 176 177 /******************************************************************************* 178 * STM32MP2 RCC 179 ******************************************************************************/ 180 #define RCC_BASE U(0x44200000) 181 182 /******************************************************************************* 183 * STM32MP2 PWR 184 ******************************************************************************/ 185 #define PWR_BASE U(0x44210000) 186 187 /******************************************************************************* 188 * STM32MP2 GPIO 189 ******************************************************************************/ 190 #define GPIOA_BASE U(0x44240000) 191 #define GPIOB_BASE U(0x44250000) 192 #define GPIOC_BASE U(0x44260000) 193 #define GPIOD_BASE U(0x44270000) 194 #define GPIOE_BASE U(0x44280000) 195 #define GPIOF_BASE U(0x44290000) 196 #define GPIOG_BASE U(0x442A0000) 197 #define GPIOH_BASE U(0x442B0000) 198 #define GPIOI_BASE U(0x442C0000) 199 #define GPIOJ_BASE U(0x442D0000) 200 #define GPIOK_BASE U(0x442E0000) 201 #define GPIOZ_BASE U(0x46200000) 202 #define GPIO_BANK_OFFSET U(0x10000) 203 204 #define STM32MP_GPIOS_PIN_MAX_COUNT 16 205 #define STM32MP_GPIOZ_PIN_MAX_COUNT 8 206 207 /******************************************************************************* 208 * STM32MP2 UART 209 ******************************************************************************/ 210 #define USART1_BASE U(0x40330000) 211 #define USART2_BASE U(0x400E0000) 212 #define USART3_BASE U(0x400F0000) 213 #define UART4_BASE U(0x40100000) 214 #define UART5_BASE U(0x40110000) 215 #define USART6_BASE U(0x40220000) 216 #define UART7_BASE U(0x40370000) 217 #define UART8_BASE U(0x40380000) 218 #define UART9_BASE U(0x402C0000) 219 #define STM32MP_NB_OF_UART U(9) 220 221 /* For UART crash console */ 222 #define STM32MP_DEBUG_USART_CLK_FRQ 64000000 223 /* USART2 on HSI@64MHz, TX on GPIOA4 Alternate 6 */ 224 #ifdef ULTRA_FLY 225 #define STM32MP_DEBUG_USART_BASE USART1_BASE 226 #define DEBUG_UART_TX_GPIO_BANK_ADDRESS GPIOA_BASE 227 #define DEBUG_UART_TX_GPIO_BANK_CLK_REG RCC_GPIOACFGR 228 #define DEBUG_UART_TX_GPIO_BANK_CLK_EN RCC_GPIOxCFGR_GPIOxEN 229 #define DEBUG_UART_TX_GPIO_PORT 3 230 #define DEBUG_UART_TX_GPIO_ALTERNATE 6 231 #define DEBUG_UART_TX_CLKSRC_REG RCC_XBAR8CFGR 232 #define DEBUG_UART_TX_CLKSRC XBAR_SRC_HSI 233 #define DEBUG_UART_TX_EN_REG RCC_USART1CFGR 234 #define DEBUG_UART_TX_EN RCC_UARTxCFGR_UARTxEN 235 #define DEBUG_UART_RST_REG RCC_USART1CFGR 236 #define DEBUG_UART_RST_BIT RCC_UARTxCFGR_UARTxRST 237 #define DEBUG_UART_PREDIV_CFGR RCC_PREDIV19CFGR 238 #define DEBUG_UART_FINDIV_CFGR RCC_FINDIV19CFGR 239 #else 240 #define STM32MP_DEBUG_USART_BASE USART2_BASE 241 #define DEBUG_UART_TX_GPIO_BANK_ADDRESS GPIOA_BASE 242 #define DEBUG_UART_TX_GPIO_BANK_CLK_REG RCC_GPIOACFGR 243 #define DEBUG_UART_TX_GPIO_BANK_CLK_EN RCC_GPIOxCFGR_GPIOxEN 244 #define DEBUG_UART_TX_GPIO_PORT 4 245 #define DEBUG_UART_TX_GPIO_ALTERNATE 6 246 #define DEBUG_UART_TX_CLKSRC_REG RCC_XBAR8CFGR 247 #define DEBUG_UART_TX_CLKSRC XBAR_SRC_HSI 248 #define DEBUG_UART_TX_EN_REG RCC_USART2CFGR 249 #define DEBUG_UART_TX_EN RCC_UARTxCFGR_UARTxEN 250 #define DEBUG_UART_RST_REG RCC_USART2CFGR 251 #define DEBUG_UART_RST_BIT RCC_UARTxCFGR_UARTxRST 252 #define DEBUG_UART_PREDIV_CFGR RCC_PREDIV8CFGR 253 #define DEBUG_UART_FINDIV_CFGR RCC_FINDIV8CFGR 254 #endif 255 256 /******************************************************************************* 257 * STM32MP2 SDMMC 258 ******************************************************************************/ 259 #define STM32MP_SDMMC1_BASE U(0x48220000) 260 #define STM32MP_SDMMC2_BASE U(0x48230000) 261 #define STM32MP_SDMMC3_BASE U(0x48240000) 262 263 /******************************************************************************* 264 * STM32MP2 BSEC / OTP 265 ******************************************************************************/ 266 /* 267 * 367 available OTPs, the other are masked 268 * - ECIES key: 368 to 375 (only readable by bootrom) 269 * - HWKEY: 376 to 383 (never reloadable or readable) 270 */ 271 #define STM32MP2_OTP_MAX_ID U(0x16F) 272 #define STM32MP2_MID_OTP_START U(0x80) 273 #define STM32MP2_UPPER_OTP_START U(0x100) 274 275 /* OTP labels */ 276 #define PART_NUMBER_OTP "part-number-otp" 277 #define REVISION_OTP "rev_otp" 278 #define PACKAGE_OTP "package-otp" 279 #define HCONF1_OTP "otp124" 280 #define NAND_OTP "otp16" 281 #define NAND2_OTP "otp20" 282 #define BOARD_ID_OTP "board-id" 283 #define UID_OTP "uid-otp" 284 #define LIFECYCLE2_OTP "otp18" 285 #define PKH_OTP "otp144" 286 #define ENCKEY_OTP "otp260" 287 288 /* OTP mask */ 289 /* PACKAGE */ 290 #define PACKAGE_OTP_PKG_MASK GENMASK_32(2, 0) 291 #define PACKAGE_OTP_PKG_SHIFT U(0) 292 293 /* IWDG OTP */ 294 #define HCONF1_OTP_IWDG_HW_POS U(0) 295 #define HCONF1_OTP_IWDG_FZ_STOP_POS U(1) 296 #define HCONF1_OTP_IWDG_FZ_STANDBY_POS U(2) 297 298 /* NAND OTP */ 299 /* NAND parameter storage flag */ 300 #define NAND_PARAM_STORED_IN_OTP BIT_32(31) 301 302 /* NAND page size in bytes */ 303 #define NAND_PAGE_SIZE_MASK GENMASK_32(30, 29) 304 #define NAND_PAGE_SIZE_SHIFT U(29) 305 #define NAND_PAGE_SIZE_2K U(0) 306 #define NAND_PAGE_SIZE_4K U(1) 307 #define NAND_PAGE_SIZE_8K U(2) 308 309 /* NAND block size in pages */ 310 #define NAND_BLOCK_SIZE_MASK GENMASK_32(28, 27) 311 #define NAND_BLOCK_SIZE_SHIFT U(27) 312 #define NAND_BLOCK_SIZE_64_PAGES U(0) 313 #define NAND_BLOCK_SIZE_128_PAGES U(1) 314 #define NAND_BLOCK_SIZE_256_PAGES U(2) 315 316 /* NAND number of block (in unit of 256 blocks) */ 317 #define NAND_BLOCK_NB_MASK GENMASK_32(26, 19) 318 #define NAND_BLOCK_NB_SHIFT U(19) 319 #define NAND_BLOCK_NB_UNIT U(256) 320 321 /* NAND bus width in bits */ 322 #define NAND_WIDTH_MASK BIT_32(18) 323 #define NAND_WIDTH_SHIFT U(18) 324 325 /* NAND number of ECC bits per 512 bytes */ 326 #define NAND_ECC_BIT_NB_MASK GENMASK_32(17, 15) 327 #define NAND_ECC_BIT_NB_SHIFT U(15) 328 #define NAND_ECC_BIT_NB_UNSET U(0) 329 #define NAND_ECC_BIT_NB_1_BITS U(1) 330 #define NAND_ECC_BIT_NB_4_BITS U(2) 331 #define NAND_ECC_BIT_NB_8_BITS U(3) 332 #define NAND_ECC_ON_DIE U(4) 333 334 /* NAND number of planes */ 335 #define NAND_PLANE_BIT_NB_MASK BIT_32(14) 336 337 /* NAND2 OTP */ 338 #define NAND2_PAGE_SIZE_SHIFT U(16) 339 340 /* NAND2 config distribution */ 341 #define NAND2_CONFIG_DISTRIB BIT_32(0) 342 #define NAND2_PNAND_NAND2_SNAND_NAND1 U(0) 343 #define NAND2_PNAND_NAND1_SNAND_NAND2 U(1) 344 345 /* MONOTONIC OTP */ 346 #define MAX_MONOTONIC_VALUE U(32) 347 348 /* UID OTP */ 349 #define UID_WORD_NB U(3) 350 351 /* Lifecycle OTP */ 352 #define SECURE_BOOT_CLOSED_SECURE GENMASK_32(3, 0) 353 354 /******************************************************************************* 355 * STM32MP2 TAMP 356 ******************************************************************************/ 357 #define PLAT_MAX_TAMP_INT U(5) 358 #define PLAT_MAX_TAMP_EXT U(3) 359 #define TAMP_BASE U(0x46010000) 360 #define TAMP_SMCR (TAMP_BASE + U(0x20)) 361 #define TAMP_BKP_REGISTER_BASE (TAMP_BASE + U(0x100)) 362 #define TAMP_BKP_REG_CLK CK_BUS_RTC 363 #define TAMP_BKP_SEC_NUMBER U(10) 364 #define TAMP_COUNTR U(0x40) 365 366 #if !(defined(__LINKER__) || defined(__ASSEMBLER__)) 367 static inline uintptr_t tamp_bkpr(uint32_t idx) 368 { 369 return TAMP_BKP_REGISTER_BASE + (idx << 2); 370 } 371 #endif 372 373 /******************************************************************************* 374 * STM32MP2 DDRCTRL 375 ******************************************************************************/ 376 #define DDRCTRL_BASE U(0x48040000) 377 378 /******************************************************************************* 379 * STM32MP2 DDRDBG 380 ******************************************************************************/ 381 #define DDRDBG_BASE U(0x48050000) 382 383 /******************************************************************************* 384 * STM32MP2 DDRPHYC 385 ******************************************************************************/ 386 #define DDRPHYC_BASE U(0x48C00000) 387 388 /******************************************************************************* 389 * Miscellaneous STM32MP1 peripherals base address 390 ******************************************************************************/ 391 #define BSEC_BASE U(0x44000000) 392 #define DBGMCU_BASE U(0x4A010000) 393 #define HASH_BASE U(0x42010000) 394 #define RTC_BASE U(0x46000000) 395 #define STGEN_BASE U(0x48080000) 396 #define SYSCFG_BASE U(0x44230000) 397 398 /******************************************************************************* 399 * STM32MP RIF 400 ******************************************************************************/ 401 #define RISAB3_BASE U(0x42110000) 402 #define RISAB5_BASE U(0x42130000) 403 404 /******************************************************************************* 405 * STM32MP CA35SSC 406 ******************************************************************************/ 407 #define A35SSC_BASE U(0x48800000) 408 409 /******************************************************************************* 410 * REGULATORS 411 ******************************************************************************/ 412 /* 3 PWR + 1 VREFBUF + 14 PMIC regulators + 1 FIXED */ 413 #define PLAT_NB_RDEVS U(19) 414 /* 2 FIXED */ 415 #define PLAT_NB_FIXED_REGUS U(2) 416 /* No GPIO regu */ 417 #define PLAT_NB_GPIO_REGUS U(0) 418 419 /******************************************************************************* 420 * Device Tree defines 421 ******************************************************************************/ 422 #define DT_BSEC_COMPAT "st,stm32mp25-bsec" 423 #define DT_DDR_COMPAT "st,stm32mp2-ddr" 424 #define DT_PWR_COMPAT "st,stm32mp25-pwr" 425 #define DT_RCC_CLK_COMPAT "st,stm32mp25-rcc" 426 #define DT_SDMMC2_COMPAT "st,stm32mp25-sdmmc2" 427 #define DT_UART_COMPAT "st,stm32h7-uart" 428 429 #endif /* STM32MP2_DEF_H */ 430