1 /* 2 * Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <common/bl_common.h> 10 #include <common/debug.h> 11 #include <drivers/arm/smmu_v3.h> 12 #include <fconf_hw_config_getter.h> 13 #include <lib/fconf/fconf.h> 14 #include <lib/fconf/fconf_dyn_cfg_getter.h> 15 #include <lib/mmio.h> 16 17 #include <plat/arm/common/arm_config.h> 18 #include <plat/arm/common/plat_arm.h> 19 #include <plat/common/platform.h> 20 21 #include "fvp_private.h" 22 23 static const struct dyn_cfg_dtb_info_t *hw_config_info __unused; 24 25 void __init bl31_early_platform_setup2(u_register_t arg0, 26 u_register_t arg1, u_register_t arg2, u_register_t arg3) 27 { 28 /* Initialize the console to provide early debug support */ 29 arm_console_boot_init(); 30 31 #if !(TRANSFER_LIST || RESET_TO_BL31 || RESET_TO_BL2) 32 const struct dyn_cfg_dtb_info_t *soc_fw_config_info; 33 34 INFO("BL31 FCONF: FW_CONFIG address = %lx\n", (uintptr_t)arg1); 35 /* Fill the properties struct with the info from the config dtb */ 36 fconf_populate("FW_CONFIG", arg1); 37 38 soc_fw_config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, SOC_FW_CONFIG_ID); 39 if (soc_fw_config_info != NULL) { 40 arg1 = soc_fw_config_info->config_addr; 41 } 42 43 /* 44 * arg2 is currently holding the 'secure' address of HW_CONFIG. 45 * But arm_bl31_early_platform_setup() below expects the 'non-secure' 46 * address of HW_CONFIG (which it will pass to BL33). 47 * This why we need to override arg2 here. 48 */ 49 hw_config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, HW_CONFIG_ID); 50 assert(hw_config_info != NULL); 51 assert(hw_config_info->secondary_config_addr != 0UL); 52 arg2 = hw_config_info->secondary_config_addr; 53 #endif /* !(TRANSFER_LIST || RESET_TO_BL31 || RESET_TO_BL2)*/ 54 55 arm_bl31_early_platform_setup(arg0, arg1, arg2, arg3); 56 57 /* Initialize the platform config for future decision making */ 58 fvp_config_setup(); 59 60 /* 61 * Initialize the correct interconnect for this cluster during cold 62 * boot. No need for locks as no other CPU is active. 63 */ 64 fvp_interconnect_init(); 65 66 /* 67 * Enable coherency in interconnect for the primary CPU's cluster. 68 * Earlier bootloader stages might already do this (e.g. Trusted 69 * Firmware's BL1 does it) but we can't assume so. There is no harm in 70 * executing this code twice anyway. 71 * FVP PSCI code will enable coherency for other clusters. 72 */ 73 fvp_interconnect_enable(); 74 75 /* Initialize System level generic or SP804 timer */ 76 fvp_timer_init(); 77 78 /* On FVP RevC, initialize SMMUv3 */ 79 if ((arm_config.flags & ARM_CONFIG_FVP_HAS_SMMUV3) != 0U) { 80 if (smmuv3_security_init(PLAT_FVP_SMMUV3_BASE) != 0) { 81 /* 82 * Don't proceed for smmuv3 initialization if the 83 * security init failed. 84 */ 85 return; 86 } 87 /* SMMUv3 initialization failure is not fatal */ 88 if (smmuv3_init(PLAT_FVP_SMMUV3_BASE) != 0) { 89 WARN("Failed initializing SMMU.\n"); 90 } 91 } 92 } 93 94 #if !TRANSFER_LIST 95 void __init bl31_plat_arch_setup(void) 96 { 97 int rc __unused; 98 uintptr_t hw_config_base_align __unused; 99 size_t mapped_size_align __unused; 100 101 arm_bl31_plat_arch_setup(); 102 103 /* 104 * For RESET_TO_BL31 systems, BL31 is the first bootloader to run. 105 * So there is no BL2 to load the HW_CONFIG dtb into memory before 106 * control is passed to BL31. The code below relies on dynamic mapping 107 * capability, which is not supported by xlat tables lib V1. 108 * TODO: remove the ARM_XLAT_TABLES_LIB_V1 check when its support 109 * gets deprecated. 110 */ 111 #if !RESET_TO_BL31 && !RESET_TO_BL2 && !ARM_XLAT_TABLES_LIB_V1 112 assert(hw_config_info != NULL); 113 assert(hw_config_info->config_addr != 0UL); 114 115 /* Page aligned address and size if necessary */ 116 hw_config_base_align = page_align(hw_config_info->config_addr, DOWN); 117 mapped_size_align = page_align(hw_config_info->config_max_size, UP); 118 119 if ((hw_config_info->config_addr != hw_config_base_align) && 120 (hw_config_info->config_max_size == mapped_size_align)) { 121 mapped_size_align += PAGE_SIZE; 122 } 123 124 /* 125 * map dynamically HW config region with its aligned base address and 126 * size 127 */ 128 rc = mmap_add_dynamic_region((unsigned long long)hw_config_base_align, 129 hw_config_base_align, 130 mapped_size_align, 131 MT_RO_DATA); 132 if (rc != 0) { 133 ERROR("Error while mapping HW_CONFIG device tree (%d).\n", rc); 134 panic(); 135 } 136 137 /* Populate HW_CONFIG device tree with the mapped address */ 138 fconf_populate("HW_CONFIG", hw_config_info->config_addr); 139 140 /* unmap the HW_CONFIG memory region */ 141 rc = mmap_remove_dynamic_region(hw_config_base_align, mapped_size_align); 142 if (rc != 0) { 143 ERROR("Error while unmapping HW_CONFIG device tree (%d).\n", 144 rc); 145 panic(); 146 } 147 #endif /* !RESET_TO_BL31 && !RESET_TO_BL2 && !ARM_XLAT_TABLES_LIB_V1 */ 148 } 149 #endif /* TRANSFER_LIST */ 150 151 unsigned int plat_get_syscnt_freq2(void) 152 { 153 unsigned int counter_base_frequency; 154 155 #if !RESET_TO_BL31 && !RESET_TO_BL2 156 /* Get the frequency through FCONF API for HW_CONFIG */ 157 counter_base_frequency = FCONF_GET_PROPERTY(hw_config, cpu_timer, clock_freq); 158 if (counter_base_frequency > 0U) { 159 return counter_base_frequency; 160 } 161 #endif 162 163 /* Read the frequency from Frequency modes table */ 164 counter_base_frequency = mmio_read_32(ARM_SYS_CNTCTL_BASE + CNTFID_OFF); 165 166 /* The first entry of the frequency modes table must not be 0 */ 167 if (counter_base_frequency == 0U) { 168 panic(); 169 } 170 171 return counter_base_frequency; 172 } 173