1 /* 2 * Copyright 2022-2023 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <stdbool.h> 9 10 #include <arch_helpers.h> 11 #include <common/bl_common.h> 12 #include <common/debug.h> 13 #include <context.h> 14 #include <drivers/console.h> 15 #include <drivers/generic_delay_timer.h> 16 #include <drivers/nxp/trdc/imx_trdc.h> 17 #include <lib/el3_runtime/context_mgmt.h> 18 #include <lib/mmio.h> 19 #include <lib/xlat_tables/xlat_tables_v2.h> 20 #include <plat/common/platform.h> 21 22 #include <imx8_lpuart.h> 23 #include <plat_imx8.h> 24 #include <platform_def.h> 25 26 #define MAP_BL31_TOTAL \ 27 MAP_REGION_FLAT(BL31_BASE, BL31_LIMIT - BL31_BASE, MT_MEMORY | MT_RW | MT_SECURE) 28 #define MAP_BL31_RO \ 29 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, MT_MEMORY | MT_RO | MT_SECURE) 30 31 static const mmap_region_t imx_mmap[] = { 32 AIPS1_MAP, AIPS2_MAP, AIPS4_MAP, GIC_MAP, 33 TRDC_A_MAP, TRDC_W_MAP, TRDC_M_MAP, 34 TRDC_N_MAP, 35 {0}, 36 }; 37 38 static entry_point_info_t bl32_image_ep_info; 39 static entry_point_info_t bl33_image_ep_info; 40 41 /* get SPSR for BL33 entry */ 42 static uint32_t get_spsr_for_bl33_entry(void) 43 { 44 unsigned long el_status; 45 unsigned long mode; 46 uint32_t spsr; 47 48 /* figure out what mode we enter the non-secure world */ 49 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; 50 el_status &= ID_AA64PFR0_ELX_MASK; 51 52 mode = (el_status) ? MODE_EL2 : MODE_EL1; 53 54 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); 55 return spsr; 56 } 57 58 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 59 u_register_t arg2, u_register_t arg3) 60 { 61 static console_t console; 62 63 console_lpuart_register(IMX_LPUART_BASE, IMX_BOOT_UART_CLK_IN_HZ, 64 IMX_CONSOLE_BAUDRATE, &console); 65 66 /* This console is only used for boot stage */ 67 console_set_scope(&console, CONSOLE_FLAG_BOOT); 68 69 /* 70 * tell BL3-1 where the non-secure software image is located 71 * and the entry state information. 72 */ 73 bl33_image_ep_info.pc = PLAT_NS_IMAGE_OFFSET; 74 bl33_image_ep_info.spsr = get_spsr_for_bl33_entry(); 75 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 76 77 #if defined(SPD_opteed) 78 /* Populate entry point information for BL32 */ 79 SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0); 80 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); 81 bl32_image_ep_info.pc = BL32_BASE; 82 bl32_image_ep_info.spsr = 0; 83 84 /* Pass TEE base and size to bl33 */ 85 bl33_image_ep_info.args.arg1 = BL32_BASE; 86 bl33_image_ep_info.args.arg2 = BL32_SIZE; 87 88 /* Make sure memory is clean */ 89 mmio_write_32(BL32_FDT_OVERLAY_ADDR, 0); 90 bl33_image_ep_info.args.arg3 = BL32_FDT_OVERLAY_ADDR; 91 bl32_image_ep_info.args.arg3 = BL32_FDT_OVERLAY_ADDR; 92 #endif 93 } 94 95 void bl31_plat_arch_setup(void) 96 { 97 /* no coherence memory support on i.MX9 */ 98 const mmap_region_t bl_regions[] = { 99 MAP_BL31_TOTAL, 100 MAP_BL31_RO, 101 }; 102 103 /* Assign all the GPIO pins to non-secure world by default */ 104 mmio_write_32(GPIO2_BASE + 0x10, 0xffffffff); 105 mmio_write_32(GPIO2_BASE + 0x14, 0x3); 106 mmio_write_32(GPIO2_BASE + 0x18, 0xffffffff); 107 mmio_write_32(GPIO2_BASE + 0x1c, 0x3); 108 109 mmio_write_32(GPIO3_BASE + 0x10, 0xffffffff); 110 mmio_write_32(GPIO3_BASE + 0x14, 0x3); 111 mmio_write_32(GPIO3_BASE + 0x18, 0xffffffff); 112 mmio_write_32(GPIO3_BASE + 0x1c, 0x3); 113 114 mmio_write_32(GPIO4_BASE + 0x10, 0xffffffff); 115 mmio_write_32(GPIO4_BASE + 0x14, 0x3); 116 mmio_write_32(GPIO4_BASE + 0x18, 0xffffffff); 117 mmio_write_32(GPIO4_BASE + 0x1c, 0x3); 118 119 mmio_write_32(GPIO1_BASE + 0x10, 0xffffffff); 120 mmio_write_32(GPIO1_BASE + 0x14, 0x3); 121 mmio_write_32(GPIO1_BASE + 0x18, 0xffffffff); 122 mmio_write_32(GPIO1_BASE + 0x1c, 0x3); 123 124 setup_page_tables(bl_regions, imx_mmap); 125 enable_mmu_el3(0); 126 127 /* trdc must be initialized */ 128 trdc_config(); 129 } 130 131 void bl31_platform_setup(void) 132 { 133 generic_delay_timer_init(); 134 135 plat_gic_driver_init(); 136 plat_gic_init(); 137 } 138 139 entry_point_info_t *bl31_plat_get_next_image_ep_info(unsigned int type) 140 { 141 if (type == NON_SECURE) { 142 return &bl33_image_ep_info; 143 } 144 145 if (type == SECURE) { 146 return &bl32_image_ep_info; 147 } 148 149 return NULL; 150 } 151 152 unsigned int plat_get_syscnt_freq2(void) 153 { 154 return COUNTER_FREQUENCY; 155 } 156