1 /* 2 * Copyright (c) 2015-2025, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 #ifndef PLAT_ARM_H 7 #define PLAT_ARM_H 8 9 #include <stdbool.h> 10 #include <stdint.h> 11 12 #include <common/desc_image_load.h> 13 #include <drivers/arm/gic.h> 14 #include <drivers/arm/tzc_common.h> 15 #include <lib/bakery_lock.h> 16 #include <lib/cassert.h> 17 #include <lib/el3_runtime/cpu_data.h> 18 #include <lib/gpt_rme/gpt_rme.h> 19 #include <lib/spinlock.h> 20 #include <lib/transfer_list.h> 21 #include <lib/utils_def.h> 22 #include <lib/xlat_tables/xlat_tables_compat.h> 23 24 /******************************************************************************* 25 * Forward declarations 26 ******************************************************************************/ 27 struct meminfo; 28 struct image_info; 29 struct bl_params; 30 31 typedef struct arm_tzc_regions_info { 32 unsigned long long base; 33 unsigned long long end; 34 unsigned int sec_attr; 35 unsigned int nsaid_permissions; 36 } arm_tzc_regions_info_t; 37 38 typedef struct arm_gpt_info { 39 pas_region_t *pas_region_base; 40 unsigned int pas_region_count; 41 uintptr_t l0_base; 42 uintptr_t l1_base; 43 size_t l0_size; 44 size_t l1_size; 45 gpccr_pps_e pps; 46 gpccr_pgs_e pgs; 47 } arm_gpt_info_t; 48 49 /******************************************************************************* 50 * Default mapping definition of the TrustZone Controller for ARM standard 51 * platforms. 52 * Configure: 53 * - Region 0 with no access; 54 * - Region 1 with secure access only; 55 * - the remaining DRAM regions access from the given Non-Secure masters. 56 ******************************************************************************/ 57 58 #if ENABLE_RME 59 #define ARM_TZC_RME_REGIONS_DEF \ 60 {ARM_AP_TZC_DRAM1_BASE, ARM_AP_TZC_DRAM1_END, TZC_REGION_S_RDWR, 0},\ 61 {ARM_EL3_TZC_DRAM1_BASE, ARM_L1_GPT_END, TZC_REGION_S_RDWR, 0}, \ 62 {ARM_NS_DRAM1_BASE, ARM_NS_DRAM1_END, ARM_TZC_NS_DRAM_S_ACCESS, \ 63 PLAT_ARM_TZC_NS_DEV_ACCESS}, \ 64 /* Realm and Shared area share the same PAS */ \ 65 {ARM_REALM_BASE, ARM_EL3_RMM_SHARED_END, ARM_TZC_NS_DRAM_S_ACCESS, \ 66 PLAT_ARM_TZC_NS_DEV_ACCESS}, \ 67 {ARM_DRAM2_BASE, ARM_DRAM2_END, ARM_TZC_NS_DRAM_S_ACCESS, \ 68 PLAT_ARM_TZC_NS_DEV_ACCESS} 69 #endif 70 71 #if SPM_MM || (SPMC_AT_EL3 && SPMC_AT_EL3_SEL0_SP) 72 #define ARM_TZC_REGIONS_DEF \ 73 {ARM_NS_DRAM1_BASE, ARM_NS_DRAM1_END, ARM_TZC_NS_DRAM_S_ACCESS, \ 74 PLAT_ARM_TZC_NS_DEV_ACCESS}, \ 75 {ARM_AP_TZC_DRAM1_BASE, (PLAT_SP_IMAGE_NS_BUF_BASE - 1), \ 76 TZC_REGION_S_RDWR, 0}, \ 77 {PLAT_SP_IMAGE_NS_BUF_BASE, (PLAT_SP_IMAGE_NS_BUF_BASE + \ 78 PLAT_SP_IMAGE_NS_BUF_SIZE - 1), TZC_REGION_S_NONE, \ 79 PLAT_ARM_TZC_NS_DEV_ACCESS}, \ 80 {PLAT_SP_IMAGE_STACK_BASE, ARM_EL3_TZC_DRAM1_END, \ 81 TZC_REGION_S_RDWR, 0}, \ 82 {ARM_DRAM2_BASE, ARM_DRAM2_END, ARM_TZC_NS_DRAM_S_ACCESS, \ 83 PLAT_ARM_TZC_NS_DEV_ACCESS} 84 85 #elif ENABLE_RME 86 #if (defined(SPD_tspd) || defined(SPD_opteed) || defined(SPD_spmd)) && \ 87 MEASURED_BOOT 88 #define ARM_TZC_REGIONS_DEF \ 89 ARM_TZC_RME_REGIONS_DEF, \ 90 {ARM_EVENT_LOG_DRAM1_BASE, ARM_EVENT_LOG_DRAM1_END, \ 91 TZC_REGION_S_RDWR, 0} 92 #else 93 #define ARM_TZC_REGIONS_DEF \ 94 ARM_TZC_RME_REGIONS_DEF 95 #endif 96 97 #else 98 #define ARM_TZC_REGIONS_DEF \ 99 {ARM_AP_TZC_DRAM1_BASE, ARM_EL3_TZC_DRAM1_END + ARM_L1_GPT_SIZE,\ 100 TZC_REGION_S_RDWR, 0}, \ 101 {ARM_NS_DRAM1_BASE, ARM_NS_DRAM1_END, ARM_TZC_NS_DRAM_S_ACCESS, \ 102 PLAT_ARM_TZC_NS_DEV_ACCESS}, \ 103 {ARM_DRAM2_BASE, ARM_DRAM2_END, ARM_TZC_NS_DRAM_S_ACCESS, \ 104 PLAT_ARM_TZC_NS_DEV_ACCESS} 105 #endif 106 107 #define ARM_CASSERT_MMAP \ 108 CASSERT((ARRAY_SIZE(plat_arm_mmap) - 1) <= PLAT_ARM_MMAP_ENTRIES, \ 109 assert_plat_arm_mmap_mismatch); \ 110 CASSERT((PLAT_ARM_MMAP_ENTRIES + ARM_BL_REGIONS) \ 111 <= MAX_MMAP_REGIONS, \ 112 assert_max_mmap_regions); 113 114 void arm_setup_romlib(void); 115 116 #if defined(IMAGE_BL31) || (!defined(__aarch64__) && defined(IMAGE_BL32)) 117 /* 118 * Use this macro to instantiate lock before it is used in below 119 * arm_lock_xxx() macros 120 */ 121 #define ARM_INSTANTIATE_LOCK static DEFINE_BAKERY_LOCK(arm_lock) 122 #define ARM_LOCK_GET_INSTANCE (&arm_lock) 123 124 #if !HW_ASSISTED_COHERENCY 125 #define ARM_SCMI_INSTANTIATE_LOCK DEFINE_BAKERY_LOCK(arm_scmi_lock) 126 #else 127 #define ARM_SCMI_INSTANTIATE_LOCK spinlock_t arm_scmi_lock 128 #endif 129 #define ARM_SCMI_LOCK_GET_INSTANCE (&arm_scmi_lock) 130 131 /* 132 * These are wrapper macros to the Coherent Memory Bakery Lock API. 133 */ 134 #define arm_lock_init() bakery_lock_init(&arm_lock) 135 #define arm_lock_get() bakery_lock_get(&arm_lock) 136 #define arm_lock_release() bakery_lock_release(&arm_lock) 137 138 #else 139 140 /* 141 * Empty macros for all other BL stages other than BL31 and BL32 142 */ 143 #define ARM_INSTANTIATE_LOCK static int arm_lock __unused 144 #define ARM_LOCK_GET_INSTANCE 0 145 #define arm_lock_init() 146 #define arm_lock_get() 147 #define arm_lock_release() 148 149 #endif /* defined(IMAGE_BL31) || (!defined(__aarch64__) && defined(IMAGE_BL32)) */ 150 151 #ifdef __aarch64__ 152 #define TL_TAG_EXEC_EP_INFO TL_TAG_EXEC_EP_INFO64 153 #define TL_TAG_SRAM_LAYOUT TL_TAG_SRAM_LAYOUT64 154 #else 155 #define TL_TAG_EXEC_EP_INFO TL_TAG_EXEC_EP_INFO32 156 #define TL_TAG_SRAM_LAYOUT TL_TAG_SRAM_LAYOUT32 157 #endif 158 159 #if ARM_RECOM_STATE_ID_ENC 160 /* 161 * Macros used to parse state information from State-ID if it is using the 162 * recommended encoding for State-ID. 163 */ 164 #define ARM_LOCAL_PSTATE_WIDTH 4 165 #define ARM_LOCAL_PSTATE_MASK ((1 << ARM_LOCAL_PSTATE_WIDTH) - 1) 166 167 /* Last in Level for the OS-initiated */ 168 #define ARM_LAST_AT_PLVL_MASK (ARM_LOCAL_PSTATE_MASK << \ 169 (ARM_LOCAL_PSTATE_WIDTH * \ 170 (PLAT_MAX_PWR_LVL + 1))) 171 172 /* Macros to construct the composite power state */ 173 174 /* Make composite power state parameter till power level 0 */ 175 #if PSCI_EXTENDED_STATE_ID 176 177 #define arm_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \ 178 (((lvl0_state) << PSTATE_ID_SHIFT) | ((type) << PSTATE_TYPE_SHIFT)) 179 #else 180 #define arm_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \ 181 (((lvl0_state) << PSTATE_ID_SHIFT) | \ 182 ((pwr_lvl) << PSTATE_PWR_LVL_SHIFT) | \ 183 ((type) << PSTATE_TYPE_SHIFT)) 184 #endif /* __PSCI_EXTENDED_STATE_ID__ */ 185 186 /* Make composite power state parameter till power level 1 */ 187 #define arm_make_pwrstate_lvl1(lvl1_state, lvl0_state, pwr_lvl, type) \ 188 (((lvl1_state) << ARM_LOCAL_PSTATE_WIDTH) | \ 189 arm_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type)) 190 191 /* Make composite power state parameter till power level 2 */ 192 #define arm_make_pwrstate_lvl2(lvl2_state, lvl1_state, lvl0_state, pwr_lvl, type) \ 193 (((lvl2_state) << (ARM_LOCAL_PSTATE_WIDTH * 2)) | \ 194 arm_make_pwrstate_lvl1(lvl1_state, lvl0_state, pwr_lvl, type)) 195 196 #endif /* __ARM_RECOM_STATE_ID_ENC__ */ 197 198 /* ARM State switch error codes */ 199 #define STATE_SW_E_PARAM (-2) 200 #define STATE_SW_E_DENIED (-3) 201 202 /* plat_get_rotpk_info() flags */ 203 #define ARM_ROTPK_REGS_ID 1 204 #define ARM_ROTPK_DEVEL_RSA_ID 2 205 #define ARM_ROTPK_DEVEL_ECDSA_ID 3 206 #define ARM_ROTPK_DEVEL_FULL_DEV_RSA_KEY_ID 4 207 #define ARM_ROTPK_DEVEL_FULL_DEV_ECDSA_KEY_ID 5 208 209 #define ARM_USE_DEVEL_ROTPK \ 210 (ARM_ROTPK_LOCATION_ID == ARM_ROTPK_DEVEL_RSA_ID) || \ 211 (ARM_ROTPK_LOCATION_ID == ARM_ROTPK_DEVEL_ECDSA_ID) || \ 212 (ARM_ROTPK_LOCATION_ID == ARM_ROTPK_DEVEL_FULL_DEV_RSA_KEY_ID) || \ 213 (ARM_ROTPK_LOCATION_ID == ARM_ROTPK_DEVEL_FULL_DEV_ECDSA_KEY_ID) 214 215 /* IO storage utility functions */ 216 int arm_io_setup(void); 217 218 /* Set image specification in IO block policy */ 219 int arm_set_image_source(unsigned int image_id, const char *part_name, 220 uintptr_t *dev_handle, uintptr_t *image_spec); 221 void arm_set_fip_addr(uint32_t active_fw_bank_idx); 222 223 /* Security utility functions */ 224 void arm_tzc400_setup(uintptr_t tzc_base, 225 const arm_tzc_regions_info_t *tzc_regions); 226 struct tzc_dmc500_driver_data; 227 void arm_tzc_dmc500_setup(struct tzc_dmc500_driver_data *plat_driver_data, 228 const arm_tzc_regions_info_t *tzc_regions); 229 230 /* Console utility functions */ 231 void arm_console_boot_init(void); 232 void arm_console_boot_end(void); 233 void arm_console_runtime_init(void); 234 void arm_console_runtime_end(void); 235 236 /* Systimer utility function */ 237 void arm_configure_sys_timer(void); 238 239 /* PM utility functions */ 240 int arm_validate_power_state(unsigned int power_state, 241 psci_power_state_t *req_state); 242 int arm_validate_psci_entrypoint(uintptr_t entrypoint); 243 int arm_validate_ns_entrypoint(uintptr_t entrypoint); 244 void arm_system_pwr_domain_save(void); 245 void arm_system_pwr_domain_resume(void); 246 int arm_psci_read_mem_protect(int *enabled); 247 int arm_nor_psci_write_mem_protect(int val); 248 void arm_nor_psci_do_static_mem_protect(void); 249 void arm_nor_psci_do_dyn_mem_protect(void); 250 int arm_psci_mem_protect_chk(uintptr_t base, u_register_t length); 251 252 /* Topology utility function */ 253 int arm_check_mpidr(u_register_t mpidr); 254 255 /* BL1 utility functions */ 256 void arm_bl1_early_platform_setup(void); 257 void arm_bl1_platform_setup(void); 258 void arm_bl1_plat_arch_setup(void); 259 260 /* BL2 utility functions */ 261 void arm_bl2_early_platform_setup(u_register_t arg0, u_register_t arg1, 262 u_register_t arg2, u_register_t arg3); 263 void arm_bl2_platform_setup(void); 264 void arm_bl2_plat_arch_setup(void); 265 uint32_t arm_get_spsr_for_bl32_entry(void); 266 uint32_t arm_get_spsr_for_bl33_entry(void); 267 int arm_bl2_plat_handle_post_image_load(unsigned int image_id); 268 int arm_bl2_handle_post_image_load(unsigned int image_id); 269 struct bl_params *arm_get_next_bl_params(void); 270 void arm_bl2_setup_next_ep_info(bl_mem_params_node_t *next_param_node); 271 272 /* BL2 at EL3 functions */ 273 void arm_bl2_el3_early_platform_setup(void); 274 void arm_bl2_el3_plat_arch_setup(void); 275 #if ARM_FW_CONFIG_LOAD_ENABLE 276 void arm_bl2_el3_plat_config_load(void); 277 #endif /* ARM_FW_CONFIG_LOAD_ENABLE */ 278 279 /* BL2U utility functions */ 280 void arm_bl2u_early_platform_setup(struct meminfo *mem_layout, 281 void *plat_info); 282 void arm_bl2u_platform_setup(void); 283 void arm_bl2u_plat_arch_setup(void); 284 285 /* BL31 utility functions */ 286 void arm_bl31_early_platform_setup(u_register_t arg0, u_register_t arg1, 287 u_register_t arg2, u_register_t arg3); 288 void arm_bl31_platform_setup(void); 289 void arm_bl31_plat_runtime_setup(void); 290 void arm_bl31_plat_arch_setup(void); 291 292 /* Firmware Handoff utility functions */ 293 void arm_transfer_list_dyn_cfg_init(struct transfer_list_header *secure_tl); 294 void arm_transfer_list_populate_ep_info(bl_mem_params_node_t *next_param_node, 295 struct transfer_list_header *secure_tl); 296 void arm_transfer_list_copy_hw_config(struct transfer_list_header *secure_tl, 297 struct transfer_list_header *ns_tl); 298 struct transfer_list_entry * 299 arm_transfer_list_set_heap_info(struct transfer_list_header *tl); 300 void arm_transfer_list_get_heap_info(void **heap_addr, size_t *heap_size); 301 302 /* TSP utility functions */ 303 void arm_tsp_early_platform_setup(void); 304 305 /* SP_MIN utility functions */ 306 void arm_sp_min_early_platform_setup(u_register_t arg0, u_register_t arg1, 307 u_register_t arg2, u_register_t arg3); 308 void arm_sp_min_plat_runtime_setup(void); 309 void arm_sp_min_plat_arch_setup(void); 310 311 /* FIP TOC validity check */ 312 bool arm_io_is_toc_valid(void); 313 314 /* Utility functions for Dynamic Config */ 315 316 void arm_bl1_set_mbedtls_heap(void); 317 int arm_get_mbedtls_heap(void **heap_addr, size_t *heap_size); 318 319 #if IMAGE_BL2 320 void arm_bl2_dyn_cfg_init(void); 321 #endif /* IMAGE_BL2 */ 322 323 #if MEASURED_BOOT 324 #if DICE_PROTECTION_ENVIRONMENT 325 int arm_set_nt_fw_info(int *ctx_handle); 326 int arm_set_tb_fw_info(int *ctx_handle); 327 int arm_get_tb_fw_info(int *ctx_handle); 328 #else 329 /* Specific to event log backend */ 330 int arm_set_tos_fw_info(uintptr_t log_addr, size_t log_size); 331 int arm_set_nt_fw_info( 332 /* 333 * Currently OP-TEE does not support reading DTBs from Secure memory 334 * and this option should be removed when feature is supported. 335 */ 336 #ifdef SPD_opteed 337 uintptr_t log_addr, 338 #endif 339 size_t log_size, uintptr_t *ns_log_addr); 340 int arm_set_tb_fw_info(uintptr_t log_addr, size_t log_size, 341 size_t log_max_size); 342 int arm_get_tb_fw_info(uint64_t *log_addr, size_t *log_size, 343 size_t *log_max_size); 344 #endif /* DICE_PROTECTION_ENVIRONMENT */ 345 #endif /* MEASURED_BOOT */ 346 347 /* 348 * Free the memory storing initialization code only used during an images boot 349 * time so it can be reclaimed for runtime data 350 */ 351 void arm_free_init_memory(void); 352 353 /* 354 * Make the higher level translation tables read-only 355 */ 356 void arm_xlat_make_tables_readonly(void); 357 358 /* 359 * Mandatory functions required in ARM standard platforms 360 */ 361 unsigned int plat_arm_get_cluster_core_count(u_register_t mpidr); 362 363 /* should not be used, but keep for compatibility */ 364 #if USE_GIC_DRIVER == 0 365 void plat_arm_gic_driver_init(void); 366 void plat_arm_gic_init(void); 367 void plat_arm_gic_cpuif_enable(void); 368 void plat_arm_gic_cpuif_disable(void); 369 void plat_arm_gic_redistif_on(void); 370 void plat_arm_gic_redistif_off(void); 371 void plat_arm_gic_pcpu_init(void); 372 void plat_arm_gic_save(void); 373 void plat_arm_gic_resume(void); 374 #endif 375 void plat_arm_security_setup(void); 376 void plat_arm_pwrc_setup(void); 377 void plat_arm_interconnect_init(void); 378 void plat_arm_interconnect_enter_coherency(void); 379 void plat_arm_interconnect_exit_coherency(void); 380 void plat_arm_program_trusted_mailbox(uintptr_t address); 381 bool plat_arm_bl1_fwu_needed(void); 382 int plat_arm_ni_setup(uintptr_t global_cfg); 383 __dead2 void plat_arm_error_handler(int err); 384 __dead2 void plat_arm_system_reset(void); 385 386 /* 387 * Optional functions in ARM standard platforms 388 */ 389 void plat_arm_override_gicr_frames(const uintptr_t *plat_gicr_frames); 390 int arm_get_rotpk_info(void *cookie, void **key_ptr, unsigned int *key_len, 391 unsigned int *flags); 392 int arm_get_rotpk_info_regs(void **key_ptr, unsigned int *key_len, 393 unsigned int *flags); 394 int arm_get_rotpk_info_cc(void **key_ptr, unsigned int *key_len, 395 unsigned int *flags); 396 int arm_get_rotpk_info_dev(void **key_ptr, unsigned int *key_len, 397 unsigned int *flags); 398 399 #if ARM_PLAT_MT 400 unsigned int plat_arm_get_cpu_pe_count(u_register_t mpidr); 401 #endif 402 403 unsigned int plat_cluster_id_by_mpidr(u_register_t mpidr); 404 405 /* 406 * This function is called after loading SCP_BL2 image and it is used to perform 407 * any platform-specific actions required to handle the SCP firmware. 408 */ 409 int plat_arm_bl2_handle_scp_bl2(struct image_info *scp_bl2_image_info); 410 411 /* 412 * Optional functions required in ARM standard platforms 413 */ 414 void plat_arm_io_setup(void); 415 int plat_arm_get_alt_image_source( 416 unsigned int image_id, 417 uintptr_t *dev_handle, 418 uintptr_t *image_spec); 419 unsigned int plat_arm_calc_core_pos(u_register_t mpidr); 420 const mmap_region_t *plat_arm_get_mmap(void); 421 422 const arm_gpt_info_t *plat_arm_get_gpt_info(void); 423 void arm_gpt_setup(void); 424 425 /* Allow platform to override psci_pm_ops during runtime */ 426 const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops); 427 428 /* Execution state switch in ARM platforms */ 429 int arm_execution_state_switch(unsigned int smc_fid, 430 uint32_t pc_hi, 431 uint32_t pc_lo, 432 uint32_t cookie_hi, 433 uint32_t cookie_lo, 434 void *handle); 435 436 /* Optional functions for SP_MIN */ 437 void plat_arm_sp_min_early_platform_setup(u_register_t arg0, u_register_t arg1, 438 u_register_t arg2, u_register_t arg3); 439 440 /* global variables */ 441 extern plat_psci_ops_t plat_arm_psci_pm_ops; 442 extern const mmap_region_t plat_arm_mmap[]; 443 extern const unsigned int arm_pm_idle_states[]; 444 extern struct transfer_list_header *secure_tl; 445 446 /* secure watchdog */ 447 void plat_arm_secure_wdt_start(void); 448 void plat_arm_secure_wdt_stop(void); 449 void plat_arm_secure_wdt_refresh(void); 450 451 /* Get SOC-ID of ARM platform */ 452 uint32_t plat_arm_get_soc_id(void); 453 454 #endif /* PLAT_ARM_H */ 455