1 /* 2 * Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef ARCH_HELPERS_H 8 #define ARCH_HELPERS_H 9 10 #include <cdefs.h> 11 #include <stdbool.h> 12 #include <stdint.h> 13 #include <string.h> 14 15 #include <arch.h> 16 #include <lib/extensions/sysreg128.h> 17 18 /********************************************************************** 19 * Macros which create inline functions to read or write CPU system 20 * registers 21 *********************************************************************/ 22 23 #define _DEFINE_SYSREG_READ_FUNC(_name, _reg_name) \ 24 static inline u_register_t read_ ## _name(void) \ 25 { \ 26 u_register_t v; \ 27 __asm__ volatile ("mrs %0, " #_reg_name : "=r" (v)); \ 28 return v; \ 29 } 30 31 #define _DEFINE_SYSREG_READ_FUNC_NV(_name, _reg_name) \ 32 static inline u_register_t read_ ## _name(void) \ 33 { \ 34 u_register_t v; \ 35 __asm__ ("mrs %0, " #_reg_name : "=r" (v)); \ 36 return v; \ 37 } 38 39 #define _DEFINE_SYSREG_WRITE_FUNC(_name, _reg_name) \ 40 static inline void write_ ## _name(u_register_t v) \ 41 { \ 42 __asm__ volatile ("msr " #_reg_name ", %0" : : "r" (v)); \ 43 } 44 45 #define SYSREG_WRITE_CONST(reg_name, v) \ 46 __asm__ volatile ("msr " #reg_name ", %0" : : "i" (v)) 47 48 /* Define read function for system register */ 49 #define DEFINE_SYSREG_READ_FUNC(_name) \ 50 _DEFINE_SYSREG_READ_FUNC(_name, _name) 51 52 /* Define read & write function for system register */ 53 #define DEFINE_SYSREG_RW_FUNCS(_name) \ 54 _DEFINE_SYSREG_READ_FUNC(_name, _name) \ 55 _DEFINE_SYSREG_WRITE_FUNC(_name, _name) 56 57 /* Define read & write function for renamed system register */ 58 #define DEFINE_RENAME_SYSREG_RW_FUNCS(_name, _reg_name) \ 59 _DEFINE_SYSREG_READ_FUNC(_name, _reg_name) \ 60 _DEFINE_SYSREG_WRITE_FUNC(_name, _reg_name) 61 62 /* Define read function for renamed system register */ 63 #define DEFINE_RENAME_SYSREG_READ_FUNC(_name, _reg_name) \ 64 _DEFINE_SYSREG_READ_FUNC(_name, _reg_name) 65 66 /* Define write function for renamed system register */ 67 #define DEFINE_RENAME_SYSREG_WRITE_FUNC(_name, _reg_name) \ 68 _DEFINE_SYSREG_WRITE_FUNC(_name, _reg_name) 69 70 /* Define read function for ID register (w/o volatile qualifier) */ 71 #define DEFINE_IDREG_READ_FUNC(_name) \ 72 _DEFINE_SYSREG_READ_FUNC_NV(_name, _name) 73 74 /* Define read function for renamed ID register (w/o volatile qualifier) */ 75 #define DEFINE_RENAME_IDREG_READ_FUNC(_name, _reg_name) \ 76 _DEFINE_SYSREG_READ_FUNC_NV(_name, _reg_name) 77 78 /********************************************************************** 79 * Macros to create inline functions for system instructions 80 *********************************************************************/ 81 82 /* Define function for simple system instruction */ 83 #define DEFINE_SYSOP_FUNC(_op) \ 84 static inline void _op(void) \ 85 { \ 86 __asm__ (#_op); \ 87 } 88 89 /* Define function for system instruction with register parameter */ 90 #define DEFINE_SYSOP_PARAM_FUNC(_op) \ 91 static inline void _op(uint64_t v) \ 92 { \ 93 __asm__ (#_op " %0" : : "r" (v)); \ 94 } 95 96 /* Define function for system instruction with type specifier */ 97 #define DEFINE_SYSOP_TYPE_FUNC(_op, _type) \ 98 static inline void _op ## _type(void) \ 99 { \ 100 __asm__ (#_op " " #_type : : : "memory"); \ 101 } 102 103 /* Define function for system instruction with register parameter */ 104 #define DEFINE_SYSOP_TYPE_PARAM_FUNC(_op, _type) \ 105 static inline void _op ## _type(uint64_t v) \ 106 { \ 107 __asm__ (#_op " " #_type ", %0" : : "r" (v)); \ 108 } 109 110 /******************************************************************************* 111 * TLB maintenance accessor prototypes 112 ******************************************************************************/ 113 114 #if ERRATA_A57_813419 || ERRATA_A76_1286807 115 /* 116 * Define function for TLBI instruction with type specifier that implements 117 * the workaround for errata 813419 of Cortex-A57 or errata 1286807 of 118 * Cortex-A76. 119 */ 120 #define DEFINE_TLBIOP_ERRATA_TYPE_FUNC(_type)\ 121 static inline void tlbi ## _type(void) \ 122 { \ 123 __asm__("tlbi " #_type "\n" \ 124 "dsb ish\n" \ 125 "tlbi " #_type); \ 126 } 127 128 /* 129 * Define function for TLBI instruction with register parameter that implements 130 * the workaround for errata 813419 of Cortex-A57 or errata 1286807 of 131 * Cortex-A76. 132 */ 133 #define DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(_type) \ 134 static inline void tlbi ## _type(uint64_t v) \ 135 { \ 136 __asm__("tlbi " #_type ", %0\n" \ 137 "dsb ish\n" \ 138 "tlbi " #_type ", %0" : : "r" (v)); \ 139 } 140 #endif /* ERRATA_A57_813419 */ 141 142 #if ERRATA_A53_819472 || ERRATA_A53_824069 || ERRATA_A53_827319 143 /* 144 * Define function for DC instruction with register parameter that enables 145 * the workaround for errata 819472, 824069 and 827319 of Cortex-A53. 146 */ 147 #define DEFINE_DCOP_ERRATA_A53_TYPE_PARAM_FUNC(_name, _type) \ 148 static inline void dc ## _name(uint64_t v) \ 149 { \ 150 __asm__("dc " #_type ", %0" : : "r" (v)); \ 151 } 152 #endif /* ERRATA_A53_819472 || ERRATA_A53_824069 || ERRATA_A53_827319 */ 153 154 #if ERRATA_A57_813419 155 DEFINE_SYSOP_TYPE_FUNC(tlbi, alle1) 156 DEFINE_SYSOP_TYPE_FUNC(tlbi, alle1is) 157 DEFINE_SYSOP_TYPE_FUNC(tlbi, alle2) 158 DEFINE_SYSOP_TYPE_FUNC(tlbi, alle2is) 159 DEFINE_TLBIOP_ERRATA_TYPE_FUNC(alle3) 160 DEFINE_TLBIOP_ERRATA_TYPE_FUNC(alle3is) 161 DEFINE_SYSOP_TYPE_FUNC(tlbi, vmalle1) 162 #elif ERRATA_A76_1286807 163 DEFINE_TLBIOP_ERRATA_TYPE_FUNC(alle1) 164 DEFINE_TLBIOP_ERRATA_TYPE_FUNC(alle1is) 165 DEFINE_TLBIOP_ERRATA_TYPE_FUNC(alle2) 166 DEFINE_TLBIOP_ERRATA_TYPE_FUNC(alle2is) 167 DEFINE_TLBIOP_ERRATA_TYPE_FUNC(alle3) 168 DEFINE_TLBIOP_ERRATA_TYPE_FUNC(alle3is) 169 DEFINE_TLBIOP_ERRATA_TYPE_FUNC(vmalle1) 170 #else 171 DEFINE_SYSOP_TYPE_FUNC(tlbi, alle1) 172 DEFINE_SYSOP_TYPE_FUNC(tlbi, alle1is) 173 DEFINE_SYSOP_TYPE_FUNC(tlbi, alle2) 174 DEFINE_SYSOP_TYPE_FUNC(tlbi, alle2is) 175 DEFINE_SYSOP_TYPE_FUNC(tlbi, alle3) 176 DEFINE_SYSOP_TYPE_FUNC(tlbi, alle3is) 177 DEFINE_SYSOP_TYPE_FUNC(tlbi, vmalle1) 178 #endif 179 180 #if ERRATA_A57_813419 181 DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vaae1is) 182 DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vaale1is) 183 DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vae2is) 184 DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vale2is) 185 DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(vae3is) 186 DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(vale3is) 187 #elif ERRATA_A76_1286807 188 DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(vaae1is) 189 DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(vaale1is) 190 DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(vae2is) 191 DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(vale2is) 192 DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(vae3is) 193 DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(vale3is) 194 #else 195 DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vaae1is) 196 DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vaale1is) 197 DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vae2is) 198 DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vale2is) 199 DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vae3is) 200 DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vale3is) 201 #endif 202 203 /******************************************************************************* 204 * Cache maintenance accessor prototypes 205 ******************************************************************************/ 206 DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, isw) 207 DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, cisw) 208 #if ERRATA_A53_827319 209 DEFINE_DCOP_ERRATA_A53_TYPE_PARAM_FUNC(csw, cisw) 210 #else 211 DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, csw) 212 #endif 213 #if ERRATA_A53_819472 || ERRATA_A53_824069 || ERRATA_A53_827319 214 DEFINE_DCOP_ERRATA_A53_TYPE_PARAM_FUNC(cvac, civac) 215 #else 216 DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, cvac) 217 #endif 218 DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, ivac) 219 DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, civac) 220 #if ERRATA_A53_819472 || ERRATA_A53_824069 || ERRATA_A53_827319 221 DEFINE_DCOP_ERRATA_A53_TYPE_PARAM_FUNC(cvau, civac) 222 #else 223 DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, cvau) 224 #endif 225 DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, zva) 226 227 /******************************************************************************* 228 * Address translation accessor prototypes 229 ******************************************************************************/ 230 DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s12e1r) 231 DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s12e1w) 232 DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s12e0r) 233 DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s12e0w) 234 DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s1e1r) 235 DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s1e2r) 236 DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s1e3r) 237 238 /******************************************************************************* 239 * Strip Pointer Authentication Code 240 ******************************************************************************/ 241 DEFINE_SYSOP_PARAM_FUNC(xpaci) 242 243 void flush_dcache_range(uintptr_t addr, size_t size); 244 void flush_dcache_to_popa_range(uintptr_t addr, size_t size); 245 void flush_dcache_to_popa_range_mte2(uintptr_t addr, size_t size); 246 void clean_dcache_range(uintptr_t addr, size_t size); 247 void inv_dcache_range(uintptr_t addr, size_t size); 248 bool is_dcache_enabled(void); 249 250 void dcsw_op_louis(u_register_t op_type); 251 void dcsw_op_all(u_register_t op_type); 252 253 void disable_mmu_el1(void); 254 void disable_mmu_el3(void); 255 void disable_mpu_el2(void); 256 void disable_mmu_icache_el1(void); 257 void disable_mmu_icache_el3(void); 258 void disable_mpu_icache_el2(void); 259 260 /******************************************************************************* 261 * Misc. accessor prototypes 262 ******************************************************************************/ 263 264 #define write_daifclr(val) SYSREG_WRITE_CONST(daifclr, val) 265 #define write_daifset(val) SYSREG_WRITE_CONST(daifset, val) 266 267 #if ENABLE_FEAT_D128 268 DECLARE_SYSREG128_RW_FUNCS(par_el1) 269 #else 270 DEFINE_SYSREG_RW_FUNCS(par_el1) 271 #endif 272 273 DEFINE_IDREG_READ_FUNC(id_pfr1_el1) 274 DEFINE_IDREG_READ_FUNC(id_aa64isar0_el1) 275 DEFINE_IDREG_READ_FUNC(id_aa64isar1_el1) 276 DEFINE_RENAME_IDREG_READ_FUNC(id_aa64isar2_el1, ID_AA64ISAR2_EL1) 277 DEFINE_IDREG_READ_FUNC(id_aa64pfr0_el1) 278 DEFINE_IDREG_READ_FUNC(id_aa64pfr1_el1) 279 DEFINE_RENAME_IDREG_READ_FUNC(id_aa64pfr2_el1, ID_AA64PFR2_EL1) 280 DEFINE_IDREG_READ_FUNC(id_aa64dfr0_el1) 281 DEFINE_IDREG_READ_FUNC(id_aa64dfr1_el1) 282 DEFINE_IDREG_READ_FUNC(id_afr0_el1) 283 DEFINE_SYSREG_READ_FUNC(CurrentEl) 284 DEFINE_SYSREG_READ_FUNC(ctr_el0) 285 DEFINE_SYSREG_RW_FUNCS(daif) 286 DEFINE_SYSREG_RW_FUNCS(spsr_el1) 287 DEFINE_SYSREG_RW_FUNCS(spsr_el2) 288 DEFINE_SYSREG_RW_FUNCS(spsr_el3) 289 DEFINE_SYSREG_RW_FUNCS(elr_el1) 290 DEFINE_SYSREG_RW_FUNCS(elr_el2) 291 DEFINE_SYSREG_RW_FUNCS(elr_el3) 292 DEFINE_SYSREG_RW_FUNCS(mdccsr_el0) 293 DEFINE_SYSREG_RW_FUNCS(mdccint_el1) 294 DEFINE_SYSREG_RW_FUNCS(dbgdtrrx_el0) 295 DEFINE_SYSREG_RW_FUNCS(dbgdtrtx_el0) 296 DEFINE_SYSREG_RW_FUNCS(sp_el1) 297 DEFINE_SYSREG_RW_FUNCS(sp_el2) 298 DEFINE_SYSREG_RW_FUNCS(dbgprcr_el1) 299 300 DEFINE_SYSOP_FUNC(wfi) 301 DEFINE_SYSOP_FUNC(wfe) 302 DEFINE_SYSOP_FUNC(sev) 303 DEFINE_SYSOP_TYPE_FUNC(dsb, sy) 304 DEFINE_SYSOP_TYPE_FUNC(dmb, sy) 305 DEFINE_SYSOP_TYPE_FUNC(dmb, st) 306 DEFINE_SYSOP_TYPE_FUNC(dmb, ld) 307 DEFINE_SYSOP_TYPE_FUNC(dsb, ish) 308 DEFINE_SYSOP_TYPE_FUNC(dsb, osh) 309 DEFINE_SYSOP_TYPE_FUNC(dsb, nsh) 310 DEFINE_SYSOP_TYPE_FUNC(dsb, ishst) 311 DEFINE_SYSOP_TYPE_FUNC(dsb, oshst) 312 DEFINE_SYSOP_TYPE_FUNC(dmb, oshld) 313 DEFINE_SYSOP_TYPE_FUNC(dmb, oshst) 314 DEFINE_SYSOP_TYPE_FUNC(dmb, osh) 315 DEFINE_SYSOP_TYPE_FUNC(dmb, nshld) 316 DEFINE_SYSOP_TYPE_FUNC(dmb, nshst) 317 DEFINE_SYSOP_TYPE_FUNC(dmb, nsh) 318 DEFINE_SYSOP_TYPE_FUNC(dmb, ishld) 319 DEFINE_SYSOP_TYPE_FUNC(dmb, ishst) 320 DEFINE_SYSOP_TYPE_FUNC(dmb, ish) 321 DEFINE_SYSOP_FUNC(isb) 322 323 static inline void enable_irq(void) 324 { 325 /* 326 * The compiler memory barrier will prevent the compiler from 327 * scheduling non-volatile memory access after the write to the 328 * register. 329 * 330 * This could happen if some initialization code issues non-volatile 331 * accesses to an area used by an interrupt handler, in the assumption 332 * that it is safe as the interrupts are disabled at the time it does 333 * that (according to program order). However, non-volatile accesses 334 * are not necessarily in program order relatively with volatile inline 335 * assembly statements (and volatile accesses). 336 */ 337 COMPILER_BARRIER(); 338 write_daifclr(DAIF_IRQ_BIT); 339 isb(); 340 } 341 342 static inline void enable_fiq(void) 343 { 344 COMPILER_BARRIER(); 345 write_daifclr(DAIF_FIQ_BIT); 346 isb(); 347 } 348 349 static inline void enable_serror(void) 350 { 351 COMPILER_BARRIER(); 352 write_daifclr(DAIF_ABT_BIT); 353 isb(); 354 } 355 356 static inline void enable_debug_exceptions(void) 357 { 358 COMPILER_BARRIER(); 359 write_daifclr(DAIF_DBG_BIT); 360 isb(); 361 } 362 363 static inline void disable_irq(void) 364 { 365 COMPILER_BARRIER(); 366 write_daifset(DAIF_IRQ_BIT); 367 isb(); 368 } 369 370 static inline void disable_fiq(void) 371 { 372 COMPILER_BARRIER(); 373 write_daifset(DAIF_FIQ_BIT); 374 isb(); 375 } 376 377 static inline void disable_serror(void) 378 { 379 COMPILER_BARRIER(); 380 write_daifset(DAIF_ABT_BIT); 381 isb(); 382 } 383 384 static inline void disable_debug_exceptions(void) 385 { 386 COMPILER_BARRIER(); 387 write_daifset(DAIF_DBG_BIT); 388 isb(); 389 } 390 391 void __dead2 smc(uint64_t x0, uint64_t x1, uint64_t x2, uint64_t x3, 392 uint64_t x4, uint64_t x5, uint64_t x6, uint64_t x7); 393 394 /******************************************************************************* 395 * System register accessor prototypes 396 ******************************************************************************/ 397 DEFINE_IDREG_READ_FUNC(midr_el1) 398 DEFINE_SYSREG_READ_FUNC(mpidr_el1) 399 DEFINE_IDREG_READ_FUNC(id_aa64mmfr0_el1) 400 DEFINE_IDREG_READ_FUNC(id_aa64mmfr1_el1) 401 402 DEFINE_SYSREG_RW_FUNCS(scr_el3) 403 DEFINE_SYSREG_RW_FUNCS(hcr_el2) 404 405 DEFINE_SYSREG_RW_FUNCS(vbar_el1) 406 DEFINE_SYSREG_RW_FUNCS(vbar_el2) 407 DEFINE_SYSREG_RW_FUNCS(vbar_el3) 408 409 DEFINE_SYSREG_RW_FUNCS(sctlr_el1) 410 DEFINE_SYSREG_RW_FUNCS(sctlr_el2) 411 DEFINE_SYSREG_RW_FUNCS(sctlr_el3) 412 413 DEFINE_SYSREG_RW_FUNCS(actlr_el1) 414 DEFINE_SYSREG_RW_FUNCS(actlr_el2) 415 DEFINE_SYSREG_RW_FUNCS(actlr_el3) 416 417 DEFINE_SYSREG_RW_FUNCS(esr_el1) 418 DEFINE_SYSREG_RW_FUNCS(esr_el2) 419 DEFINE_SYSREG_RW_FUNCS(esr_el3) 420 421 DEFINE_SYSREG_RW_FUNCS(afsr0_el1) 422 DEFINE_SYSREG_RW_FUNCS(afsr0_el2) 423 DEFINE_SYSREG_RW_FUNCS(afsr0_el3) 424 425 DEFINE_SYSREG_RW_FUNCS(afsr1_el1) 426 DEFINE_SYSREG_RW_FUNCS(afsr1_el2) 427 DEFINE_SYSREG_RW_FUNCS(afsr1_el3) 428 429 DEFINE_SYSREG_RW_FUNCS(far_el1) 430 DEFINE_SYSREG_RW_FUNCS(far_el2) 431 DEFINE_SYSREG_RW_FUNCS(far_el3) 432 433 DEFINE_SYSREG_RW_FUNCS(mair_el1) 434 DEFINE_SYSREG_RW_FUNCS(mair_el2) 435 DEFINE_SYSREG_RW_FUNCS(mair_el3) 436 437 DEFINE_SYSREG_RW_FUNCS(amair_el1) 438 DEFINE_SYSREG_RW_FUNCS(amair_el2) 439 DEFINE_SYSREG_RW_FUNCS(amair_el3) 440 441 DEFINE_SYSREG_READ_FUNC(rvbar_el1) 442 DEFINE_SYSREG_READ_FUNC(rvbar_el2) 443 DEFINE_SYSREG_READ_FUNC(rvbar_el3) 444 445 DEFINE_SYSREG_RW_FUNCS(rmr_el1) 446 DEFINE_SYSREG_RW_FUNCS(rmr_el2) 447 DEFINE_SYSREG_RW_FUNCS(rmr_el3) 448 449 DEFINE_SYSREG_RW_FUNCS(tcr_el1) 450 DEFINE_SYSREG_RW_FUNCS(tcr_el2) 451 DEFINE_SYSREG_RW_FUNCS(tcr_el3) 452 453 #if ENABLE_FEAT_D128 454 DECLARE_SYSREG128_RW_FUNCS(ttbr0_el1) 455 DECLARE_SYSREG128_RW_FUNCS(ttbr1_el1) 456 DECLARE_SYSREG128_RW_FUNCS(ttbr0_el2) 457 DECLARE_SYSREG128_RW_FUNCS(ttbr1_el2) 458 DECLARE_SYSREG128_RW_FUNCS(vttbr_el2) 459 #else 460 DEFINE_SYSREG_RW_FUNCS(ttbr0_el1) 461 DEFINE_SYSREG_RW_FUNCS(ttbr1_el1) 462 DEFINE_SYSREG_RW_FUNCS(ttbr0_el2) 463 DEFINE_RENAME_SYSREG_RW_FUNCS(ttbr1_el2, TTBR1_EL2) 464 DEFINE_SYSREG_RW_FUNCS(vttbr_el2) 465 #endif 466 467 DEFINE_SYSREG_RW_FUNCS(ttbr0_el3) 468 469 DEFINE_SYSREG_RW_FUNCS(cptr_el2) 470 DEFINE_SYSREG_RW_FUNCS(cptr_el3) 471 472 DEFINE_SYSREG_RW_FUNCS(cpacr_el1) 473 DEFINE_SYSREG_RW_FUNCS(cntfrq_el0) 474 DEFINE_SYSREG_RW_FUNCS(cnthp_ctl_el2) 475 DEFINE_SYSREG_RW_FUNCS(cnthp_tval_el2) 476 DEFINE_SYSREG_RW_FUNCS(cnthp_cval_el2) 477 DEFINE_SYSREG_RW_FUNCS(cntps_ctl_el1) 478 DEFINE_SYSREG_RW_FUNCS(cntps_tval_el1) 479 DEFINE_SYSREG_RW_FUNCS(cntps_cval_el1) 480 DEFINE_SYSREG_RW_FUNCS(cntp_ctl_el0) 481 DEFINE_SYSREG_RW_FUNCS(cntp_tval_el0) 482 DEFINE_SYSREG_RW_FUNCS(cntp_cval_el0) 483 DEFINE_SYSREG_READ_FUNC(cntpct_el0) 484 DEFINE_SYSREG_RW_FUNCS(cnthctl_el2) 485 DEFINE_SYSREG_RW_FUNCS(cntv_ctl_el0) 486 DEFINE_SYSREG_RW_FUNCS(cntv_cval_el0) 487 DEFINE_SYSREG_RW_FUNCS(cntkctl_el1) 488 489 DEFINE_SYSREG_RW_FUNCS(vtcr_el2) 490 491 #define get_cntp_ctl_enable(x) (((x) >> CNTP_CTL_ENABLE_SHIFT) & \ 492 CNTP_CTL_ENABLE_MASK) 493 #define get_cntp_ctl_imask(x) (((x) >> CNTP_CTL_IMASK_SHIFT) & \ 494 CNTP_CTL_IMASK_MASK) 495 #define get_cntp_ctl_istatus(x) (((x) >> CNTP_CTL_ISTATUS_SHIFT) & \ 496 CNTP_CTL_ISTATUS_MASK) 497 498 #define set_cntp_ctl_enable(x) ((x) |= (U(1) << CNTP_CTL_ENABLE_SHIFT)) 499 #define set_cntp_ctl_imask(x) ((x) |= (U(1) << CNTP_CTL_IMASK_SHIFT)) 500 501 #define clr_cntp_ctl_enable(x) ((x) &= ~(U(1) << CNTP_CTL_ENABLE_SHIFT)) 502 #define clr_cntp_ctl_imask(x) ((x) &= ~(U(1) << CNTP_CTL_IMASK_SHIFT)) 503 504 DEFINE_SYSREG_RW_FUNCS(tpidr_el0) 505 DEFINE_SYSREG_RW_FUNCS(tpidr_el1) 506 DEFINE_SYSREG_RW_FUNCS(tpidr_el2) 507 DEFINE_SYSREG_RW_FUNCS(tpidr_el3) 508 509 DEFINE_SYSREG_RW_FUNCS(cntvoff_el2) 510 511 DEFINE_SYSREG_RW_FUNCS(vpidr_el2) 512 DEFINE_SYSREG_RW_FUNCS(vmpidr_el2) 513 514 DEFINE_SYSREG_RW_FUNCS(hacr_el2) 515 DEFINE_SYSREG_RW_FUNCS(hpfar_el2) 516 517 DEFINE_SYSREG_RW_FUNCS(dbgvcr32_el2) 518 DEFINE_RENAME_SYSREG_RW_FUNCS(ich_hcr_el2, ICH_HCR_EL2) 519 DEFINE_RENAME_SYSREG_RW_FUNCS(ich_vmcr_el2, ICH_VMCR_EL2) 520 521 DEFINE_SYSREG_READ_FUNC(isr_el1) 522 523 DEFINE_SYSREG_RW_FUNCS(mdscr_el1) 524 DEFINE_SYSREG_RW_FUNCS(mdcr_el2) 525 DEFINE_SYSREG_RW_FUNCS(mdcr_el3) 526 DEFINE_SYSREG_RW_FUNCS(hstr_el2) 527 DEFINE_SYSREG_RW_FUNCS(pmcr_el0) 528 529 DEFINE_SYSREG_RW_FUNCS(csselr_el1) 530 DEFINE_SYSREG_RW_FUNCS(tpidrro_el0) 531 DEFINE_SYSREG_RW_FUNCS(contextidr_el1) 532 DEFINE_SYSREG_RW_FUNCS(spsr_abt) 533 DEFINE_SYSREG_RW_FUNCS(spsr_und) 534 DEFINE_SYSREG_RW_FUNCS(spsr_irq) 535 DEFINE_SYSREG_RW_FUNCS(spsr_fiq) 536 DEFINE_SYSREG_RW_FUNCS(dacr32_el2) 537 DEFINE_SYSREG_RW_FUNCS(ifsr32_el2) 538 539 /* GICv3 System Registers */ 540 541 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sre_el1, ICC_SRE_EL1) 542 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sre_el2, ICC_SRE_EL2) 543 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sre_el3, ICC_SRE_EL3) 544 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_pmr_el1, ICC_PMR_EL1) 545 DEFINE_RENAME_SYSREG_READ_FUNC(icc_rpr_el1, ICC_RPR_EL1) 546 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_igrpen1_el3, ICC_IGRPEN1_EL3) 547 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_igrpen1_el1, ICC_IGRPEN1_EL1) 548 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_igrpen0_el1, ICC_IGRPEN0_EL1) 549 DEFINE_RENAME_SYSREG_READ_FUNC(icc_hppir0_el1, ICC_HPPIR0_EL1) 550 DEFINE_RENAME_SYSREG_READ_FUNC(icc_hppir1_el1, ICC_HPPIR1_EL1) 551 DEFINE_RENAME_SYSREG_READ_FUNC(icc_iar0_el1, ICC_IAR0_EL1) 552 DEFINE_RENAME_SYSREG_READ_FUNC(icc_iar1_el1, ICC_IAR1_EL1) 553 DEFINE_RENAME_SYSREG_WRITE_FUNC(icc_eoir0_el1, ICC_EOIR0_EL1) 554 DEFINE_RENAME_SYSREG_WRITE_FUNC(icc_eoir1_el1, ICC_EOIR1_EL1) 555 DEFINE_RENAME_SYSREG_WRITE_FUNC(icc_sgi0r_el1, ICC_SGI0R_EL1) 556 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sgi1r, ICC_SGI1R) 557 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_asgi1r, ICC_ASGI1R) 558 559 DEFINE_RENAME_SYSREG_READ_FUNC(amcfgr_el0, AMCFGR_EL0) 560 DEFINE_RENAME_SYSREG_READ_FUNC(amcgcr_el0, AMCGCR_EL0) 561 DEFINE_RENAME_SYSREG_READ_FUNC(amcg1idr_el0, AMCG1IDR_EL0) 562 DEFINE_RENAME_SYSREG_RW_FUNCS(amcr_el0, AMCR_EL0) 563 DEFINE_RENAME_SYSREG_RW_FUNCS(amcntenclr0_el0, AMCNTENCLR0_EL0) 564 DEFINE_RENAME_SYSREG_RW_FUNCS(amcntenset0_el0, AMCNTENSET0_EL0) 565 DEFINE_RENAME_SYSREG_RW_FUNCS(amcntenclr1_el0, AMCNTENCLR1_EL0) 566 DEFINE_RENAME_SYSREG_RW_FUNCS(amcntenset1_el0, AMCNTENSET1_EL0) 567 568 DEFINE_RENAME_SYSREG_RW_FUNCS(pmblimitr_el1, PMBLIMITR_EL1) 569 570 DEFINE_RENAME_SYSREG_WRITE_FUNC(zcr_el3, ZCR_EL3) 571 DEFINE_RENAME_SYSREG_WRITE_FUNC(zcr_el2, ZCR_EL2) 572 573 DEFINE_RENAME_IDREG_READ_FUNC(id_aa64smfr0_el1, ID_AA64SMFR0_EL1) 574 DEFINE_RENAME_SYSREG_RW_FUNCS(smcr_el3, SMCR_EL3) 575 576 DEFINE_RENAME_SYSREG_READ_FUNC(erridr_el1, ERRIDR_EL1) 577 DEFINE_RENAME_SYSREG_WRITE_FUNC(errselr_el1, ERRSELR_EL1) 578 579 DEFINE_RENAME_SYSREG_READ_FUNC(erxfr_el1, ERXFR_EL1) 580 DEFINE_RENAME_SYSREG_RW_FUNCS(erxctlr_el1, ERXCTLR_EL1) 581 DEFINE_RENAME_SYSREG_RW_FUNCS(erxstatus_el1, ERXSTATUS_EL1) 582 DEFINE_RENAME_SYSREG_READ_FUNC(erxaddr_el1, ERXADDR_EL1) 583 DEFINE_RENAME_SYSREG_READ_FUNC(erxmisc0_el1, ERXMISC0_EL1) 584 DEFINE_RENAME_SYSREG_READ_FUNC(erxmisc1_el1, ERXMISC1_EL1) 585 586 DEFINE_RENAME_SYSREG_RW_FUNCS(scxtnum_el2, SCXTNUM_EL2) 587 DEFINE_RENAME_SYSREG_RW_FUNCS(scxtnum_el1, SCXTNUM_EL1) 588 DEFINE_RENAME_SYSREG_RW_FUNCS(scxtnum_el0, SCXTNUM_EL0) 589 590 /* Armv8.1 VHE Registers */ 591 DEFINE_RENAME_SYSREG_RW_FUNCS(contextidr_el2, CONTEXTIDR_EL2) 592 593 /* Armv8.2 ID Registers */ 594 DEFINE_RENAME_IDREG_READ_FUNC(id_aa64mmfr2_el1, ID_AA64MMFR2_EL1) 595 596 /* Armv8.2 RAS Registers */ 597 DEFINE_RENAME_SYSREG_RW_FUNCS(disr_el1, DISR_EL1) 598 DEFINE_RENAME_SYSREG_RW_FUNCS(vdisr_el2, VDISR_EL2) 599 DEFINE_RENAME_SYSREG_RW_FUNCS(vsesr_el2, VSESR_EL2) 600 601 /* Armv8.2 MPAM Registers */ 602 DEFINE_RENAME_SYSREG_READ_FUNC(mpamidr_el1, MPAMIDR_EL1) 603 DEFINE_RENAME_SYSREG_RW_FUNCS(mpam3_el3, MPAM3_EL3) 604 DEFINE_RENAME_SYSREG_RW_FUNCS(mpam2_el2, MPAM2_EL2) 605 DEFINE_RENAME_SYSREG_RW_FUNCS(mpamhcr_el2, MPAMHCR_EL2) 606 DEFINE_RENAME_SYSREG_RW_FUNCS(mpamvpm0_el2, MPAMVPM0_EL2) 607 DEFINE_RENAME_SYSREG_RW_FUNCS(mpamvpm1_el2, MPAMVPM1_EL2) 608 DEFINE_RENAME_SYSREG_RW_FUNCS(mpamvpm2_el2, MPAMVPM2_EL2) 609 DEFINE_RENAME_SYSREG_RW_FUNCS(mpamvpm3_el2, MPAMVPM3_EL2) 610 DEFINE_RENAME_SYSREG_RW_FUNCS(mpamvpm4_el2, MPAMVPM4_EL2) 611 DEFINE_RENAME_SYSREG_RW_FUNCS(mpamvpm5_el2, MPAMVPM5_EL2) 612 DEFINE_RENAME_SYSREG_RW_FUNCS(mpamvpm6_el2, MPAMVPM6_EL2) 613 DEFINE_RENAME_SYSREG_RW_FUNCS(mpamvpm7_el2, MPAMVPM7_EL2) 614 DEFINE_RENAME_SYSREG_RW_FUNCS(mpamvpmv_el2, MPAMVPMV_EL2) 615 616 /* Armv8.3 Pointer Authentication Registers */ 617 DEFINE_RENAME_SYSREG_RW_FUNCS(apiakeyhi_el1, APIAKeyHi_EL1) 618 DEFINE_RENAME_SYSREG_RW_FUNCS(apiakeylo_el1, APIAKeyLo_EL1) 619 620 /* Armv8.4 Data Independent Timing Register */ 621 DEFINE_RENAME_SYSREG_RW_FUNCS(dit, DIT) 622 623 /* Armv8.4 FEAT_TRF Register */ 624 DEFINE_RENAME_SYSREG_RW_FUNCS(trfcr_el2, TRFCR_EL2) 625 DEFINE_RENAME_SYSREG_RW_FUNCS(trfcr_el1, TRFCR_EL1) 626 DEFINE_RENAME_SYSREG_RW_FUNCS(vncr_el2, VNCR_EL2) 627 628 /* Armv8.5 MTE Registers */ 629 DEFINE_RENAME_SYSREG_RW_FUNCS(tfsre0_el1, TFSRE0_EL1) 630 DEFINE_RENAME_SYSREG_RW_FUNCS(tfsr_el1, TFSR_EL1) 631 DEFINE_RENAME_SYSREG_RW_FUNCS(rgsr_el1, RGSR_EL1) 632 DEFINE_RENAME_SYSREG_RW_FUNCS(gcr_el1, GCR_EL1) 633 DEFINE_RENAME_SYSREG_RW_FUNCS(tfsr_el2, TFSR_EL2) 634 635 /* Armv8.5 FEAT_RNG Registers */ 636 DEFINE_RENAME_SYSREG_READ_FUNC(rndr, RNDR) 637 DEFINE_RENAME_SYSREG_READ_FUNC(rndrrs, RNDRRS) 638 639 /* Armv8.6 FEAT_FGT Registers */ 640 DEFINE_RENAME_SYSREG_RW_FUNCS(hdfgrtr_el2, HDFGRTR_EL2) 641 DEFINE_RENAME_SYSREG_RW_FUNCS(hafgrtr_el2, HAFGRTR_EL2) 642 DEFINE_RENAME_SYSREG_RW_FUNCS(hdfgwtr_el2, HDFGWTR_EL2) 643 DEFINE_RENAME_SYSREG_RW_FUNCS(hfgitr_el2, HFGITR_EL2) 644 DEFINE_RENAME_SYSREG_RW_FUNCS(hfgrtr_el2, HFGRTR_EL2) 645 DEFINE_RENAME_SYSREG_RW_FUNCS(hfgwtr_el2, HFGWTR_EL2) 646 647 /* ARMv8.6 FEAT_ECV Register */ 648 DEFINE_RENAME_SYSREG_RW_FUNCS(cntpoff_el2, CNTPOFF_EL2) 649 650 /* FEAT_HCX Register */ 651 DEFINE_RENAME_SYSREG_RW_FUNCS(hcrx_el2, HCRX_EL2) 652 653 /* Armv8.9 system registers */ 654 DEFINE_RENAME_IDREG_READ_FUNC(id_aa64mmfr3_el1, ID_AA64MMFR3_EL1) 655 656 /* Armv8.9 FEAT_FGT2 Registers */ 657 DEFINE_RENAME_SYSREG_RW_FUNCS(hdfgrtr2_el2, HDFGRTR2_EL2) 658 DEFINE_RENAME_SYSREG_RW_FUNCS(hdfgwtr2_el2, HDFGWTR2_EL2) 659 DEFINE_RENAME_SYSREG_RW_FUNCS(hfgitr2_el2, HFGITR2_EL2) 660 DEFINE_RENAME_SYSREG_RW_FUNCS(hfgrtr2_el2, HFGRTR2_EL2) 661 DEFINE_RENAME_SYSREG_RW_FUNCS(hfgwtr2_el2, HFGWTR2_EL2) 662 663 /* FEAT_TCR2 Register */ 664 DEFINE_RENAME_SYSREG_RW_FUNCS(tcr2_el1, TCR2_EL1) 665 DEFINE_RENAME_SYSREG_RW_FUNCS(tcr2_el2, TCR2_EL2) 666 667 /* FEAT_SxPIE Registers */ 668 DEFINE_RENAME_SYSREG_RW_FUNCS(pire0_el1, PIRE0_EL1) 669 DEFINE_RENAME_SYSREG_RW_FUNCS(pire0_el2, PIRE0_EL2) 670 DEFINE_RENAME_SYSREG_RW_FUNCS(pir_el1, PIR_EL1) 671 DEFINE_RENAME_SYSREG_RW_FUNCS(pir_el2, PIR_EL2) 672 DEFINE_RENAME_SYSREG_RW_FUNCS(s2pir_el2, S2PIR_EL2) 673 674 /* FEAT_SxPOE Registers */ 675 DEFINE_RENAME_SYSREG_RW_FUNCS(por_el1, POR_EL1) 676 DEFINE_RENAME_SYSREG_RW_FUNCS(por_el2, POR_EL2) 677 DEFINE_RENAME_SYSREG_RW_FUNCS(s2por_el1, S2POR_EL1) 678 679 /* FEAT_GCS Registers */ 680 DEFINE_RENAME_SYSREG_RW_FUNCS(gcscr_el2, GCSCR_EL2) 681 DEFINE_RENAME_SYSREG_RW_FUNCS(gcspr_el2, GCSPR_EL2) 682 DEFINE_RENAME_SYSREG_RW_FUNCS(gcscr_el1, GCSCR_EL1) 683 DEFINE_RENAME_SYSREG_RW_FUNCS(gcscre0_el1, GCSCRE0_EL1) 684 DEFINE_RENAME_SYSREG_RW_FUNCS(gcspr_el1, GCSPR_EL1) 685 DEFINE_RENAME_SYSREG_RW_FUNCS(gcspr_el0, GCSPR_EL0) 686 687 /* FEAT_THE Registers */ 688 #if ENABLE_FEAT_D128 689 DECLARE_SYSREG128_RW_FUNCS(rcwmask_el1) 690 DECLARE_SYSREG128_RW_FUNCS(rcwsmask_el1) 691 #else 692 DEFINE_RENAME_SYSREG_RW_FUNCS(rcwmask_el1, RCWMASK_EL1) 693 DEFINE_RENAME_SYSREG_RW_FUNCS(rcwsmask_el1, RCWSMASK_EL1) 694 #endif 695 696 /* FEAT_SCTLR2 Registers */ 697 DEFINE_RENAME_SYSREG_RW_FUNCS(sctlr2_el1, SCTLR2_EL1) 698 DEFINE_RENAME_SYSREG_RW_FUNCS(sctlr2_el2, SCTLR2_EL2) 699 700 /* FEAT_LS64_ACCDATA Registers */ 701 DEFINE_RENAME_SYSREG_RW_FUNCS(accdata_el1, ACCDATA_EL1) 702 703 /* DynamIQ Control registers */ 704 DEFINE_RENAME_SYSREG_RW_FUNCS(clusterpwrdn_el1, CLUSTERPWRDN_EL1) 705 DEFINE_RENAME_SYSREG_RW_FUNCS(clusterpmcr_el1, CLUSTERPMCR_EL1) 706 DEFINE_RENAME_SYSREG_RW_FUNCS(clusterpmcntenset_el1, CLUSTERPMCNTENSET_EL1) 707 DEFINE_RENAME_SYSREG_RW_FUNCS(clusterpmccntr_el1, CLUSTERPMCCNTR_EL1) 708 DEFINE_RENAME_SYSREG_RW_FUNCS(clusterpmovsset_el1, CLUSTERPMOVSSET_EL1) 709 DEFINE_RENAME_SYSREG_RW_FUNCS(clusterpmovsclr_el1, CLUSTERPMOVSCLR_EL1) 710 DEFINE_RENAME_SYSREG_RW_FUNCS(clusterpmselr_el1, CLUSTERPMSELR_EL1) 711 DEFINE_RENAME_SYSREG_RW_FUNCS(clusterpmxevcntr_el1, CLUSTERPMXEVCNTR_EL1) 712 DEFINE_RENAME_SYSREG_RW_FUNCS(clusterpmxevtyper_el1, CLUSTERPMXEVTYPER_EL1) 713 714 /* CPU Power/Performance Management registers */ 715 DEFINE_RENAME_SYSREG_RW_FUNCS(cpuppmcr_el3, CPUPPMCR_EL3) 716 DEFINE_RENAME_SYSREG_RW_FUNCS(cpumpmmcr_el3, CPUMPMMCR_EL3) 717 718 /* Armv9.2 RME Registers */ 719 DEFINE_RENAME_SYSREG_RW_FUNCS(gptbr_el3, GPTBR_EL3) 720 DEFINE_RENAME_SYSREG_RW_FUNCS(gpccr_el3, GPCCR_EL3) 721 722 DEFINE_RENAME_SYSREG_RW_FUNCS(fpmr, FPMR) 723 724 #define IS_IN_EL(x) \ 725 (GET_EL(read_CurrentEl()) == MODE_EL##x) 726 727 #define IS_IN_EL1() IS_IN_EL(1) 728 #define IS_IN_EL2() IS_IN_EL(2) 729 #define IS_IN_EL3() IS_IN_EL(3) 730 731 static inline unsigned int get_current_el(void) 732 { 733 return GET_EL(read_CurrentEl()); 734 } 735 736 static inline unsigned int get_current_el_maybe_constant(void) 737 { 738 #if defined(IMAGE_AT_EL1) 739 return 1; 740 #elif defined(IMAGE_AT_EL2) 741 return 2; /* no use-case in TF-A */ 742 #elif defined(IMAGE_AT_EL3) 743 return 3; 744 #else 745 /* 746 * If we do not know which exception level this is being built for 747 * (e.g. built for library), fall back to run-time detection. 748 */ 749 return get_current_el(); 750 #endif 751 } 752 753 /* 754 * Check if an EL is implemented from AA64PFR0 register fields. 755 */ 756 static inline uint64_t el_implemented(unsigned int el) 757 { 758 if (el > 3U) { 759 return EL_IMPL_NONE; 760 } else { 761 unsigned int shift = ID_AA64PFR0_EL1_SHIFT * el; 762 763 return (read_id_aa64pfr0_el1() >> shift) & ID_AA64PFR0_ELX_MASK; 764 } 765 } 766 767 /* 768 * TLBI PAALLOS instruction 769 * (TLB Invalidate GPT Information by PA, All Entries, Outer Shareable) 770 */ 771 static inline void tlbipaallos(void) 772 { 773 __asm__("sys #6, c8, c1, #4"); 774 } 775 776 /* 777 * TLBI RPALOS instructions 778 * (TLB Range Invalidate GPT Information by PA, Last level, Outer Shareable) 779 * 780 * command SIZE, bits [47:44] field: 781 * 0b0000 4KB 782 * 0b0001 16KB 783 * 0b0010 64KB 784 * 0b0011 2MB 785 * 0b0100 32MB 786 * 0b0101 512MB 787 * 0b0110 1GB 788 * 0b0111 16GB 789 * 0b1000 64GB 790 * 0b1001 512GB 791 */ 792 #define TLBI_SZ_4K 0UL 793 #define TLBI_SZ_16K 1UL 794 #define TLBI_SZ_64K 2UL 795 #define TLBI_SZ_2M 3UL 796 #define TLBI_SZ_32M 4UL 797 #define TLBI_SZ_512M 5UL 798 #define TLBI_SZ_1G 6UL 799 #define TLBI_SZ_16G 7UL 800 #define TLBI_SZ_64G 8UL 801 #define TLBI_SZ_512G 9UL 802 803 #define TLBI_ADDR_SHIFT U(12) 804 #define TLBI_SIZE_SHIFT U(44) 805 806 #define TLBIRPALOS(_addr, _size) \ 807 { \ 808 u_register_t arg = ((_addr) >> TLBI_ADDR_SHIFT) | \ 809 ((_size) << TLBI_SIZE_SHIFT); \ 810 __asm__("sys #6, c8, c4, #7, %0" : : "r" (arg)); \ 811 } 812 813 /* Note: addr must be aligned to 4KB */ 814 static inline void tlbirpalos_4k(uintptr_t addr) 815 { 816 TLBIRPALOS(addr, TLBI_SZ_4K); 817 } 818 819 /* Note: addr must be aligned to 16KB */ 820 static inline void tlbirpalos_16k(uintptr_t addr) 821 { 822 TLBIRPALOS(addr, TLBI_SZ_16K); 823 } 824 825 /* Note: addr must be aligned to 64KB */ 826 static inline void tlbirpalos_64k(uintptr_t addr) 827 { 828 TLBIRPALOS(addr, TLBI_SZ_64K); 829 } 830 831 /* Note: addr must be aligned to 2MB */ 832 static inline void tlbirpalos_2m(uintptr_t addr) 833 { 834 TLBIRPALOS(addr, TLBI_SZ_2M); 835 } 836 837 /* Note: addr must be aligned to 32MB */ 838 static inline void tlbirpalos_32m(uintptr_t addr) 839 { 840 TLBIRPALOS(addr, TLBI_SZ_32M); 841 } 842 843 /* Note: addr must be aligned to 512MB */ 844 static inline void tlbirpalos_512m(uintptr_t addr) 845 { 846 TLBIRPALOS(addr, TLBI_SZ_512M); 847 } 848 849 /* Previously defined accessor functions with incomplete register names */ 850 851 #define read_current_el() read_CurrentEl() 852 853 #define dsb() dsbsy() 854 855 #define read_midr() read_midr_el1() 856 857 #define read_mpidr() read_mpidr_el1() 858 859 #define read_scr() read_scr_el3() 860 #define write_scr(_v) write_scr_el3(_v) 861 862 #define read_hcr() read_hcr_el2() 863 #define write_hcr(_v) write_hcr_el2(_v) 864 865 #define read_cpacr() read_cpacr_el1() 866 #define write_cpacr(_v) write_cpacr_el1(_v) 867 868 #define read_clusterpwrdn() read_clusterpwrdn_el1() 869 #define write_clusterpwrdn(_v) write_clusterpwrdn_el1(_v) 870 871 #define read_clusterpmcr() read_clusterpmcr_el1() 872 #define write_clusterpmcr(_v) write_clusterpmcr_el1(_v) 873 874 #define read_clusterpmcntenset() read_clusterpmcntenset_el1() 875 #define write_clusterpmcntenset(_v) write_clusterpmcntenset_el1(_v) 876 877 #define read_clusterpmccntr() read_clusterpmccntr_el1() 878 #define write_clusterpmccntr(_v) write_clusterpmccntr_el1(_v) 879 880 #define read_clusterpmovsset() read_clusterpmovsset_el1() 881 #define write_clusterpmovsset(_v) write_clusterpmovsset_el1(_v) 882 883 #define read_clusterpmovsclr() read_clusterpmovsclr_el1() 884 #define write_clusterpmovsclr(_v) write_clusterpmovsclr_el1(_v) 885 886 #define read_clusterpmselr() read_clusterpmselr_el1() 887 #define write_clusterpmselr(_v) write_clusterpmselr_el1(_v) 888 889 #define read_clusterpmxevcntr() read_clusterpmxevcntr_el1() 890 #define write_clusterpmxevcntr(_v) write_clusterpmxevcntr_el1(_v) 891 892 #define read_clusterpmxevtyper() read_clusterpmxevtyper_el1() 893 #define write_clusterpmxevtyper(_v) write_clusterpmxevtyper_el1(_v) 894 895 #if ERRATA_SPECULATIVE_AT 896 /* 897 * Assuming SCTLR.M bit is already enabled 898 * 1. Enable page table walk by clearing TCR_EL1.EPDx bits 899 * 2. Execute AT instruction for lower EL1/0 900 * 3. Disable page table walk by setting TCR_EL1.EPDx bits 901 */ 902 #define AT(_at_inst, _va) \ 903 { \ 904 assert((read_sctlr_el1() & SCTLR_M_BIT) != 0ULL); \ 905 write_tcr_el1(read_tcr_el1() & ~(TCR_EPD0_BIT | TCR_EPD1_BIT)); \ 906 isb(); \ 907 _at_inst(_va); \ 908 write_tcr_el1(read_tcr_el1() | (TCR_EPD0_BIT | TCR_EPD1_BIT)); \ 909 isb(); \ 910 } 911 #else 912 #define AT(_at_inst, _va) _at_inst(_va) 913 #endif 914 915 #endif /* ARCH_HELPERS_H */ 916