1/* 2 * Copyright (c) 2021-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_x3.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13#include "wa_cve_2022_23960_bhb_vector.S" 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "Cortex-X3 must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20/* 64-bit only core */ 21#if CTX_INCLUDE_AARCH32_REGS == 1 22#error "Cortex-X3 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 23#endif 24 25.global check_erratum_cortex_x3_3701769 26 27add_erratum_entry cortex_x3, ERRATUM(3701769), ERRATA_X3_3701769 28 29check_erratum_ls cortex_x3, ERRATUM(3701769), CPU_REV(1, 2) 30 31#if WORKAROUND_CVE_2022_23960 32 wa_cve_2022_23960_bhb_vector_table CORTEX_X3_BHB_LOOP_COUNT, cortex_x3 33#endif /* WORKAROUND_CVE_2022_23960 */ 34 35cpu_reset_prologue cortex_x3 36 37/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */ 38workaround_reset_start cortex_x3, CVE(2024, 5660), WORKAROUND_CVE_2024_5660 39 sysreg_bit_set CORTEX_X3_CPUECTLR_EL1, BIT(46) 40workaround_reset_end cortex_x3, CVE(2024, 5660) 41 42check_erratum_ls cortex_x3, CVE(2024, 5660), CPU_REV(1, 2) 43 44workaround_reset_start cortex_x3, ERRATUM(2070301), ERRATA_X3_2070301 45 sysreg_bitfield_insert CORTEX_X3_CPUECTLR2_EL1, CORTEX_X3_CPUECTLR2_EL1_PF_MODE_CNSRV, \ 46 CORTEX_X3_CPUECTLR2_EL1_PF_MODE_LSB, CORTEX_X3_CPUECTLR2_EL1_PF_MODE_WIDTH 47workaround_reset_end cortex_x3, ERRATUM(2070301) 48 49check_erratum_ls cortex_x3, ERRATUM(2070301), CPU_REV(1, 2) 50 51workaround_reset_start cortex_x3, ERRATUM(2266875), ERRATA_X3_2266875 52 sysreg_bit_set CORTEX_X3_CPUACTLR_EL1, BIT(22) 53workaround_reset_end cortex_x3, ERRATUM(2266875) 54 55check_erratum_ls cortex_x3, ERRATUM(2266875), CPU_REV(1, 0) 56 57workaround_reset_start cortex_x3, ERRATUM(2302506), ERRATA_X3_2302506 58 sysreg_bit_set CORTEX_X3_CPUACTLR2_EL1, BIT(0) 59workaround_reset_end cortex_x3, ERRATUM(2302506) 60 61check_erratum_ls cortex_x3, ERRATUM(2302506), CPU_REV(1, 1) 62 63.global erratum_cortex_x3_2313909_wa 64workaround_runtime_start cortex_x3, ERRATUM(2313909), ERRATA_X3_2313909 65 /* Set/unset bit 36 in ACTLR2_EL1. The first call will set it, applying 66 * the workaround. Second call clears it to undo it. */ 67 sysreg_bit_toggle CORTEX_X3_CPUACTLR2_EL1, CORTEX_X3_CPUACTLR2_EL1_BIT_36 68workaround_runtime_end cortex_x3, ERRATUM(2313909), NO_ISB 69 70check_erratum_ls cortex_x3, ERRATUM(2313909), CPU_REV(1, 0) 71 72workaround_reset_start cortex_x3, ERRATUM(2372204), ERRATA_X3_2372204 73 /* Set bit 40 in CPUACTLR2_EL1 */ 74 sysreg_bit_set CORTEX_X3_CPUACTLR2_EL1, BIT(40) 75workaround_reset_end cortex_x3, ERRATUM(2372204) 76 77check_erratum_ls cortex_x3, ERRATUM(2372204), CPU_REV(1, 0) 78 79workaround_reset_start cortex_x3, ERRATUM(2615812), ERRATA_X3_2615812 80 /* Disable retention control for WFI and WFE. */ 81 mrs x0, CORTEX_X3_CPUPWRCTLR_EL1 82 bfi x0, xzr, #CORTEX_X3_CPUPWRCTLR_EL1_WFI_RET_CTRL_BITS_SHIFT, #3 83 bfi x0, xzr, #CORTEX_X3_CPUPWRCTLR_EL1_WFE_RET_CTRL_BITS_SHIFT, #3 84 msr CORTEX_X3_CPUPWRCTLR_EL1, x0 85workaround_reset_end cortex_x3, ERRATUM(2615812) 86 87check_erratum_ls cortex_x3, ERRATUM(2615812), CPU_REV(1, 1) 88 89workaround_reset_start cortex_x3, ERRATUM(2641945), ERRATA_X3_2641945 90 sysreg_bit_set CORTEX_X3_CPUACTLR6_EL1, BIT(41) 91workaround_reset_end cortex_x3, ERRATUM(2641945) 92 93check_erratum_ls cortex_x3, ERRATUM(2641945), CPU_REV(1, 0) 94 95workaround_reset_start cortex_x3, ERRATUM(2742421), ERRATA_X3_2742421 96 /* Set CPUACTLR5_EL1[56:55] to 2'b01 */ 97 sysreg_bit_set CORTEX_X3_CPUACTLR5_EL1, CORTEX_X3_CPUACTLR5_EL1_BIT_55 98 sysreg_bit_clear CORTEX_X3_CPUACTLR5_EL1, CORTEX_X3_CPUACTLR5_EL1_BIT_56 99workaround_reset_end cortex_x3, ERRATUM(2742421) 100 101check_erratum_ls cortex_x3, ERRATUM(2742421), CPU_REV(1, 1) 102 103workaround_runtime_start cortex_x3, ERRATUM(2743088), ERRATA_X3_2743088 104 /* dsb before isb of power down sequence */ 105 dsb sy 106workaround_runtime_end cortex_x3, ERRATUM(2743088), NO_ISB 107 108check_erratum_ls cortex_x3, ERRATUM(2743088), CPU_REV(1, 1) 109 110workaround_reset_start cortex_x3, ERRATUM(2779509), ERRATA_X3_2779509 111 /* Set CPUACTLR3_EL1 bit 47 */ 112 sysreg_bit_set CORTEX_X3_CPUACTLR3_EL1, CORTEX_X3_CPUACTLR3_EL1_BIT_47 113workaround_reset_end cortex_x3, ERRATUM(2779509) 114 115check_erratum_ls cortex_x3, ERRATUM(2779509), CPU_REV(1, 1) 116 117workaround_reset_start cortex_x3, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 118#if IMAGE_BL31 119 override_vector_table wa_cve_vbar_cortex_x3 120#endif /* IMAGE_BL31 */ 121workaround_reset_end cortex_x3, CVE(2022, 23960) 122 123check_erratum_chosen cortex_x3, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 124 125workaround_reset_start cortex_x3, CVE(2024, 7881), WORKAROUND_CVE_2024_7881 126 /* --------------------------------- 127 * Sets BIT41 of CPUACTLR6_EL1 which 128 * disables L1 Data cache prefetcher 129 * --------------------------------- 130 */ 131 sysreg_bit_set CORTEX_X3_CPUACTLR6_EL1, BIT(41) 132workaround_reset_end cortex_x3, CVE(2024, 7881) 133 134check_erratum_chosen cortex_x3, CVE(2024, 7881), WORKAROUND_CVE_2024_7881 135 136cpu_reset_func_start cortex_x3 137 /* Disable speculative loads */ 138 msr SSBS, xzr 139 enable_mpmm 140cpu_reset_func_end cortex_x3 141 142 /* ---------------------------------------------------- 143 * HW will do the cache maintenance while powering down 144 * ---------------------------------------------------- 145 */ 146func cortex_x3_core_pwr_dwn 147 apply_erratum cortex_x3, ERRATUM(2313909), ERRATA_X3_2313909, NO_GET_CPU_REV 148 /* --------------------------------------------------- 149 * Enable CPU power down bit in power control register 150 * --------------------------------------------------- 151 */ 152 sysreg_bit_set CORTEX_X3_CPUPWRCTLR_EL1, CORTEX_X3_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 153 apply_erratum cortex_x3, ERRATUM(2743088), ERRATA_X3_2743088, NO_GET_CPU_REV 154 isb 155 ret 156endfunc cortex_x3_core_pwr_dwn 157 158 /* --------------------------------------------- 159 * This function provides Cortex-X3- 160 * specific register information for crash 161 * reporting. It needs to return with x6 162 * pointing to a list of register names in ascii 163 * and x8 - x15 having values of registers to be 164 * reported. 165 * --------------------------------------------- 166 */ 167.section .rodata.cortex_x3_regs, "aS" 168cortex_x3_regs: /* The ascii list of register names to be reported */ 169 .asciz "cpuectlr_el1", "" 170 171func cortex_x3_cpu_reg_dump 172 adr x6, cortex_x3_regs 173 mrs x8, CORTEX_X3_CPUECTLR_EL1 174 ret 175endfunc cortex_x3_cpu_reg_dump 176 177declare_cpu_ops_wa_4 cortex_x3, CORTEX_X3_MIDR, \ 178 cortex_x3_reset_func, \ 179 CPU_NO_EXTRA1_FUNC, \ 180 CPU_NO_EXTRA2_FUNC, \ 181 CPU_NO_EXTRA3_FUNC, \ 182 check_erratum_cortex_x3_7881, \ 183 cortex_x3_core_pwr_dwn 184