1 /* 2 * Copyright (c) 2020-2025, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 #include <inttypes.h> 10 #include <stdint.h> 11 #include <string.h> 12 13 #include <arch_helpers.h> 14 #include <arch/aarch64/arch_features.h> 15 #include <bl31/bl31.h> 16 #include <bl31/interrupt_mgmt.h> 17 #include <common/debug.h> 18 #include <common/runtime_svc.h> 19 #include <common/tbbr/tbbr_img_def.h> 20 #include <lib/el3_runtime/context_mgmt.h> 21 #include <lib/fconf/fconf.h> 22 #include <lib/fconf/fconf_dyn_cfg_getter.h> 23 #include <lib/smccc.h> 24 #include <lib/spinlock.h> 25 #include <lib/utils.h> 26 #include <lib/xlat_tables/xlat_tables_v2.h> 27 #include <plat/common/common_def.h> 28 #include <plat/common/platform.h> 29 #include <platform_def.h> 30 #include <services/el3_spmd_logical_sp.h> 31 #include <services/ffa_svc.h> 32 #include <services/spmc_svc.h> 33 #include <services/spmd_svc.h> 34 #include <smccc_helpers.h> 35 #include "spmd_private.h" 36 37 /******************************************************************************* 38 * SPM Core context information. 39 ******************************************************************************/ 40 static spmd_spm_core_context_t spm_core_context[PLATFORM_CORE_COUNT]; 41 42 /******************************************************************************* 43 * SPM Core attribute information is read from its manifest if the SPMC is not 44 * at EL3. Else, it is populated from the SPMC directly. 45 ******************************************************************************/ 46 static spmc_manifest_attribute_t spmc_attrs; 47 48 /******************************************************************************* 49 * SPM Core entry point information. Discovered on the primary core and reused 50 * on secondary cores. 51 ******************************************************************************/ 52 static entry_point_info_t *spmc_ep_info; 53 54 /******************************************************************************* 55 * SPM Core context on current CPU get helper. 56 ******************************************************************************/ 57 spmd_spm_core_context_t *spmd_get_context(void) 58 { 59 return &spm_core_context[plat_my_core_pos()]; 60 } 61 62 /******************************************************************************* 63 * SPM Core ID getter. 64 ******************************************************************************/ 65 uint16_t spmd_spmc_id_get(void) 66 { 67 return spmc_attrs.spmc_id; 68 } 69 70 /******************************************************************************* 71 * Static function declaration. 72 ******************************************************************************/ 73 static int32_t spmd_init(void); 74 static int spmd_spmc_init(void *pm_addr); 75 76 static uint64_t spmd_smc_forward(uint32_t smc_fid, 77 bool secure_origin, 78 uint64_t x1, 79 uint64_t x2, 80 uint64_t x3, 81 uint64_t x4, 82 void *cookie, 83 void *handle, 84 uint64_t flags); 85 86 /****************************************************************************** 87 * Builds an SPMD to SPMC direct message request. 88 *****************************************************************************/ 89 void spmd_build_spmc_message(gp_regs_t *gpregs, uint8_t target_func, 90 unsigned long long message) 91 { 92 write_ctx_reg(gpregs, CTX_GPREG_X0, FFA_MSG_SEND_DIRECT_REQ_SMC32); 93 write_ctx_reg(gpregs, CTX_GPREG_X1, 94 (SPMD_DIRECT_MSG_ENDPOINT_ID << FFA_DIRECT_MSG_SOURCE_SHIFT) | 95 spmd_spmc_id_get()); 96 write_ctx_reg(gpregs, CTX_GPREG_X2, BIT(31) | target_func); 97 write_ctx_reg(gpregs, CTX_GPREG_X3, message); 98 99 /* Zero out x4-x7 for the direct request emitted towards the SPMC. */ 100 write_ctx_reg(gpregs, CTX_GPREG_X4, 0); 101 write_ctx_reg(gpregs, CTX_GPREG_X5, 0); 102 write_ctx_reg(gpregs, CTX_GPREG_X6, 0); 103 write_ctx_reg(gpregs, CTX_GPREG_X7, 0); 104 } 105 106 107 /******************************************************************************* 108 * This function takes an SPMC context pointer and performs a synchronous 109 * SPMC entry. 110 ******************************************************************************/ 111 uint64_t spmd_spm_core_sync_entry(spmd_spm_core_context_t *spmc_ctx) 112 { 113 uint64_t rc; 114 115 assert(spmc_ctx != NULL); 116 117 cm_set_context(&(spmc_ctx->cpu_ctx), SECURE); 118 119 /* Restore the context assigned above */ 120 #if SPMD_SPM_AT_SEL2 121 cm_el2_sysregs_context_restore(SECURE); 122 #else 123 cm_el1_sysregs_context_restore(SECURE); 124 #endif 125 cm_set_next_eret_context(SECURE); 126 127 /* Enter SPMC */ 128 rc = spmd_spm_core_enter(&spmc_ctx->c_rt_ctx); 129 130 /* Save secure state */ 131 #if SPMD_SPM_AT_SEL2 132 cm_el2_sysregs_context_save(SECURE); 133 #else 134 cm_el1_sysregs_context_save(SECURE); 135 #endif 136 137 return rc; 138 } 139 140 /******************************************************************************* 141 * This function returns to the place where spmd_spm_core_sync_entry() was 142 * called originally. 143 ******************************************************************************/ 144 __dead2 void spmd_spm_core_sync_exit(uint64_t rc) 145 { 146 spmd_spm_core_context_t *ctx = spmd_get_context(); 147 148 /* Get current CPU context from SPMC context */ 149 assert(cm_get_context(SECURE) == &(ctx->cpu_ctx)); 150 151 /* 152 * The SPMD must have initiated the original request through a 153 * synchronous entry into SPMC. Jump back to the original C runtime 154 * context with the value of rc in x0; 155 */ 156 spmd_spm_core_exit(ctx->c_rt_ctx, rc); 157 158 panic(); 159 } 160 161 /******************************************************************************* 162 * Jump to the SPM Core for the first time. 163 ******************************************************************************/ 164 static int32_t spmd_init(void) 165 { 166 spmd_spm_core_context_t *ctx = spmd_get_context(); 167 uint64_t rc; 168 169 VERBOSE("SPM Core init start.\n"); 170 171 /* Primary boot core enters the SPMC for initialization. */ 172 ctx->state = SPMC_STATE_ON_PENDING; 173 174 rc = spmd_spm_core_sync_entry(ctx); 175 if (rc != 0ULL) { 176 ERROR("SPMC initialisation failed 0x%" PRIx64 "\n", rc); 177 return 0; 178 } 179 180 ctx->state = SPMC_STATE_ON; 181 182 VERBOSE("SPM Core init end.\n"); 183 184 spmd_logical_sp_set_spmc_initialized(); 185 rc = spmd_logical_sp_init(); 186 if (rc != 0) { 187 WARN("SPMD Logical partitions failed init.\n"); 188 } 189 190 return 1; 191 } 192 193 /******************************************************************************* 194 * spmd_secure_interrupt_handler 195 * Enter the SPMC for further handling of the secure interrupt by the SPMC 196 * itself or a Secure Partition. 197 ******************************************************************************/ 198 static uint64_t spmd_secure_interrupt_handler(uint32_t id, 199 uint32_t flags, 200 void *handle, 201 void *cookie) 202 { 203 spmd_spm_core_context_t *ctx = spmd_get_context(); 204 gp_regs_t *gpregs = get_gpregs_ctx(&ctx->cpu_ctx); 205 int64_t rc; 206 207 /* Sanity check the security state when the exception was generated */ 208 assert(get_interrupt_src_ss(flags) == NON_SECURE); 209 210 /* Sanity check the pointer to this cpu's context */ 211 assert(handle == cm_get_context(NON_SECURE)); 212 213 /* Save the non-secure context before entering SPMC */ 214 #if SPMD_SPM_AT_SEL2 215 cm_el2_sysregs_context_save(NON_SECURE); 216 #else 217 cm_el1_sysregs_context_save(NON_SECURE); 218 219 #if CTX_INCLUDE_FPREGS || CTX_INCLUDE_SVE_REGS 220 /* 221 * The hint bit denoting absence of SVE live state is effectively false 222 * in this scenario where execution was trapped to EL3 due to FIQ. 223 */ 224 simd_ctx_save(NON_SECURE, false); 225 simd_ctx_restore(SECURE); 226 #endif 227 #endif 228 229 /* Convey the event to the SPMC through the FFA_INTERRUPT interface. */ 230 write_ctx_reg(gpregs, CTX_GPREG_X0, FFA_INTERRUPT); 231 write_ctx_reg(gpregs, CTX_GPREG_X1, 0); 232 write_ctx_reg(gpregs, CTX_GPREG_X2, 0); 233 write_ctx_reg(gpregs, CTX_GPREG_X3, 0); 234 write_ctx_reg(gpregs, CTX_GPREG_X4, 0); 235 write_ctx_reg(gpregs, CTX_GPREG_X5, 0); 236 write_ctx_reg(gpregs, CTX_GPREG_X6, 0); 237 write_ctx_reg(gpregs, CTX_GPREG_X7, 0); 238 239 /* Mark current core as handling a secure interrupt. */ 240 ctx->secure_interrupt_ongoing = true; 241 242 rc = spmd_spm_core_sync_entry(ctx); 243 244 if (rc != 0ULL) { 245 ERROR("%s failed (%" PRId64 ") on CPU%u\n", __func__, rc, plat_my_core_pos()); 246 } 247 248 ctx->secure_interrupt_ongoing = false; 249 250 #if SPMD_SPM_AT_SEL2 251 cm_el2_sysregs_context_restore(NON_SECURE); 252 #else 253 cm_el1_sysregs_context_restore(NON_SECURE); 254 255 #if CTX_INCLUDE_FPREGS || CTX_INCLUDE_SVE_REGS 256 simd_ctx_save(SECURE, false); 257 simd_ctx_restore(NON_SECURE); 258 #endif 259 #endif 260 cm_set_next_eret_context(NON_SECURE); 261 262 SMC_RET0(&ctx->cpu_ctx); 263 } 264 265 #if (EL3_EXCEPTION_HANDLING == 0) 266 /******************************************************************************* 267 * spmd_group0_interrupt_handler_nwd 268 * Group0 secure interrupt in the normal world are trapped to EL3. Delegate the 269 * handling of the interrupt to the platform handler, and return only upon 270 * successfully handling the Group0 interrupt. 271 ******************************************************************************/ 272 static uint64_t spmd_group0_interrupt_handler_nwd(uint32_t id, 273 uint32_t flags, 274 void *handle, 275 void *cookie) 276 { 277 uint32_t intid; 278 279 /* Sanity check the security state when the exception was generated. */ 280 assert(get_interrupt_src_ss(flags) == NON_SECURE); 281 282 /* Sanity check the pointer to this cpu's context. */ 283 assert(handle == cm_get_context(NON_SECURE)); 284 285 assert(id == INTR_ID_UNAVAILABLE); 286 287 assert(plat_ic_get_pending_interrupt_type() == INTR_TYPE_EL3); 288 289 intid = plat_ic_acknowledge_interrupt(); 290 291 if (plat_spmd_handle_group0_interrupt(intid) < 0) { 292 ERROR("Group0 interrupt %u not handled\n", intid); 293 panic(); 294 } 295 296 /* Deactivate the corresponding Group0 interrupt. */ 297 plat_ic_end_of_interrupt(intid); 298 299 return 0U; 300 } 301 #endif 302 303 /******************************************************************************* 304 * spmd_handle_group0_intr_swd 305 * SPMC delegates handling of Group0 secure interrupt to EL3 firmware using 306 * FFA_EL3_INTR_HANDLE SMC call. Further, SPMD delegates the handling of the 307 * interrupt to the platform handler, and returns only upon successfully 308 * handling the Group0 interrupt. 309 ******************************************************************************/ 310 static uint64_t spmd_handle_group0_intr_swd(void *handle) 311 { 312 uint32_t intid; 313 314 /* Sanity check the pointer to this cpu's context */ 315 assert(handle == cm_get_context(SECURE)); 316 317 assert(plat_ic_get_pending_interrupt_type() == INTR_TYPE_EL3); 318 319 intid = plat_ic_acknowledge_interrupt(); 320 321 /* 322 * TODO: Currently due to a limitation in SPMD implementation, the 323 * platform handler is expected to not delegate handling to NWd while 324 * processing Group0 secure interrupt. 325 */ 326 if (plat_spmd_handle_group0_interrupt(intid) < 0) { 327 /* Group0 interrupt was not handled by the platform. */ 328 ERROR("Group0 interrupt %u not handled\n", intid); 329 panic(); 330 } 331 332 /* Deactivate the corresponding Group0 interrupt. */ 333 plat_ic_end_of_interrupt(intid); 334 335 /* Return success. */ 336 SMC_RET8(handle, FFA_SUCCESS_SMC32, FFA_PARAM_MBZ, FFA_PARAM_MBZ, 337 FFA_PARAM_MBZ, FFA_PARAM_MBZ, FFA_PARAM_MBZ, FFA_PARAM_MBZ, 338 FFA_PARAM_MBZ); 339 } 340 341 #if ENABLE_RME && SPMD_SPM_AT_SEL2 && !RESET_TO_BL31 342 static int spmd_dynamic_map_mem(uintptr_t base_addr, size_t size, 343 unsigned int attr, uintptr_t *align_addr, 344 size_t *align_size) 345 { 346 uintptr_t base_addr_align; 347 size_t mapped_size_align; 348 int rc; 349 350 /* Page aligned address and size if necessary */ 351 base_addr_align = page_align(base_addr, DOWN); 352 mapped_size_align = page_align(size, UP); 353 354 if ((base_addr != base_addr_align) && 355 (size == mapped_size_align)) { 356 mapped_size_align += PAGE_SIZE; 357 } 358 359 /* 360 * Map dynamically given region with its aligned base address and 361 * size 362 */ 363 rc = mmap_add_dynamic_region((unsigned long long)base_addr_align, 364 base_addr_align, 365 mapped_size_align, 366 attr); 367 if (rc == 0) { 368 *align_addr = base_addr_align; 369 *align_size = mapped_size_align; 370 } 371 372 return rc; 373 } 374 375 static void spmd_do_sec_cpy(uintptr_t root_base_addr, uintptr_t sec_base_addr, 376 size_t size) 377 { 378 uintptr_t root_base_addr_align, sec_base_addr_align; 379 size_t root_mapped_size_align, sec_mapped_size_align; 380 int rc; 381 382 assert(root_base_addr != 0UL); 383 assert(sec_base_addr != 0UL); 384 assert(size != 0UL); 385 386 /* Map the memory with required attributes */ 387 rc = spmd_dynamic_map_mem(root_base_addr, size, MT_RO_DATA | MT_ROOT, 388 &root_base_addr_align, 389 &root_mapped_size_align); 390 if (rc != 0) { 391 ERROR("%s %s %lu (%d)\n", "Error while mapping", "root region", 392 root_base_addr, rc); 393 panic(); 394 } 395 396 rc = spmd_dynamic_map_mem(sec_base_addr, size, MT_RW_DATA | MT_SECURE, 397 &sec_base_addr_align, &sec_mapped_size_align); 398 if (rc != 0) { 399 ERROR("%s %s %lu (%d)\n", "Error while mapping", 400 "secure region", sec_base_addr, rc); 401 panic(); 402 } 403 404 /* Do copy operation */ 405 (void)memcpy((void *)sec_base_addr, (void *)root_base_addr, size); 406 407 /* Unmap root memory region */ 408 rc = mmap_remove_dynamic_region(root_base_addr_align, 409 root_mapped_size_align); 410 if (rc != 0) { 411 ERROR("%s %s %lu (%d)\n", "Error while unmapping", 412 "root region", root_base_addr_align, rc); 413 panic(); 414 } 415 416 /* Unmap secure memory region */ 417 rc = mmap_remove_dynamic_region(sec_base_addr_align, 418 sec_mapped_size_align); 419 if (rc != 0) { 420 ERROR("%s %s %lu (%d)\n", "Error while unmapping", 421 "secure region", sec_base_addr_align, rc); 422 panic(); 423 } 424 } 425 #endif /* ENABLE_RME && SPMD_SPM_AT_SEL2 && !RESET_TO_BL31 */ 426 427 /******************************************************************************* 428 * Loads SPMC manifest and inits SPMC. 429 ******************************************************************************/ 430 static int spmd_spmc_init(void *pm_addr) 431 { 432 cpu_context_t *cpu_ctx; 433 unsigned int core_id; 434 uint32_t ep_attr, flags; 435 int rc; 436 const struct dyn_cfg_dtb_info_t *image_info __unused; 437 438 /* Load the SPM Core manifest */ 439 rc = plat_spm_core_manifest_load(&spmc_attrs, pm_addr); 440 if (rc != 0) { 441 WARN("No or invalid SPM Core manifest image provided by BL2\n"); 442 return rc; 443 } 444 445 /* 446 * Ensure that the SPM Core version is compatible with the SPM 447 * Dispatcher version. 448 */ 449 if ((spmc_attrs.major_version != FFA_VERSION_MAJOR) || 450 (spmc_attrs.minor_version > FFA_VERSION_MINOR)) { 451 WARN("Unsupported FFA version (%u.%u)\n", 452 spmc_attrs.major_version, spmc_attrs.minor_version); 453 return -EINVAL; 454 } 455 456 VERBOSE("FFA version (%u.%u)\n", spmc_attrs.major_version, 457 spmc_attrs.minor_version); 458 459 VERBOSE("SPM Core run time EL%x.\n", 460 SPMD_SPM_AT_SEL2 ? MODE_EL2 : MODE_EL1); 461 462 /* Validate the SPMC ID, Ensure high bit is set */ 463 if (((spmc_attrs.spmc_id >> SPMC_SECURE_ID_SHIFT) & 464 SPMC_SECURE_ID_MASK) == 0U) { 465 WARN("Invalid ID (0x%x) for SPMC.\n", spmc_attrs.spmc_id); 466 return -EINVAL; 467 } 468 469 /* Validate the SPM Core execution state */ 470 if ((spmc_attrs.exec_state != MODE_RW_64) && 471 (spmc_attrs.exec_state != MODE_RW_32)) { 472 WARN("Unsupported %s%x.\n", "SPM Core execution state 0x", 473 spmc_attrs.exec_state); 474 return -EINVAL; 475 } 476 477 VERBOSE("%s%x.\n", "SPM Core execution state 0x", 478 spmc_attrs.exec_state); 479 480 #if SPMD_SPM_AT_SEL2 481 /* Ensure manifest has not requested AArch32 state in S-EL2 */ 482 if (spmc_attrs.exec_state == MODE_RW_32) { 483 WARN("AArch32 state at S-EL2 is not supported.\n"); 484 return -EINVAL; 485 } 486 487 /* 488 * Check if S-EL2 is supported on this system if S-EL2 489 * is required for SPM 490 */ 491 if (!is_feat_sel2_supported()) { 492 WARN("SPM Core run time S-EL2 is not supported.\n"); 493 return -EINVAL; 494 } 495 #endif /* SPMD_SPM_AT_SEL2 */ 496 497 /* Initialise an entrypoint to set up the CPU context */ 498 ep_attr = SECURE | EP_ST_ENABLE; 499 if ((read_sctlr_el3() & SCTLR_EE_BIT) != 0ULL) { 500 ep_attr |= EP_EE_BIG; 501 } 502 503 SET_PARAM_HEAD(spmc_ep_info, PARAM_EP, VERSION_1, ep_attr); 504 505 /* 506 * Populate SPSR for SPM Core based upon validated parameters from the 507 * manifest. 508 */ 509 if (spmc_attrs.exec_state == MODE_RW_32) { 510 spmc_ep_info->spsr = SPSR_MODE32(MODE32_svc, SPSR_T_ARM, 511 SPSR_E_LITTLE, 512 DAIF_FIQ_BIT | 513 DAIF_IRQ_BIT | 514 DAIF_ABT_BIT); 515 } else { 516 517 #if SPMD_SPM_AT_SEL2 518 static const uint32_t runtime_el = MODE_EL2; 519 #else 520 static const uint32_t runtime_el = MODE_EL1; 521 #endif 522 spmc_ep_info->spsr = SPSR_64(runtime_el, 523 MODE_SP_ELX, 524 DISABLE_ALL_EXCEPTIONS); 525 } 526 527 #if ENABLE_RME && SPMD_SPM_AT_SEL2 && !RESET_TO_BL31 528 image_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, TOS_FW_CONFIG_ID); 529 assert(image_info != NULL); 530 531 if ((image_info->config_addr == 0UL) || 532 (image_info->secondary_config_addr == 0UL) || 533 (image_info->config_max_size == 0UL)) { 534 return -EINVAL; 535 } 536 537 /* Copy manifest from root->secure region */ 538 spmd_do_sec_cpy(image_info->config_addr, 539 image_info->secondary_config_addr, 540 image_info->config_max_size); 541 542 /* Update ep info of BL32 */ 543 assert(spmc_ep_info != NULL); 544 spmc_ep_info->args.arg0 = image_info->secondary_config_addr; 545 #endif /* ENABLE_RME && SPMD_SPM_AT_SEL2 && !RESET_TO_BL31 */ 546 547 /* Set an initial SPMC context state for all cores. */ 548 for (core_id = 0U; core_id < PLATFORM_CORE_COUNT; core_id++) { 549 spm_core_context[core_id].state = SPMC_STATE_OFF; 550 551 /* Setup an initial cpu context for the SPMC. */ 552 cpu_ctx = &spm_core_context[core_id].cpu_ctx; 553 cm_setup_context(cpu_ctx, spmc_ep_info); 554 555 /* 556 * Pass the core linear ID to the SPMC through x4. 557 * (TF-A implementation defined behavior helping 558 * a legacy TOS migration to adopt FF-A). 559 */ 560 write_ctx_reg(get_gpregs_ctx(cpu_ctx), CTX_GPREG_X4, core_id); 561 } 562 563 /* Register power management hooks with PSCI */ 564 psci_register_spd_pm_hook(&spmd_pm); 565 566 /* Register init function for deferred init. */ 567 bl31_register_bl32_init(&spmd_init); 568 569 INFO("SPM Core setup done.\n"); 570 571 /* 572 * Register an interrupt handler routing secure interrupts to SPMD 573 * while the NWd is running. 574 */ 575 flags = 0; 576 set_interrupt_rm_flag(flags, NON_SECURE); 577 rc = register_interrupt_type_handler(INTR_TYPE_S_EL1, 578 spmd_secure_interrupt_handler, 579 flags); 580 if (rc != 0) { 581 panic(); 582 } 583 584 /* 585 * Permit configurations where the SPM resides at S-EL1/2 and upon a 586 * Group0 interrupt triggering while the normal world runs, the 587 * interrupt is routed either through the EHF or directly to the SPMD: 588 * 589 * EL3_EXCEPTION_HANDLING=0: the Group0 interrupt is routed to the SPMD 590 * for handling by spmd_group0_interrupt_handler_nwd. 591 * 592 * EL3_EXCEPTION_HANDLING=1: the Group0 interrupt is routed to the EHF. 593 * 594 */ 595 #if (EL3_EXCEPTION_HANDLING == 0) 596 /* 597 * If EL3 interrupts are supported by the platform, register an 598 * interrupt handler routing Group0 interrupts to SPMD while the NWd is 599 * running. 600 */ 601 if (plat_ic_has_interrupt_type(INTR_TYPE_EL3)) { 602 rc = register_interrupt_type_handler(INTR_TYPE_EL3, 603 spmd_group0_interrupt_handler_nwd, 604 flags); 605 if (rc != 0) { 606 panic(); 607 } 608 } 609 #endif 610 611 return 0; 612 } 613 614 /******************************************************************************* 615 * Initialize context of SPM Core. 616 ******************************************************************************/ 617 int spmd_setup(void) 618 { 619 int rc; 620 void *spmc_manifest; 621 622 /* 623 * If the SPMC is at EL3, then just initialise it directly. The 624 * shenanigans of when it is at a lower EL are not needed. 625 */ 626 if (is_spmc_at_el3()) { 627 /* Allow the SPMC to populate its attributes directly. */ 628 spmc_populate_attrs(&spmc_attrs); 629 630 rc = spmc_setup(); 631 if (rc != 0) { 632 WARN("SPMC initialisation failed 0x%x.\n", rc); 633 } 634 return 0; 635 } 636 637 spmc_ep_info = bl31_plat_get_next_image_ep_info(SECURE); 638 if (spmc_ep_info == NULL) { 639 WARN("No SPM Core image provided by BL2 boot loader.\n"); 640 return 0; 641 } 642 643 /* Under no circumstances will this parameter be 0 */ 644 assert(spmc_ep_info->pc != 0ULL); 645 646 /* 647 * Check if BL32 ep_info has a reference to 'tos_fw_config'. This will 648 * be used as a manifest for the SPM Core at the next lower EL/mode. 649 */ 650 spmc_manifest = (void *)spmc_ep_info->args.arg0; 651 if (spmc_manifest == NULL) { 652 WARN("Invalid or absent SPM Core manifest.\n"); 653 return 0; 654 } 655 656 /* Load manifest, init SPMC */ 657 rc = spmd_spmc_init(spmc_manifest); 658 if (rc != 0) { 659 WARN("Booting device without SPM initialization.\n"); 660 } 661 662 return 0; 663 } 664 665 /******************************************************************************* 666 * Forward FF-A SMCs to the other security state. 667 ******************************************************************************/ 668 uint64_t spmd_smc_switch_state(uint32_t smc_fid, 669 bool secure_origin, 670 uint64_t x1, 671 uint64_t x2, 672 uint64_t x3, 673 uint64_t x4, 674 void *handle, 675 uint64_t flags) 676 { 677 unsigned int secure_state_in = (secure_origin) ? SECURE : NON_SECURE; 678 unsigned int secure_state_out = (!secure_origin) ? SECURE : NON_SECURE; 679 void *ctx_out; 680 681 #if SPMD_SPM_AT_SEL2 682 if ((secure_state_out == SECURE) && (is_sve_hint_set(flags) == true)) { 683 /* 684 * Set the SVE hint bit in x0 and pass to the lower secure EL, 685 * if it was set by the caller. 686 */ 687 smc_fid |= (FUNCID_SVE_HINT_MASK << FUNCID_SVE_HINT_SHIFT); 688 } 689 #endif 690 691 /* Save incoming security state */ 692 #if SPMD_SPM_AT_SEL2 693 cm_el2_sysregs_context_save(secure_state_in); 694 #else 695 cm_el1_sysregs_context_save(secure_state_in); 696 #if CTX_INCLUDE_FPREGS || CTX_INCLUDE_SVE_REGS 697 /* Forward the hint bit denoting the absence of SVE live state. */ 698 simd_ctx_save(secure_state_in, (!secure_origin && (is_sve_hint_set(flags) == true))); 699 #endif 700 #endif 701 702 /* Restore outgoing security state */ 703 #if SPMD_SPM_AT_SEL2 704 cm_el2_sysregs_context_restore(secure_state_out); 705 #else 706 cm_el1_sysregs_context_restore(secure_state_out); 707 #if CTX_INCLUDE_FPREGS || CTX_INCLUDE_SVE_REGS 708 simd_ctx_restore(secure_state_out); 709 #endif 710 #endif 711 cm_set_next_eret_context(secure_state_out); 712 713 ctx_out = cm_get_context(secure_state_out); 714 if (smc_fid == FFA_NORMAL_WORLD_RESUME) { 715 SMC_RET0(ctx_out); 716 } 717 718 #if SPMD_SPM_AT_SEL2 719 /* 720 * If SPMC is at SEL2, save additional registers x8-x17, which may 721 * be used in FF-A calls such as FFA_PARTITION_INFO_GET_REGS. 722 * Note that technically, all SPMCs can support this, but this code is 723 * under ifdef to minimize breakage in case other SPMCs do not save 724 * and restore x8-x17. 725 * We also need to pass through these registers since not all FF-A ABIs 726 * modify x8-x17, in which case, SMCCC requires that these registers be 727 * preserved, so the SPMD passes through these registers and expects the 728 * SPMC to save and restore (potentially also modify) them. 729 */ 730 SMC_RET18(ctx_out, smc_fid, x1, x2, x3, x4, 731 SMC_GET_GP(handle, CTX_GPREG_X5), 732 SMC_GET_GP(handle, CTX_GPREG_X6), 733 SMC_GET_GP(handle, CTX_GPREG_X7), 734 SMC_GET_GP(handle, CTX_GPREG_X8), 735 SMC_GET_GP(handle, CTX_GPREG_X9), 736 SMC_GET_GP(handle, CTX_GPREG_X10), 737 SMC_GET_GP(handle, CTX_GPREG_X11), 738 SMC_GET_GP(handle, CTX_GPREG_X12), 739 SMC_GET_GP(handle, CTX_GPREG_X13), 740 SMC_GET_GP(handle, CTX_GPREG_X14), 741 SMC_GET_GP(handle, CTX_GPREG_X15), 742 SMC_GET_GP(handle, CTX_GPREG_X16), 743 SMC_GET_GP(handle, CTX_GPREG_X17) 744 ); 745 746 #else 747 SMC_RET8(ctx_out, smc_fid, x1, x2, x3, x4, 748 SMC_GET_GP(handle, CTX_GPREG_X5), 749 SMC_GET_GP(handle, CTX_GPREG_X6), 750 SMC_GET_GP(handle, CTX_GPREG_X7)); 751 #endif 752 } 753 754 /******************************************************************************* 755 * Forward SMCs to the other security state. 756 ******************************************************************************/ 757 static uint64_t spmd_smc_forward(uint32_t smc_fid, 758 bool secure_origin, 759 uint64_t x1, 760 uint64_t x2, 761 uint64_t x3, 762 uint64_t x4, 763 void *cookie, 764 void *handle, 765 uint64_t flags) 766 { 767 if (is_spmc_at_el3() && !secure_origin) { 768 return spmc_smc_handler(smc_fid, secure_origin, x1, x2, x3, x4, 769 cookie, handle, flags); 770 } 771 772 return spmd_smc_switch_state(smc_fid, secure_origin, x1, x2, x3, x4, 773 handle, flags); 774 775 } 776 777 /******************************************************************************* 778 * Return FFA_ERROR with specified error code 779 ******************************************************************************/ 780 uint64_t spmd_ffa_error_return(void *handle, int error_code) 781 { 782 SMC_RET8(handle, (uint32_t) FFA_ERROR, 783 FFA_TARGET_INFO_MBZ, (uint32_t)error_code, 784 FFA_PARAM_MBZ, FFA_PARAM_MBZ, FFA_PARAM_MBZ, 785 FFA_PARAM_MBZ, FFA_PARAM_MBZ); 786 } 787 788 /******************************************************************************* 789 * spmd_check_address_in_binary_image 790 ******************************************************************************/ 791 bool spmd_check_address_in_binary_image(uint64_t address) 792 { 793 assert(!check_uptr_overflow(spmc_attrs.load_address, spmc_attrs.binary_size)); 794 795 return ((address >= spmc_attrs.load_address) && 796 (address < (spmc_attrs.load_address + spmc_attrs.binary_size))); 797 } 798 799 /****************************************************************************** 800 * spmd_is_spmc_message 801 *****************************************************************************/ 802 static bool spmd_is_spmc_message(unsigned int ep) 803 { 804 if (is_spmc_at_el3()) { 805 return false; 806 } 807 808 return ((ffa_endpoint_destination(ep) == SPMD_DIRECT_MSG_ENDPOINT_ID) 809 && (ffa_endpoint_source(ep) == spmc_attrs.spmc_id)); 810 } 811 812 /******************************************************************************* 813 * This function forwards FF-A SMCs to either the main SPMD handler or the 814 * SPMC at EL3, depending on the origin security state, if enabled. 815 ******************************************************************************/ 816 uint64_t spmd_ffa_smc_handler(uint32_t smc_fid, 817 uint64_t x1, 818 uint64_t x2, 819 uint64_t x3, 820 uint64_t x4, 821 void *cookie, 822 void *handle, 823 uint64_t flags) 824 { 825 if (is_spmc_at_el3()) { 826 /* 827 * If we have an SPMC at EL3 allow handling of the SMC first. 828 * The SPMC will call back through to SPMD handler if required. 829 */ 830 if (is_caller_secure(flags)) { 831 return spmc_smc_handler(smc_fid, 832 is_caller_secure(flags), 833 x1, x2, x3, x4, cookie, 834 handle, flags); 835 } 836 } 837 return spmd_smc_handler(smc_fid, x1, x2, x3, x4, cookie, 838 handle, flags); 839 } 840 841 /******************************************************************************* 842 * This function handles all SMCs in the range reserved for FFA. Each call is 843 * either forwarded to the other security state or handled by the SPM dispatcher 844 ******************************************************************************/ 845 uint64_t spmd_smc_handler(uint32_t smc_fid, 846 uint64_t x1, 847 uint64_t x2, 848 uint64_t x3, 849 uint64_t x4, 850 void *cookie, 851 void *handle, 852 uint64_t flags) 853 { 854 spmd_spm_core_context_t *ctx = spmd_get_context(); 855 bool secure_origin; 856 int ret; 857 uint32_t input_version; 858 859 /* Determine which security state this SMC originated from */ 860 secure_origin = is_caller_secure(flags); 861 862 VERBOSE("SPM(%u): 0x%x 0x%" PRIx64 " 0x%" PRIx64 " 0x%" PRIx64 " 0x%" PRIx64 863 " 0x%" PRIx64 " 0x%" PRIx64 " 0x%" PRIx64 "\n", 864 plat_my_core_pos(), smc_fid, x1, x2, x3, x4, 865 SMC_GET_GP(handle, CTX_GPREG_X5), 866 SMC_GET_GP(handle, CTX_GPREG_X6), 867 SMC_GET_GP(handle, CTX_GPREG_X7)); 868 869 /* 870 * If there is an on-going info regs from EL3 SPMD LP, unconditionally 871 * return, we don't expect any other FF-A ABIs to be called between 872 * calls to FFA_PARTITION_INFO_GET_REGS. 873 */ 874 if (is_spmd_logical_sp_info_regs_req_in_progress(ctx)) { 875 assert(secure_origin); 876 spmd_spm_core_sync_exit(0ULL); 877 } 878 879 switch (smc_fid) { 880 case FFA_ERROR: 881 /* 882 * Check if this is the first invocation of this interface on 883 * this CPU. If so, then indicate that the SPM Core initialised 884 * unsuccessfully. 885 */ 886 if (secure_origin && (ctx->state == SPMC_STATE_ON_PENDING)) { 887 spmd_spm_core_sync_exit(x2); 888 } 889 890 /* 891 * If there was an SPMD logical partition direct request on-going, 892 * return back to the SPMD logical partition so the error can be 893 * consumed. 894 */ 895 if (is_spmd_logical_sp_dir_req_in_progress(ctx)) { 896 assert(secure_origin); 897 spmd_spm_core_sync_exit(0ULL); 898 } 899 900 return spmd_smc_forward(smc_fid, secure_origin, 901 x1, x2, x3, x4, cookie, 902 handle, flags); 903 break; /* not reached */ 904 905 case FFA_VERSION: 906 input_version = (uint32_t)(0xFFFFFFFF & x1); 907 /* 908 * If caller is secure and SPMC was initialized, 909 * return FFA_VERSION of SPMD. 910 * If caller is non secure and SPMC was initialized, 911 * forward to the EL3 SPMC if enabled, otherwise return 912 * the SPMC version if implemented at a lower EL. 913 * Sanity check to "input_version". 914 * If the EL3 SPMC is enabled, ignore the SPMC state as 915 * this is not used. 916 */ 917 if ((input_version & FFA_VERSION_BIT31_MASK) || 918 (!is_spmc_at_el3() && (ctx->state == SPMC_STATE_RESET))) { 919 ret = FFA_ERROR_NOT_SUPPORTED; 920 } else if (!secure_origin) { 921 if (is_spmc_at_el3()) { 922 /* 923 * Forward the call directly to the EL3 SPMC, if 924 * enabled, as we don't need to wrap the call in 925 * a direct request. 926 */ 927 return spmd_smc_forward(smc_fid, secure_origin, 928 x1, x2, x3, x4, cookie, 929 handle, flags); 930 } 931 932 gp_regs_t *gpregs = get_gpregs_ctx(&ctx->cpu_ctx); 933 uint64_t rc; 934 935 if (spmc_attrs.major_version == 1 && 936 spmc_attrs.minor_version == 0) { 937 ret = MAKE_FFA_VERSION(spmc_attrs.major_version, 938 spmc_attrs.minor_version); 939 SMC_RET8(handle, (uint32_t)ret, 940 FFA_TARGET_INFO_MBZ, 941 FFA_TARGET_INFO_MBZ, 942 FFA_PARAM_MBZ, FFA_PARAM_MBZ, 943 FFA_PARAM_MBZ, FFA_PARAM_MBZ, 944 FFA_PARAM_MBZ); 945 break; 946 } 947 /* Save non-secure system registers context */ 948 #if SPMD_SPM_AT_SEL2 949 cm_el2_sysregs_context_save(NON_SECURE); 950 #else 951 cm_el1_sysregs_context_save(NON_SECURE); 952 #endif 953 954 /* 955 * The incoming request has FFA_VERSION as X0 smc_fid 956 * and requested version in x1. Prepare a direct request 957 * from SPMD to SPMC with FFA_VERSION framework function 958 * identifier in X2 and requested version in X3. 959 */ 960 spmd_build_spmc_message(gpregs, 961 SPMD_FWK_MSG_FFA_VERSION_REQ, 962 input_version); 963 964 /* 965 * Ensure x8-x17 NS GP register values are untouched when returning 966 * from the SPMC. 967 */ 968 write_ctx_reg(gpregs, CTX_GPREG_X8, SMC_GET_GP(handle, CTX_GPREG_X8)); 969 write_ctx_reg(gpregs, CTX_GPREG_X9, SMC_GET_GP(handle, CTX_GPREG_X9)); 970 write_ctx_reg(gpregs, CTX_GPREG_X10, SMC_GET_GP(handle, CTX_GPREG_X10)); 971 write_ctx_reg(gpregs, CTX_GPREG_X11, SMC_GET_GP(handle, CTX_GPREG_X11)); 972 write_ctx_reg(gpregs, CTX_GPREG_X12, SMC_GET_GP(handle, CTX_GPREG_X12)); 973 write_ctx_reg(gpregs, CTX_GPREG_X13, SMC_GET_GP(handle, CTX_GPREG_X13)); 974 write_ctx_reg(gpregs, CTX_GPREG_X14, SMC_GET_GP(handle, CTX_GPREG_X14)); 975 write_ctx_reg(gpregs, CTX_GPREG_X15, SMC_GET_GP(handle, CTX_GPREG_X15)); 976 write_ctx_reg(gpregs, CTX_GPREG_X16, SMC_GET_GP(handle, CTX_GPREG_X16)); 977 write_ctx_reg(gpregs, CTX_GPREG_X17, SMC_GET_GP(handle, CTX_GPREG_X17)); 978 979 rc = spmd_spm_core_sync_entry(ctx); 980 981 if ((rc != 0ULL) || 982 (SMC_GET_GP(gpregs, CTX_GPREG_X0) != 983 FFA_MSG_SEND_DIRECT_RESP_SMC32) || 984 (SMC_GET_GP(gpregs, CTX_GPREG_X2) != 985 (FFA_FWK_MSG_BIT | 986 SPMD_FWK_MSG_FFA_VERSION_RESP))) { 987 ERROR("Failed to forward FFA_VERSION\n"); 988 ret = FFA_ERROR_NOT_SUPPORTED; 989 } else { 990 ret = SMC_GET_GP(gpregs, CTX_GPREG_X3); 991 } 992 993 /* 994 * x0-x4 are updated by spmd_smc_forward below. 995 * Zero out x5-x7 in the FFA_VERSION response. 996 */ 997 write_ctx_reg(gpregs, CTX_GPREG_X5, 0); 998 write_ctx_reg(gpregs, CTX_GPREG_X6, 0); 999 write_ctx_reg(gpregs, CTX_GPREG_X7, 0); 1000 1001 /* 1002 * Return here after SPMC has handled FFA_VERSION. 1003 * The returned SPMC version is held in X3. 1004 * Forward this version in X0 to the non-secure caller. 1005 */ 1006 return spmd_smc_forward(ret, true, FFA_PARAM_MBZ, 1007 FFA_PARAM_MBZ, FFA_PARAM_MBZ, 1008 FFA_PARAM_MBZ, cookie, gpregs, 1009 flags); 1010 } else { 1011 ret = MAKE_FFA_VERSION(FFA_VERSION_MAJOR, 1012 FFA_VERSION_MINOR); 1013 } 1014 1015 SMC_RET8(handle, (uint32_t)ret, FFA_TARGET_INFO_MBZ, 1016 FFA_TARGET_INFO_MBZ, FFA_PARAM_MBZ, FFA_PARAM_MBZ, 1017 FFA_PARAM_MBZ, FFA_PARAM_MBZ, FFA_PARAM_MBZ); 1018 break; /* not reached */ 1019 1020 case FFA_FEATURES: 1021 /* 1022 * This is an optional interface. Do the minimal checks and 1023 * forward to SPM Core which will handle it if implemented. 1024 */ 1025 1026 /* Forward SMC from Normal world to the SPM Core */ 1027 if (!secure_origin) { 1028 return spmd_smc_forward(smc_fid, secure_origin, 1029 x1, x2, x3, x4, cookie, 1030 handle, flags); 1031 } 1032 1033 /* 1034 * Return success if call was from secure world i.e. all 1035 * FFA functions are supported. This is essentially a 1036 * nop. 1037 */ 1038 SMC_RET8(handle, FFA_SUCCESS_SMC32, x1, x2, x3, x4, 1039 SMC_GET_GP(handle, CTX_GPREG_X5), 1040 SMC_GET_GP(handle, CTX_GPREG_X6), 1041 SMC_GET_GP(handle, CTX_GPREG_X7)); 1042 1043 break; /* not reached */ 1044 1045 case FFA_ID_GET: 1046 /* 1047 * Returns the ID of the calling FFA component. 1048 */ 1049 if (!secure_origin) { 1050 SMC_RET8(handle, FFA_SUCCESS_SMC32, 1051 FFA_TARGET_INFO_MBZ, FFA_NS_ENDPOINT_ID, 1052 FFA_PARAM_MBZ, FFA_PARAM_MBZ, 1053 FFA_PARAM_MBZ, FFA_PARAM_MBZ, 1054 FFA_PARAM_MBZ); 1055 } 1056 1057 SMC_RET8(handle, FFA_SUCCESS_SMC32, 1058 FFA_TARGET_INFO_MBZ, spmc_attrs.spmc_id, 1059 FFA_PARAM_MBZ, FFA_PARAM_MBZ, 1060 FFA_PARAM_MBZ, FFA_PARAM_MBZ, 1061 FFA_PARAM_MBZ); 1062 1063 break; /* not reached */ 1064 1065 case FFA_SECONDARY_EP_REGISTER_SMC64: 1066 if (secure_origin) { 1067 ret = spmd_pm_secondary_ep_register(x1); 1068 1069 if (ret < 0) { 1070 SMC_RET8(handle, FFA_ERROR_SMC64, 1071 FFA_TARGET_INFO_MBZ, ret, 1072 FFA_PARAM_MBZ, FFA_PARAM_MBZ, 1073 FFA_PARAM_MBZ, FFA_PARAM_MBZ, 1074 FFA_PARAM_MBZ); 1075 } else { 1076 SMC_RET8(handle, FFA_SUCCESS_SMC64, 1077 FFA_TARGET_INFO_MBZ, FFA_PARAM_MBZ, 1078 FFA_PARAM_MBZ, FFA_PARAM_MBZ, 1079 FFA_PARAM_MBZ, FFA_PARAM_MBZ, 1080 FFA_PARAM_MBZ); 1081 } 1082 } 1083 1084 return spmd_ffa_error_return(handle, FFA_ERROR_NOT_SUPPORTED); 1085 break; /* Not reached */ 1086 1087 case FFA_SPM_ID_GET: 1088 if (MAKE_FFA_VERSION(1, 1) > FFA_VERSION_COMPILED) { 1089 return spmd_ffa_error_return(handle, 1090 FFA_ERROR_NOT_SUPPORTED); 1091 } 1092 /* 1093 * Returns the ID of the SPMC or SPMD depending on the FF-A 1094 * instance where this function is invoked 1095 */ 1096 if (!secure_origin) { 1097 SMC_RET8(handle, FFA_SUCCESS_SMC32, 1098 FFA_TARGET_INFO_MBZ, spmc_attrs.spmc_id, 1099 FFA_PARAM_MBZ, FFA_PARAM_MBZ, 1100 FFA_PARAM_MBZ, FFA_PARAM_MBZ, 1101 FFA_PARAM_MBZ); 1102 } 1103 SMC_RET8(handle, FFA_SUCCESS_SMC32, 1104 FFA_TARGET_INFO_MBZ, SPMD_DIRECT_MSG_ENDPOINT_ID, 1105 FFA_PARAM_MBZ, FFA_PARAM_MBZ, 1106 FFA_PARAM_MBZ, FFA_PARAM_MBZ, 1107 FFA_PARAM_MBZ); 1108 1109 break; /* not reached */ 1110 1111 case FFA_MSG_SEND_DIRECT_REQ_SMC32: 1112 case FFA_MSG_SEND_DIRECT_REQ_SMC64: 1113 case FFA_MSG_SEND_DIRECT_REQ2_SMC64: 1114 /* 1115 * Regardless of secure_origin, SPMD logical partitions cannot 1116 * handle direct messages. They can only initiate direct 1117 * messages and consume direct responses or errors. 1118 */ 1119 if (is_spmd_lp_id(ffa_endpoint_source(x1)) || 1120 is_spmd_lp_id(ffa_endpoint_destination(x1))) { 1121 return spmd_ffa_error_return(handle, 1122 FFA_ERROR_INVALID_PARAMETER 1123 ); 1124 } 1125 1126 /* 1127 * When there is an ongoing SPMD logical partition direct 1128 * request, there cannot be another direct request. Return 1129 * error in this case. Panic'ing is an option but that does 1130 * not provide the opportunity for caller to abort based on 1131 * error codes. 1132 */ 1133 if (is_spmd_logical_sp_dir_req_in_progress(ctx)) { 1134 assert(secure_origin); 1135 return spmd_ffa_error_return(handle, 1136 FFA_ERROR_DENIED); 1137 } 1138 1139 if (!secure_origin) { 1140 /* Validate source endpoint is non-secure for non-secure caller. */ 1141 if (ffa_is_secure_world_id(ffa_endpoint_source(x1))) { 1142 return spmd_ffa_error_return(handle, 1143 FFA_ERROR_INVALID_PARAMETER); 1144 } 1145 } 1146 if (secure_origin && spmd_is_spmc_message(x1)) { 1147 return spmd_ffa_error_return(handle, 1148 FFA_ERROR_DENIED); 1149 } else { 1150 /* Forward direct message to the other world */ 1151 return spmd_smc_forward(smc_fid, secure_origin, 1152 x1, x2, x3, x4, cookie, 1153 handle, flags); 1154 } 1155 break; /* Not reached */ 1156 1157 case FFA_MSG_SEND_DIRECT_RESP_SMC32: 1158 case FFA_MSG_SEND_DIRECT_RESP_SMC64: 1159 case FFA_MSG_SEND_DIRECT_RESP2_SMC64: 1160 if (secure_origin && (spmd_is_spmc_message(x1) || 1161 is_spmd_logical_sp_dir_req_in_progress(ctx))) { 1162 spmd_spm_core_sync_exit(0ULL); 1163 } else { 1164 /* Forward direct message to the other world */ 1165 return spmd_smc_forward(smc_fid, secure_origin, 1166 x1, x2, x3, x4, cookie, 1167 handle, flags); 1168 } 1169 break; /* Not reached */ 1170 case FFA_RX_RELEASE: 1171 case FFA_RXTX_MAP_SMC32: 1172 case FFA_RXTX_MAP_SMC64: 1173 case FFA_RXTX_UNMAP: 1174 case FFA_PARTITION_INFO_GET: 1175 #if MAKE_FFA_VERSION(1, 1) <= FFA_VERSION_COMPILED 1176 case FFA_NOTIFICATION_BITMAP_CREATE: 1177 case FFA_NOTIFICATION_BITMAP_DESTROY: 1178 case FFA_NOTIFICATION_BIND: 1179 case FFA_NOTIFICATION_UNBIND: 1180 case FFA_NOTIFICATION_SET: 1181 case FFA_NOTIFICATION_GET: 1182 case FFA_NOTIFICATION_INFO_GET: 1183 case FFA_NOTIFICATION_INFO_GET_SMC64: 1184 case FFA_MSG_SEND2: 1185 case FFA_RX_ACQUIRE: 1186 #endif 1187 case FFA_MSG_RUN: 1188 /* 1189 * Above calls should be invoked only by the Normal world and 1190 * must not be forwarded from Secure world to Normal world. 1191 */ 1192 if (secure_origin) { 1193 return spmd_ffa_error_return(handle, 1194 FFA_ERROR_NOT_SUPPORTED); 1195 } 1196 1197 /* Forward the call to the other world */ 1198 /* fallthrough */ 1199 case FFA_MSG_SEND: 1200 case FFA_MEM_DONATE_SMC32: 1201 case FFA_MEM_DONATE_SMC64: 1202 case FFA_MEM_LEND_SMC32: 1203 case FFA_MEM_LEND_SMC64: 1204 case FFA_MEM_SHARE_SMC32: 1205 case FFA_MEM_SHARE_SMC64: 1206 case FFA_MEM_RETRIEVE_REQ_SMC32: 1207 case FFA_MEM_RETRIEVE_REQ_SMC64: 1208 case FFA_MEM_RETRIEVE_RESP: 1209 case FFA_MEM_RELINQUISH: 1210 case FFA_MEM_RECLAIM: 1211 case FFA_MEM_FRAG_TX: 1212 case FFA_MEM_FRAG_RX: 1213 case FFA_SUCCESS_SMC32: 1214 case FFA_SUCCESS_SMC64: 1215 /* 1216 * If there is an ongoing direct request from an SPMD logical 1217 * partition, return an error. 1218 */ 1219 if (is_spmd_logical_sp_dir_req_in_progress(ctx)) { 1220 assert(secure_origin); 1221 return spmd_ffa_error_return(handle, 1222 FFA_ERROR_DENIED); 1223 } 1224 1225 return spmd_smc_forward(smc_fid, secure_origin, 1226 x1, x2, x3, x4, cookie, 1227 handle, flags); 1228 break; /* not reached */ 1229 1230 case FFA_MSG_WAIT: 1231 /* 1232 * Check if this is the first invocation of this interface on 1233 * this CPU from the Secure world. If so, then indicate that the 1234 * SPM Core initialised successfully. 1235 */ 1236 if (secure_origin && (ctx->state == SPMC_STATE_ON_PENDING)) { 1237 spmd_spm_core_sync_exit(0ULL); 1238 } 1239 1240 /* Forward the call to the other world */ 1241 /* fallthrough */ 1242 case FFA_INTERRUPT: 1243 case FFA_MSG_YIELD: 1244 /* This interface must be invoked only by the Secure world */ 1245 if (!secure_origin) { 1246 return spmd_ffa_error_return(handle, 1247 FFA_ERROR_NOT_SUPPORTED); 1248 } 1249 1250 if (is_spmd_logical_sp_dir_req_in_progress(ctx)) { 1251 assert(secure_origin); 1252 return spmd_ffa_error_return(handle, 1253 FFA_ERROR_DENIED); 1254 } 1255 1256 return spmd_smc_forward(smc_fid, secure_origin, 1257 x1, x2, x3, x4, cookie, 1258 handle, flags); 1259 break; /* not reached */ 1260 1261 case FFA_NORMAL_WORLD_RESUME: 1262 if (secure_origin && ctx->secure_interrupt_ongoing) { 1263 spmd_spm_core_sync_exit(0ULL); 1264 } else { 1265 return spmd_ffa_error_return(handle, FFA_ERROR_DENIED); 1266 } 1267 break; /* Not reached */ 1268 #if MAKE_FFA_VERSION(1, 1) <= FFA_VERSION_COMPILED 1269 case FFA_PARTITION_INFO_GET_REGS_SMC64: 1270 if (secure_origin) { 1271 return spmd_el3_populate_logical_partition_info(handle, x1, 1272 x2, x3); 1273 } 1274 1275 /* Call only supported with SMCCC 1.2+ */ 1276 if (MAKE_SMCCC_VERSION(SMCCC_MAJOR_VERSION, SMCCC_MINOR_VERSION) < 0x10002) { 1277 return spmd_ffa_error_return(handle, FFA_ERROR_NOT_SUPPORTED); 1278 } 1279 1280 return spmd_smc_forward(smc_fid, secure_origin, 1281 x1, x2, x3, x4, cookie, 1282 handle, flags); 1283 break; /* Not reached */ 1284 #endif 1285 case FFA_CONSOLE_LOG_SMC32: 1286 case FFA_CONSOLE_LOG_SMC64: 1287 /* This interface must not be forwarded to other worlds. */ 1288 return spmd_ffa_error_return(handle, FFA_ERROR_NOT_SUPPORTED); 1289 break; /* not reached */ 1290 1291 case FFA_EL3_INTR_HANDLE: 1292 if (secure_origin) { 1293 return spmd_handle_group0_intr_swd(handle); 1294 } else { 1295 return spmd_ffa_error_return(handle, FFA_ERROR_NOT_SUPPORTED); 1296 } 1297 default: 1298 WARN("SPM: Unsupported call 0x%08x\n", smc_fid); 1299 return spmd_ffa_error_return(handle, FFA_ERROR_NOT_SUPPORTED); 1300 } 1301 } 1302