1 /* 2 * Copyright (c) 2015-2025, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 #ifndef PLAT_ARM_H 7 #define PLAT_ARM_H 8 9 #include <stdbool.h> 10 #include <stdint.h> 11 12 #include <common/desc_image_load.h> 13 #include <drivers/arm/tzc_common.h> 14 #include <lib/bakery_lock.h> 15 #include <lib/cassert.h> 16 #include <lib/el3_runtime/cpu_data.h> 17 #include <lib/gpt_rme/gpt_rme.h> 18 #include <lib/spinlock.h> 19 #include <lib/transfer_list.h> 20 #include <lib/utils_def.h> 21 #include <lib/xlat_tables/xlat_tables_compat.h> 22 23 /******************************************************************************* 24 * Forward declarations 25 ******************************************************************************/ 26 struct meminfo; 27 struct image_info; 28 struct bl_params; 29 30 typedef struct arm_tzc_regions_info { 31 unsigned long long base; 32 unsigned long long end; 33 unsigned int sec_attr; 34 unsigned int nsaid_permissions; 35 } arm_tzc_regions_info_t; 36 37 typedef struct arm_gpt_info { 38 pas_region_t *pas_region_base; 39 unsigned int pas_region_count; 40 uintptr_t l0_base; 41 uintptr_t l1_base; 42 size_t l0_size; 43 size_t l1_size; 44 gpccr_pps_e pps; 45 gpccr_pgs_e pgs; 46 } arm_gpt_info_t; 47 48 /******************************************************************************* 49 * Default mapping definition of the TrustZone Controller for ARM standard 50 * platforms. 51 * Configure: 52 * - Region 0 with no access; 53 * - Region 1 with secure access only; 54 * - the remaining DRAM regions access from the given Non-Secure masters. 55 ******************************************************************************/ 56 57 #if ENABLE_RME 58 #define ARM_TZC_RME_REGIONS_DEF \ 59 {ARM_AP_TZC_DRAM1_BASE, ARM_AP_TZC_DRAM1_END, TZC_REGION_S_RDWR, 0},\ 60 {ARM_EL3_TZC_DRAM1_BASE, ARM_L1_GPT_END, TZC_REGION_S_RDWR, 0}, \ 61 {ARM_NS_DRAM1_BASE, ARM_NS_DRAM1_END, ARM_TZC_NS_DRAM_S_ACCESS, \ 62 PLAT_ARM_TZC_NS_DEV_ACCESS}, \ 63 /* Realm and Shared area share the same PAS */ \ 64 {ARM_REALM_BASE, ARM_EL3_RMM_SHARED_END, ARM_TZC_NS_DRAM_S_ACCESS, \ 65 PLAT_ARM_TZC_NS_DEV_ACCESS}, \ 66 {ARM_DRAM2_BASE, ARM_DRAM2_END, ARM_TZC_NS_DRAM_S_ACCESS, \ 67 PLAT_ARM_TZC_NS_DEV_ACCESS} 68 #endif 69 70 #if SPM_MM || (SPMC_AT_EL3 && SPMC_AT_EL3_SEL0_SP) 71 #define ARM_TZC_REGIONS_DEF \ 72 {ARM_NS_DRAM1_BASE, ARM_NS_DRAM1_END, ARM_TZC_NS_DRAM_S_ACCESS, \ 73 PLAT_ARM_TZC_NS_DEV_ACCESS}, \ 74 {ARM_AP_TZC_DRAM1_BASE, (PLAT_SP_IMAGE_NS_BUF_BASE - 1), \ 75 TZC_REGION_S_RDWR, 0}, \ 76 {PLAT_SP_IMAGE_NS_BUF_BASE, (PLAT_SP_IMAGE_NS_BUF_BASE + \ 77 PLAT_SP_IMAGE_NS_BUF_SIZE - 1), TZC_REGION_S_NONE, \ 78 PLAT_ARM_TZC_NS_DEV_ACCESS}, \ 79 {PLAT_SP_IMAGE_STACK_BASE, ARM_EL3_TZC_DRAM1_END, \ 80 TZC_REGION_S_RDWR, 0}, \ 81 {ARM_DRAM2_BASE, ARM_DRAM2_END, ARM_TZC_NS_DRAM_S_ACCESS, \ 82 PLAT_ARM_TZC_NS_DEV_ACCESS} 83 84 #elif ENABLE_RME 85 #if (defined(SPD_tspd) || defined(SPD_opteed) || defined(SPD_spmd)) && \ 86 MEASURED_BOOT 87 #define ARM_TZC_REGIONS_DEF \ 88 ARM_TZC_RME_REGIONS_DEF, \ 89 {ARM_EVENT_LOG_DRAM1_BASE, ARM_EVENT_LOG_DRAM1_END, \ 90 TZC_REGION_S_RDWR, 0} 91 #else 92 #define ARM_TZC_REGIONS_DEF \ 93 ARM_TZC_RME_REGIONS_DEF 94 #endif 95 96 #else 97 #define ARM_TZC_REGIONS_DEF \ 98 {ARM_AP_TZC_DRAM1_BASE, ARM_EL3_TZC_DRAM1_END + ARM_L1_GPT_SIZE,\ 99 TZC_REGION_S_RDWR, 0}, \ 100 {ARM_NS_DRAM1_BASE, ARM_NS_DRAM1_END, ARM_TZC_NS_DRAM_S_ACCESS, \ 101 PLAT_ARM_TZC_NS_DEV_ACCESS}, \ 102 {ARM_DRAM2_BASE, ARM_DRAM2_END, ARM_TZC_NS_DRAM_S_ACCESS, \ 103 PLAT_ARM_TZC_NS_DEV_ACCESS} 104 #endif 105 106 #define ARM_CASSERT_MMAP \ 107 CASSERT((ARRAY_SIZE(plat_arm_mmap) - 1) <= PLAT_ARM_MMAP_ENTRIES, \ 108 assert_plat_arm_mmap_mismatch); \ 109 CASSERT((PLAT_ARM_MMAP_ENTRIES + ARM_BL_REGIONS) \ 110 <= MAX_MMAP_REGIONS, \ 111 assert_max_mmap_regions); 112 113 void arm_setup_romlib(void); 114 115 #if defined(IMAGE_BL31) || (!defined(__aarch64__) && defined(IMAGE_BL32)) 116 /* 117 * Use this macro to instantiate lock before it is used in below 118 * arm_lock_xxx() macros 119 */ 120 #define ARM_INSTANTIATE_LOCK static DEFINE_BAKERY_LOCK(arm_lock) 121 #define ARM_LOCK_GET_INSTANCE (&arm_lock) 122 123 #if !HW_ASSISTED_COHERENCY 124 #define ARM_SCMI_INSTANTIATE_LOCK DEFINE_BAKERY_LOCK(arm_scmi_lock) 125 #else 126 #define ARM_SCMI_INSTANTIATE_LOCK spinlock_t arm_scmi_lock 127 #endif 128 #define ARM_SCMI_LOCK_GET_INSTANCE (&arm_scmi_lock) 129 130 /* 131 * These are wrapper macros to the Coherent Memory Bakery Lock API. 132 */ 133 #define arm_lock_init() bakery_lock_init(&arm_lock) 134 #define arm_lock_get() bakery_lock_get(&arm_lock) 135 #define arm_lock_release() bakery_lock_release(&arm_lock) 136 137 #else 138 139 /* 140 * Empty macros for all other BL stages other than BL31 and BL32 141 */ 142 #define ARM_INSTANTIATE_LOCK static int arm_lock __unused 143 #define ARM_LOCK_GET_INSTANCE 0 144 #define arm_lock_init() 145 #define arm_lock_get() 146 #define arm_lock_release() 147 148 #endif /* defined(IMAGE_BL31) || (!defined(__aarch64__) && defined(IMAGE_BL32)) */ 149 150 #ifdef __aarch64__ 151 #define TL_TAG_EXEC_EP_INFO TL_TAG_EXEC_EP_INFO64 152 #define TL_TAG_SRAM_LAYOUT TL_TAG_SRAM_LAYOUT64 153 #else 154 #define TL_TAG_EXEC_EP_INFO TL_TAG_EXEC_EP_INFO32 155 #define TL_TAG_SRAM_LAYOUT TL_TAG_SRAM_LAYOUT32 156 #endif 157 158 #if ARM_RECOM_STATE_ID_ENC 159 /* 160 * Macros used to parse state information from State-ID if it is using the 161 * recommended encoding for State-ID. 162 */ 163 #define ARM_LOCAL_PSTATE_WIDTH 4 164 #define ARM_LOCAL_PSTATE_MASK ((1 << ARM_LOCAL_PSTATE_WIDTH) - 1) 165 166 /* Last in Level for the OS-initiated */ 167 #define ARM_LAST_AT_PLVL_MASK (ARM_LOCAL_PSTATE_MASK << \ 168 (ARM_LOCAL_PSTATE_WIDTH * \ 169 (PLAT_MAX_PWR_LVL + 1))) 170 171 /* Macros to construct the composite power state */ 172 173 /* Make composite power state parameter till power level 0 */ 174 #if PSCI_EXTENDED_STATE_ID 175 176 #define arm_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \ 177 (((lvl0_state) << PSTATE_ID_SHIFT) | ((type) << PSTATE_TYPE_SHIFT)) 178 #else 179 #define arm_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \ 180 (((lvl0_state) << PSTATE_ID_SHIFT) | \ 181 ((pwr_lvl) << PSTATE_PWR_LVL_SHIFT) | \ 182 ((type) << PSTATE_TYPE_SHIFT)) 183 #endif /* __PSCI_EXTENDED_STATE_ID__ */ 184 185 /* Make composite power state parameter till power level 1 */ 186 #define arm_make_pwrstate_lvl1(lvl1_state, lvl0_state, pwr_lvl, type) \ 187 (((lvl1_state) << ARM_LOCAL_PSTATE_WIDTH) | \ 188 arm_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type)) 189 190 /* Make composite power state parameter till power level 2 */ 191 #define arm_make_pwrstate_lvl2(lvl2_state, lvl1_state, lvl0_state, pwr_lvl, type) \ 192 (((lvl2_state) << (ARM_LOCAL_PSTATE_WIDTH * 2)) | \ 193 arm_make_pwrstate_lvl1(lvl1_state, lvl0_state, pwr_lvl, type)) 194 195 #endif /* __ARM_RECOM_STATE_ID_ENC__ */ 196 197 /* ARM State switch error codes */ 198 #define STATE_SW_E_PARAM (-2) 199 #define STATE_SW_E_DENIED (-3) 200 201 /* plat_get_rotpk_info() flags */ 202 #define ARM_ROTPK_REGS_ID 1 203 #define ARM_ROTPK_DEVEL_RSA_ID 2 204 #define ARM_ROTPK_DEVEL_ECDSA_ID 3 205 #define ARM_ROTPK_DEVEL_FULL_DEV_RSA_KEY_ID 4 206 #define ARM_ROTPK_DEVEL_FULL_DEV_ECDSA_KEY_ID 5 207 208 #define ARM_USE_DEVEL_ROTPK \ 209 (ARM_ROTPK_LOCATION_ID == ARM_ROTPK_DEVEL_RSA_ID) || \ 210 (ARM_ROTPK_LOCATION_ID == ARM_ROTPK_DEVEL_ECDSA_ID) || \ 211 (ARM_ROTPK_LOCATION_ID == ARM_ROTPK_DEVEL_FULL_DEV_RSA_KEY_ID) || \ 212 (ARM_ROTPK_LOCATION_ID == ARM_ROTPK_DEVEL_FULL_DEV_ECDSA_KEY_ID) 213 214 /* IO storage utility functions */ 215 int arm_io_setup(void); 216 217 /* Set image specification in IO block policy */ 218 int arm_set_image_source(unsigned int image_id, const char *part_name, 219 uintptr_t *dev_handle, uintptr_t *image_spec); 220 void arm_set_fip_addr(uint32_t active_fw_bank_idx); 221 222 /* Security utility functions */ 223 void arm_tzc400_setup(uintptr_t tzc_base, 224 const arm_tzc_regions_info_t *tzc_regions); 225 struct tzc_dmc500_driver_data; 226 void arm_tzc_dmc500_setup(struct tzc_dmc500_driver_data *plat_driver_data, 227 const arm_tzc_regions_info_t *tzc_regions); 228 229 /* Console utility functions */ 230 void arm_console_boot_init(void); 231 void arm_console_boot_end(void); 232 void arm_console_runtime_init(void); 233 void arm_console_runtime_end(void); 234 235 /* Systimer utility function */ 236 void arm_configure_sys_timer(void); 237 238 /* PM utility functions */ 239 int arm_validate_power_state(unsigned int power_state, 240 psci_power_state_t *req_state); 241 int arm_validate_psci_entrypoint(uintptr_t entrypoint); 242 int arm_validate_ns_entrypoint(uintptr_t entrypoint); 243 void arm_system_pwr_domain_save(void); 244 void arm_system_pwr_domain_resume(void); 245 int arm_psci_read_mem_protect(int *enabled); 246 int arm_nor_psci_write_mem_protect(int val); 247 void arm_nor_psci_do_static_mem_protect(void); 248 void arm_nor_psci_do_dyn_mem_protect(void); 249 int arm_psci_mem_protect_chk(uintptr_t base, u_register_t length); 250 251 /* Topology utility function */ 252 int arm_check_mpidr(u_register_t mpidr); 253 254 /* BL1 utility functions */ 255 void arm_bl1_early_platform_setup(void); 256 void arm_bl1_platform_setup(void); 257 void arm_bl1_plat_arch_setup(void); 258 259 /* BL2 utility functions */ 260 void arm_bl2_early_platform_setup(u_register_t arg0, u_register_t arg1, 261 u_register_t arg2, u_register_t arg3); 262 void arm_bl2_platform_setup(void); 263 void arm_bl2_plat_arch_setup(void); 264 uint32_t arm_get_spsr_for_bl32_entry(void); 265 uint32_t arm_get_spsr_for_bl33_entry(void); 266 int arm_bl2_plat_handle_post_image_load(unsigned int image_id); 267 int arm_bl2_handle_post_image_load(unsigned int image_id); 268 struct bl_params *arm_get_next_bl_params(void); 269 void arm_bl2_setup_next_ep_info(bl_mem_params_node_t *next_param_node); 270 271 /* BL2 at EL3 functions */ 272 void arm_bl2_el3_early_platform_setup(void); 273 void arm_bl2_el3_plat_arch_setup(void); 274 #if ARM_FW_CONFIG_LOAD_ENABLE 275 void arm_bl2_el3_plat_config_load(void); 276 #endif /* ARM_FW_CONFIG_LOAD_ENABLE */ 277 278 /* BL2U utility functions */ 279 void arm_bl2u_early_platform_setup(struct meminfo *mem_layout, 280 void *plat_info); 281 void arm_bl2u_platform_setup(void); 282 void arm_bl2u_plat_arch_setup(void); 283 284 /* BL31 utility functions */ 285 void arm_bl31_early_platform_setup(u_register_t arg0, u_register_t arg1, 286 u_register_t arg2, u_register_t arg3); 287 void arm_bl31_platform_setup(void); 288 void arm_bl31_plat_runtime_setup(void); 289 void arm_bl31_plat_arch_setup(void); 290 291 /* Firmware Handoff utility functions */ 292 void arm_transfer_list_dyn_cfg_init(struct transfer_list_header *secure_tl); 293 void arm_transfer_list_populate_ep_info(bl_mem_params_node_t *next_param_node, 294 struct transfer_list_header *secure_tl); 295 void arm_transfer_list_copy_hw_config(struct transfer_list_header *secure_tl, 296 struct transfer_list_header *ns_tl); 297 struct transfer_list_entry * 298 arm_transfer_list_set_heap_info(struct transfer_list_header *tl); 299 void arm_transfer_list_get_heap_info(void **heap_addr, size_t *heap_size); 300 301 /* TSP utility functions */ 302 void arm_tsp_early_platform_setup(void); 303 304 /* SP_MIN utility functions */ 305 void arm_sp_min_early_platform_setup(u_register_t arg0, u_register_t arg1, 306 u_register_t arg2, u_register_t arg3); 307 void arm_sp_min_plat_runtime_setup(void); 308 void arm_sp_min_plat_arch_setup(void); 309 310 /* FIP TOC validity check */ 311 bool arm_io_is_toc_valid(void); 312 313 /* Utility functions for Dynamic Config */ 314 315 void arm_bl1_set_mbedtls_heap(void); 316 int arm_get_mbedtls_heap(void **heap_addr, size_t *heap_size); 317 318 #if IMAGE_BL2 319 void arm_bl2_dyn_cfg_init(void); 320 #endif /* IMAGE_BL2 */ 321 322 #if MEASURED_BOOT 323 #if DICE_PROTECTION_ENVIRONMENT 324 int arm_set_nt_fw_info(int *ctx_handle); 325 int arm_set_tb_fw_info(int *ctx_handle); 326 int arm_get_tb_fw_info(int *ctx_handle); 327 #else 328 /* Specific to event log backend */ 329 int arm_set_tos_fw_info(uintptr_t log_addr, size_t log_size); 330 int arm_set_nt_fw_info( 331 /* 332 * Currently OP-TEE does not support reading DTBs from Secure memory 333 * and this option should be removed when feature is supported. 334 */ 335 #ifdef SPD_opteed 336 uintptr_t log_addr, 337 #endif 338 size_t log_size, uintptr_t *ns_log_addr); 339 int arm_set_tb_fw_info(uintptr_t log_addr, size_t log_size, 340 size_t log_max_size); 341 int arm_get_tb_fw_info(uint64_t *log_addr, size_t *log_size, 342 size_t *log_max_size); 343 #endif /* DICE_PROTECTION_ENVIRONMENT */ 344 #endif /* MEASURED_BOOT */ 345 346 /* 347 * Free the memory storing initialization code only used during an images boot 348 * time so it can be reclaimed for runtime data 349 */ 350 void arm_free_init_memory(void); 351 352 /* 353 * Make the higher level translation tables read-only 354 */ 355 void arm_xlat_make_tables_readonly(void); 356 357 /* 358 * Mandatory functions required in ARM standard platforms 359 */ 360 unsigned int plat_arm_get_cluster_core_count(u_register_t mpidr); 361 void plat_arm_gic_driver_init(void); 362 void plat_arm_gic_init(void); 363 void plat_arm_gic_cpuif_enable(void); 364 void plat_arm_gic_cpuif_disable(void); 365 void plat_arm_gic_redistif_on(void); 366 void plat_arm_gic_redistif_off(void); 367 void plat_arm_gic_pcpu_init(void); 368 void plat_arm_gic_save(void); 369 void plat_arm_gic_resume(void); 370 void plat_arm_security_setup(void); 371 void plat_arm_pwrc_setup(void); 372 void plat_arm_interconnect_init(void); 373 void plat_arm_interconnect_enter_coherency(void); 374 void plat_arm_interconnect_exit_coherency(void); 375 void plat_arm_program_trusted_mailbox(uintptr_t address); 376 bool plat_arm_bl1_fwu_needed(void); 377 int plat_arm_ni_setup(uintptr_t global_cfg); 378 __dead2 void plat_arm_error_handler(int err); 379 __dead2 void plat_arm_system_reset(void); 380 381 /* 382 * Optional functions in ARM standard platforms 383 */ 384 void plat_arm_override_gicr_frames(const uintptr_t *plat_gicr_frames); 385 int arm_get_rotpk_info(void *cookie, void **key_ptr, unsigned int *key_len, 386 unsigned int *flags); 387 int arm_get_rotpk_info_regs(void **key_ptr, unsigned int *key_len, 388 unsigned int *flags); 389 int arm_get_rotpk_info_cc(void **key_ptr, unsigned int *key_len, 390 unsigned int *flags); 391 int arm_get_rotpk_info_dev(void **key_ptr, unsigned int *key_len, 392 unsigned int *flags); 393 394 #if ARM_PLAT_MT 395 unsigned int plat_arm_get_cpu_pe_count(u_register_t mpidr); 396 #endif 397 398 unsigned int plat_cluster_id_by_mpidr(u_register_t mpidr); 399 400 /* 401 * This function is called after loading SCP_BL2 image and it is used to perform 402 * any platform-specific actions required to handle the SCP firmware. 403 */ 404 int plat_arm_bl2_handle_scp_bl2(struct image_info *scp_bl2_image_info); 405 406 /* 407 * Optional functions required in ARM standard platforms 408 */ 409 void plat_arm_io_setup(void); 410 int plat_arm_get_alt_image_source( 411 unsigned int image_id, 412 uintptr_t *dev_handle, 413 uintptr_t *image_spec); 414 unsigned int plat_arm_calc_core_pos(u_register_t mpidr); 415 const mmap_region_t *plat_arm_get_mmap(void); 416 417 const arm_gpt_info_t *plat_arm_get_gpt_info(void); 418 void arm_gpt_setup(void); 419 420 /* Allow platform to override psci_pm_ops during runtime */ 421 const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops); 422 423 /* Execution state switch in ARM platforms */ 424 int arm_execution_state_switch(unsigned int smc_fid, 425 uint32_t pc_hi, 426 uint32_t pc_lo, 427 uint32_t cookie_hi, 428 uint32_t cookie_lo, 429 void *handle); 430 431 /* Optional functions for SP_MIN */ 432 void plat_arm_sp_min_early_platform_setup(u_register_t arg0, u_register_t arg1, 433 u_register_t arg2, u_register_t arg3); 434 435 /* global variables */ 436 extern plat_psci_ops_t plat_arm_psci_pm_ops; 437 extern const mmap_region_t plat_arm_mmap[]; 438 extern const unsigned int arm_pm_idle_states[]; 439 extern struct transfer_list_header *secure_tl; 440 441 /* secure watchdog */ 442 void plat_arm_secure_wdt_start(void); 443 void plat_arm_secure_wdt_stop(void); 444 void plat_arm_secure_wdt_refresh(void); 445 446 /* Get SOC-ID of ARM platform */ 447 uint32_t plat_arm_get_soc_id(void); 448 449 #endif /* PLAT_ARM_H */ 450