1# 2# Copyright (c) 2017-2022, ARM Limited and Contributors. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7# We don't use BL1 or BL2, so BL31 is the first image to execute 8RESET_TO_BL31 := 1 9# Only one core starts up at first 10COLD_BOOT_SINGLE_CPU := 1 11# We can choose where a core starts executing 12PROGRAMMABLE_RESET_ADDRESS:= 1 13 14# ARM coherency is managed in hardware 15WARMBOOT_ENABLE_DCACHE_EARLY := 1 16 17# A53 erratum for SoC. (enable them all) 18ERRATA_A53_826319 := 1 19ERRATA_A53_835769 := 1 20ERRATA_A53_836870 := 1 21ERRATA_A53_843419 := 1 22ERRATA_A53_855873 := 1 23ERRATA_A53_1530924 := 1 24 25# A72 Erratum for SoC 26ERRATA_A72_859971 := 1 27ERRATA_A72_1319367 := 1 28 29CRASH_REPORTING := 1 30 31NS_TIMER_SWITCH := 0 32 33# Split out RO data into a non-executable section 34SEPARATE_CODE_AND_RODATA := 1 35 36# Generate a Position Independent Executable 37ENABLE_PIE := 1 38 39TI_16550_MDR_QUIRK := 1 40$(eval $(call add_define,TI_16550_MDR_QUIRK)) 41 42K3_USART := 0 43$(eval $(call add_define,K3_USART)) 44 45# Allow customizing the UART baud rate 46K3_USART_BAUD := 115200 47$(eval $(call add_define,K3_USART_BAUD)) 48 49# Libraries 50include lib/xlat_tables_v2/xlat_tables.mk 51 52PLAT_INCLUDES += \ 53 -I${PLAT_PATH}/include \ 54 -Idrivers/ti/ti_sci \ 55 56K3_CONSOLE_SOURCES += \ 57 drivers/ti/uart/aarch64/16550_console.S \ 58 plat/ti/common/k3_console.c \ 59 60# Include GICv3 driver files 61include drivers/arm/gic/v3/gicv3.mk 62 63K3_GIC_SOURCES += \ 64 ${GICV3_SOURCES} \ 65 plat/common/plat_gicv3.c \ 66 plat/ti/common/k3_gicv3.c \ 67 68K3_PSCI_SOURCES += \ 69 plat/common/plat_psci_common.c \ 70 71 72K3_TI_SCI_SOURCES += \ 73 drivers/ti/ti_sci/ti_sci.c \ 74 75PLAT_BL_COMMON_SOURCES += \ 76 lib/cpus/aarch64/cortex_a53.S \ 77 lib/cpus/aarch64/cortex_a72.S \ 78 ${XLAT_TABLES_LIB_SRCS} \ 79 ${K3_CONSOLE_SOURCES} \ 80 81BL31_SOURCES += \ 82 plat/ti/common/ti_bl31_setup.c \ 83 plat/ti/common/k3_helpers.S \ 84 ${K3_GIC_SOURCES} \ 85 ${K3_TI_SCI_SOURCES} \ 86