1# 2# Copyright (c) 2023-2024, STMicroelectronics - All Rights Reserved 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7# Extra partitions used to find FIP, contains: 8# metadata (2) and fsbl-m (2) and the FIP partitions (default is 2). 9STM32_EXTRA_PARTS := 6 10 11include plat/st/common/common.mk 12 13CRASH_REPORTING := 1 14ENABLE_PIE := 1 15PROGRAMMABLE_RESET_ADDRESS := 1 16BL2_IN_XIP_MEM := 1 17 18STM32MP_BL33_EL1 ?= 1 19ifeq ($(STM32MP_BL33_EL1),1) 20INIT_UNUSED_NS_EL2 := 1 21endif 22 23# Disable features unsupported in ARMv8.0 24ENABLE_SPE_FOR_NS := 0 25ENABLE_SVE_FOR_NS := 0 26 27# Default Device tree 28DTB_FILE_NAME ?= stm32mp257f-ev1.dtb 29 30STM32MP25 := 1 31 32# STM32 image header version v2.2 33STM32_HEADER_VERSION_MAJOR := 2 34STM32_HEADER_VERSION_MINOR := 2 35 36# Set load address for serial boot devices 37DWL_BUFFER_BASE ?= 0x87000000 38 39# DDR types 40STM32MP_DDR3_TYPE ?= 0 41STM32MP_DDR4_TYPE ?= 0 42STM32MP_LPDDR4_TYPE ?= 0 43ifeq (${STM32MP_DDR3_TYPE},1) 44DDR_TYPE := ddr3 45endif 46ifeq (${STM32MP_DDR4_TYPE},1) 47DDR_TYPE := ddr4 48endif 49ifeq (${STM32MP_LPDDR4_TYPE},1) 50DDR_TYPE := lpddr4 51endif 52 53# DDR features 54STM32MP_DDR_DUAL_AXI_PORT := 1 55STM32MP_DDR_FIP_IO_STORAGE := 1 56 57# Device tree 58BL2_DTSI := stm32mp25-bl2.dtsi 59FDT_SOURCES := $(addprefix ${BUILD_PLAT}/fdts/, $(patsubst %.dtb,%-bl2.dts,$(DTB_FILE_NAME))) 60BL31_DTSI := stm32mp25-bl31.dtsi 61FDT_SOURCES += $(addprefix ${BUILD_PLAT}/fdts/, $(patsubst %.dtb,%-bl31.dts,$(DTB_FILE_NAME))) 62 63# Macros and rules to build TF binary 64STM32_TF_STM32 := $(addprefix ${BUILD_PLAT}/tf-a-, $(patsubst %.dtb,%.stm32,$(DTB_FILE_NAME))) 65STM32_LD_FILE := plat/st/stm32mp2/${ARCH}/stm32mp2.ld.S 66STM32_BINARY_MAPPING := plat/st/stm32mp2/${ARCH}/stm32mp2.S 67 68STM32MP_FW_CONFIG_NAME := $(patsubst %.dtb,%-fw-config.dtb,$(DTB_FILE_NAME)) 69STM32MP_FW_CONFIG := ${BUILD_PLAT}/fdts/$(STM32MP_FW_CONFIG_NAME) 70STM32MP_SOC_FW_CONFIG := $(addprefix ${BUILD_PLAT}/fdts/, $(patsubst %.dtb,%-bl31.dtb,$(DTB_FILE_NAME))) 71ifeq (${STM32MP_DDR_FIP_IO_STORAGE},1) 72STM32MP_DDR_FW_PATH ?= drivers/st/ddr/phy/firmware/bin/stm32mp2 73STM32MP_DDR_FW_NAME := ${DDR_TYPE}_pmu_train.bin 74STM32MP_DDR_FW := ${STM32MP_DDR_FW_PATH}/${STM32MP_DDR_FW_NAME} 75endif 76FDT_SOURCES += $(addprefix fdts/, $(patsubst %.dtb,%.dts,$(STM32MP_FW_CONFIG_NAME))) 77# Add the FW_CONFIG to FIP and specify the same to certtool 78$(eval $(call TOOL_ADD_PAYLOAD,${STM32MP_FW_CONFIG},--fw-config)) 79# Add the SOC_FW_CONFIG to FIP and specify the same to certtool 80$(eval $(call TOOL_ADD_IMG,STM32MP_SOC_FW_CONFIG,--soc-fw-config)) 81ifeq (${STM32MP_DDR_FIP_IO_STORAGE},1) 82# Add the FW_DDR to FIP and specify the same to certtool 83$(eval $(call TOOL_ADD_IMG,STM32MP_DDR_FW,--ddr-fw)) 84endif 85 86# Enable flags for C files 87$(eval $(call assert_booleans,\ 88 $(sort \ 89 STM32MP_DDR_DUAL_AXI_PORT \ 90 STM32MP_DDR_FIP_IO_STORAGE \ 91 STM32MP_DDR3_TYPE \ 92 STM32MP_DDR4_TYPE \ 93 STM32MP_LPDDR4_TYPE \ 94 STM32MP25 \ 95 STM32MP_BL33_EL1 \ 96))) 97 98$(eval $(call assert_numerics,\ 99 $(sort \ 100 PLAT_PARTITION_MAX_ENTRIES \ 101 STM32_HEADER_VERSION_MAJOR \ 102 STM32_TF_A_COPIES \ 103))) 104 105$(eval $(call add_defines,\ 106 $(sort \ 107 DWL_BUFFER_BASE \ 108 PLAT_DEF_FIP_UUID \ 109 PLAT_PARTITION_MAX_ENTRIES \ 110 PLAT_TBBR_IMG_DEF \ 111 STM32_TF_A_COPIES \ 112 STM32MP_DDR_DUAL_AXI_PORT \ 113 STM32MP_DDR_FIP_IO_STORAGE \ 114 STM32MP_DDR3_TYPE \ 115 STM32MP_DDR4_TYPE \ 116 STM32MP_LPDDR4_TYPE \ 117 STM32MP25 \ 118 STM32MP_BL33_EL1 \ 119))) 120 121# STM32MP2x is based on Cortex-A35, which is Armv8.0, and does not support BTI 122# Disable mbranch-protection to avoid adding useless code 123TF_CFLAGS += -mbranch-protection=none 124 125# Include paths and source files 126PLAT_INCLUDES += -Iplat/st/stm32mp2/include/ 127PLAT_INCLUDES += -Idrivers/st/ddr/phy/phyinit/include/ 128PLAT_INCLUDES += -Idrivers/st/ddr/phy/firmware/include/ 129 130PLAT_BL_COMMON_SOURCES += lib/cpus/${ARCH}/cortex_a35.S 131PLAT_BL_COMMON_SOURCES += drivers/st/uart/${ARCH}/stm32_console.S 132PLAT_BL_COMMON_SOURCES += plat/st/stm32mp2/${ARCH}/stm32mp2_helper.S 133 134PLAT_BL_COMMON_SOURCES += drivers/st/pmic/stm32mp_pmic2.c \ 135 drivers/st/pmic/stpmic2.c \ 136 137PLAT_BL_COMMON_SOURCES += drivers/st/i2c/stm32_i2c.c 138 139PLAT_BL_COMMON_SOURCES += plat/st/stm32mp2/stm32mp2_private.c 140 141PLAT_BL_COMMON_SOURCES += drivers/st/bsec/bsec3.c \ 142 drivers/st/reset/stm32mp2_reset.c \ 143 plat/st/stm32mp2/stm32mp2_syscfg.c 144 145PLAT_BL_COMMON_SOURCES += drivers/st/clk/clk-stm32-core.c \ 146 drivers/st/clk/clk-stm32mp2.c 147 148BL2_SOURCES += plat/st/stm32mp2/plat_bl2_mem_params_desc.c 149 150BL2_SOURCES += plat/st/stm32mp2/bl2_plat_setup.c \ 151 plat/st/stm32mp2/plat_ddr.c 152 153ifneq ($(filter 1,${STM32MP_EMMC} ${STM32MP_SDMMC}),) 154BL2_SOURCES += drivers/st/mmc/stm32_sdmmc2.c 155endif 156 157ifeq (${STM32MP_USB_PROGRAMMER},1) 158BL2_SOURCES += plat/st/stm32mp2/stm32mp2_usb_dfu.c 159endif 160 161BL2_SOURCES += drivers/st/ddr/stm32mp2_ddr.c \ 162 drivers/st/ddr/stm32mp2_ddr_helpers.c \ 163 drivers/st/ddr/stm32mp2_ram.c 164 165BL2_SOURCES += drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_c_initphyconfig.c \ 166 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_calcmb.c \ 167 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_i_loadpieimage.c \ 168 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_initstruct.c \ 169 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_isdbytedisabled.c \ 170 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_loadpieprodcode.c \ 171 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_mapdrvstren.c \ 172 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_progcsrskiptrain.c \ 173 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_reginterface.c \ 174 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_restore_sequence.c \ 175 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_sequence.c \ 176 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_softsetmb.c \ 177 drivers/st/ddr/phy/phyinit/usercustom/ddrphy_phyinit_usercustom_custompretrain.c \ 178 drivers/st/ddr/phy/phyinit/usercustom/ddrphy_phyinit_usercustom_saveretregs.c 179 180BL2_SOURCES += drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_d_loadimem.c \ 181 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_f_loaddmem.c \ 182 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_g_execfw.c \ 183 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_writeoutmem.c \ 184 drivers/st/ddr/phy/phyinit/usercustom/ddrphy_phyinit_usercustom_g_waitfwdone.c 185 186# BL31 sources 187BL31_SOURCES += ${FDT_WRAPPERS_SOURCES} 188 189BL31_SOURCES += plat/st/stm32mp2/bl31_plat_setup.c \ 190 plat/st/stm32mp2/stm32mp2_pm.c \ 191 plat/st/stm32mp2/stm32mp2_topology.c 192# Generic GIC v2 193include drivers/arm/gic/v2/gicv2.mk 194 195BL31_SOURCES += ${GICV2_SOURCES} \ 196 plat/common/plat_gicv2.c \ 197 plat/st/common/stm32mp_gic.c 198 199# Generic PSCI 200BL31_SOURCES += plat/common/plat_psci_common.c 201 202# Compilation rules 203.PHONY: check_ddr_type 204.SUFFIXES: 205 206bl2: check_ddr_type 207 208check_ddr_type: 209 $(eval DDR_TYPE = $(shell echo $$(($(STM32MP_DDR3_TYPE) + \ 210 $(STM32MP_DDR4_TYPE) + \ 211 $(STM32MP_LPDDR4_TYPE))))) 212 @if [ ${DDR_TYPE} != 1 ]; then \ 213 echo "One and only one DDR type must be defined"; \ 214 false; \ 215 fi 216 217# Create DTB file for BL31 218${BUILD_PLAT}/fdts/%-bl31.dts: fdts/%.dts fdts/${BL31_DTSI} | $$(@D)/ 219 @echo '#include "$(patsubst fdts/%,%,$<)"' > $@ 220 @echo '#include "${BL31_DTSI}"' >> $@ 221 222${BUILD_PLAT}/fdts/%-bl31.dtb: ${BUILD_PLAT}/fdts/%-bl31.dts 223 224include plat/st/common/common_rules.mk 225