1 /* 2 * Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2022, NVIDIA Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <assert.h> 9 #include <stdbool.h> 10 #include <string.h> 11 12 #include <platform_def.h> 13 14 #include <arch.h> 15 #include <arch_helpers.h> 16 #include <arch_features.h> 17 #include <bl31/interrupt_mgmt.h> 18 #include <common/bl_common.h> 19 #include <common/debug.h> 20 #include <context.h> 21 #include <drivers/arm/gicv3.h> 22 #include <lib/cpus/cpu_ops.h> 23 #include <lib/cpus/errata.h> 24 #include <lib/el3_runtime/context_mgmt.h> 25 #include <lib/el3_runtime/cpu_data.h> 26 #include <lib/el3_runtime/pubsub_events.h> 27 #include <lib/extensions/amu.h> 28 #include <lib/extensions/brbe.h> 29 #include <lib/extensions/debug_v8p9.h> 30 #include <lib/extensions/fgt2.h> 31 #include <lib/extensions/fpmr.h> 32 #include <lib/extensions/mpam.h> 33 #include <lib/extensions/pauth.h> 34 #include <lib/extensions/pmuv3.h> 35 #include <lib/extensions/sme.h> 36 #include <lib/extensions/spe.h> 37 #include <lib/extensions/sve.h> 38 #include <lib/extensions/sysreg128.h> 39 #include <lib/extensions/sys_reg_trace.h> 40 #include <lib/extensions/tcr2.h> 41 #include <lib/extensions/trbe.h> 42 #include <lib/extensions/trf.h> 43 #include <lib/utils.h> 44 45 #if ENABLE_FEAT_TWED 46 /* Make sure delay value fits within the range(0-15) */ 47 CASSERT(((TWED_DELAY & ~SCR_TWEDEL_MASK) == 0U), assert_twed_delay_value_check); 48 #endif /* ENABLE_FEAT_TWED */ 49 50 per_world_context_t per_world_context[CPU_DATA_CONTEXT_NUM]; 51 52 static void manage_extensions_nonsecure(cpu_context_t *ctx); 53 static void manage_extensions_secure(cpu_context_t *ctx); 54 55 #if ((IMAGE_BL1) || (IMAGE_BL31 && (!CTX_INCLUDE_EL2_REGS))) 56 static void setup_el1_context(cpu_context_t *ctx, const struct entry_point_info *ep) 57 { 58 u_register_t sctlr_elx, actlr_elx; 59 60 /* 61 * Initialise SCTLR_EL1 to the reset value corresponding to the target 62 * execution state setting all fields rather than relying on the hw. 63 * Some fields have architecturally UNKNOWN reset values and these are 64 * set to zero. 65 * 66 * SCTLR.EE: Endianness is taken from the entrypoint attributes. 67 * 68 * SCTLR.M, SCTLR.C and SCTLR.I: These fields must be zero (as 69 * required by PSCI specification) 70 */ 71 sctlr_elx = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0UL; 72 if (GET_RW(ep->spsr) == MODE_RW_64) { 73 sctlr_elx |= SCTLR_EL1_RES1; 74 } else { 75 /* 76 * If the target execution state is AArch32 then the following 77 * fields need to be set. 78 * 79 * SCTRL_EL1.nTWE: Set to one so that EL0 execution of WFE 80 * instructions are not trapped to EL1. 81 * 82 * SCTLR_EL1.nTWI: Set to one so that EL0 execution of WFI 83 * instructions are not trapped to EL1. 84 * 85 * SCTLR_EL1.CP15BEN: Set to one to enable EL0 execution of the 86 * CP15DMB, CP15DSB, and CP15ISB instructions. 87 */ 88 sctlr_elx |= SCTLR_AARCH32_EL1_RES1 | SCTLR_CP15BEN_BIT 89 | SCTLR_NTWI_BIT | SCTLR_NTWE_BIT; 90 } 91 92 /* 93 * If workaround of errata 764081 for Cortex-A75 is used then set 94 * SCTLR_EL1.IESB to enable Implicit Error Synchronization Barrier. 95 */ 96 if (errata_a75_764081_applies()) { 97 sctlr_elx |= SCTLR_IESB_BIT; 98 } 99 100 /* Store the initialised SCTLR_EL1 value in the cpu_context */ 101 write_ctx_sctlr_el1_reg_errata(ctx, sctlr_elx); 102 103 /* 104 * Base the context ACTLR_EL1 on the current value, as it is 105 * implementation defined. The context restore process will write 106 * the value from the context to the actual register and can cause 107 * problems for processor cores that don't expect certain bits to 108 * be zero. 109 */ 110 actlr_elx = read_actlr_el1(); 111 write_el1_ctx_common(get_el1_sysregs_ctx(ctx), actlr_el1, actlr_elx); 112 } 113 #endif /* (IMAGE_BL1) || (IMAGE_BL31 && (!CTX_INCLUDE_EL2_REGS)) */ 114 115 /****************************************************************************** 116 * This function performs initializations that are specific to SECURE state 117 * and updates the cpu context specified by 'ctx'. 118 *****************************************************************************/ 119 static void setup_secure_context(cpu_context_t *ctx, const struct entry_point_info *ep) 120 { 121 u_register_t scr_el3; 122 el3_state_t *state; 123 124 state = get_el3state_ctx(ctx); 125 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 126 127 #if defined(IMAGE_BL31) && !defined(SPD_spmd) 128 /* 129 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 130 * indicated by the interrupt routing model for BL31. 131 */ 132 scr_el3 |= get_scr_el3_from_routing_model(SECURE); 133 #endif 134 135 /* Allow access to Allocation Tags when FEAT_MTE2 is implemented and enabled. */ 136 if (is_feat_mte2_supported()) { 137 scr_el3 |= SCR_ATA_BIT; 138 } 139 140 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 141 142 /* 143 * Initialize EL1 context registers unless SPMC is running 144 * at S-EL2. 145 */ 146 #if (!SPMD_SPM_AT_SEL2) 147 setup_el1_context(ctx, ep); 148 #endif 149 150 manage_extensions_secure(ctx); 151 } 152 153 #if ENABLE_RME 154 /****************************************************************************** 155 * This function performs initializations that are specific to REALM state 156 * and updates the cpu context specified by 'ctx'. 157 *****************************************************************************/ 158 static void setup_realm_context(cpu_context_t *ctx, const struct entry_point_info *ep) 159 { 160 u_register_t scr_el3; 161 el3_state_t *state; 162 163 state = get_el3state_ctx(ctx); 164 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 165 166 scr_el3 |= SCR_NS_BIT | SCR_NSE_BIT; 167 168 /* CSV2 version 2 and above */ 169 if (is_feat_csv2_2_supported()) { 170 /* Enable access to the SCXTNUM_ELx registers. */ 171 scr_el3 |= SCR_EnSCXT_BIT; 172 } 173 174 if (is_feat_sctlr2_supported()) { 175 /* Set the SCTLR2En bit in SCR_EL3 to enable access to 176 * SCTLR2_ELx registers. 177 */ 178 scr_el3 |= SCR_SCTLR2En_BIT; 179 } 180 181 if (is_feat_d128_supported()) { 182 /* 183 * Set the D128En bit in SCR_EL3 to enable access to 128-bit 184 * versions of TTBR0_EL1, TTBR1_EL1, RCWMASK_EL1, RCWSMASK_EL1, 185 * PAR_EL1 and TTBR1_EL2, TTBR0_EL2 and VTTBR_EL2 registers. 186 */ 187 scr_el3 |= SCR_D128En_BIT; 188 } 189 190 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 191 192 if (is_feat_fgt2_supported()) { 193 fgt2_enable(ctx); 194 } 195 196 if (is_feat_debugv8p9_supported()) { 197 debugv8p9_extended_bp_wp_enable(ctx); 198 } 199 200 if (is_feat_brbe_supported()) { 201 brbe_enable(ctx); 202 } 203 204 } 205 #endif /* ENABLE_RME */ 206 207 /****************************************************************************** 208 * This function performs initializations that are specific to NON-SECURE state 209 * and updates the cpu context specified by 'ctx'. 210 *****************************************************************************/ 211 static void setup_ns_context(cpu_context_t *ctx, const struct entry_point_info *ep) 212 { 213 u_register_t scr_el3; 214 el3_state_t *state; 215 216 state = get_el3state_ctx(ctx); 217 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 218 219 /* SCR_NS: Set the NS bit */ 220 scr_el3 |= SCR_NS_BIT; 221 222 /* Allow access to Allocation Tags when FEAT_MTE2 is implemented and enabled. */ 223 if (is_feat_mte2_supported()) { 224 scr_el3 |= SCR_ATA_BIT; 225 } 226 227 /* 228 * Pointer Authentication feature, if present, is always enabled by 229 * default for Non secure lower exception levels. We do not have an 230 * explicit flag to set it. To prevent the leakage between the worlds 231 * during world switch, we enable it only for the non-secure world. 232 * 233 * CTX_INCLUDE_PAUTH_REGS flag, is explicitly used to enable for lower 234 * exception levels of secure and realm worlds. 235 * 236 * If the Secure/realm world wants to use pointer authentication, 237 * CTX_INCLUDE_PAUTH_REGS must be explicitly set to 1, in which case 238 * it will be enabled globally for all the contexts. 239 * 240 * SCR_EL3.API: Set to one to not trap any PAuth instructions at ELs 241 * other than EL3 242 * 243 * SCR_EL3.APK: Set to one to not trap any PAuth key values at ELs other 244 * than EL3 245 */ 246 if (!is_ctx_pauth_supported()) { 247 scr_el3 |= SCR_API_BIT | SCR_APK_BIT; 248 } 249 250 #if HANDLE_EA_EL3_FIRST_NS 251 /* SCR_EL3.EA: Route External Abort and SError Interrupt to EL3. */ 252 scr_el3 |= SCR_EA_BIT; 253 #endif 254 255 #if RAS_TRAP_NS_ERR_REC_ACCESS 256 /* 257 * SCR_EL3.TERR: Trap Error record accesses. Accesses to the RAS ERR 258 * and RAS ERX registers from EL1 and EL2(from any security state) 259 * are trapped to EL3. 260 * Set here to trap only for NS EL1/EL2 261 */ 262 scr_el3 |= SCR_TERR_BIT; 263 #endif 264 265 /* CSV2 version 2 and above */ 266 if (is_feat_csv2_2_supported()) { 267 /* Enable access to the SCXTNUM_ELx registers. */ 268 scr_el3 |= SCR_EnSCXT_BIT; 269 } 270 271 #ifdef IMAGE_BL31 272 /* 273 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as 274 * indicated by the interrupt routing model for BL31. 275 */ 276 scr_el3 |= get_scr_el3_from_routing_model(NON_SECURE); 277 #endif 278 279 if (is_feat_the_supported()) { 280 /* Set the RCWMASKEn bit in SCR_EL3 to enable access to 281 * RCWMASK_EL1 and RCWSMASK_EL1 registers. 282 */ 283 scr_el3 |= SCR_RCWMASKEn_BIT; 284 } 285 286 if (is_feat_sctlr2_supported()) { 287 /* Set the SCTLR2En bit in SCR_EL3 to enable access to 288 * SCTLR2_ELx registers. 289 */ 290 scr_el3 |= SCR_SCTLR2En_BIT; 291 } 292 293 if (is_feat_d128_supported()) { 294 /* Set the D128En bit in SCR_EL3 to enable access to 128-bit 295 * versions of TTBR0_EL1, TTBR1_EL1, RCWMASK_EL1, RCWSMASK_EL1, 296 * PAR_EL1 and TTBR1_EL2, TTBR0_EL2 and VTTBR_EL2 registers. 297 */ 298 scr_el3 |= SCR_D128En_BIT; 299 } 300 301 if (is_feat_fpmr_supported()) { 302 /* Set the EnFPM bit in SCR_EL3 to enable access to FPMR 303 * register. 304 */ 305 scr_el3 |= SCR_EnFPM_BIT; 306 } 307 308 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 309 310 /* Initialize EL2 context registers */ 311 #if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) 312 313 /* 314 * Initialize SCTLR_EL2 context register with reset value. 315 */ 316 write_el2_ctx_common(get_el2_sysregs_ctx(ctx), sctlr_el2, SCTLR_EL2_RES1); 317 318 if (is_feat_hcx_supported()) { 319 /* 320 * Initialize register HCRX_EL2 with its init value. 321 * As the value of HCRX_EL2 is UNKNOWN on reset, there is a 322 * chance that this can lead to unexpected behavior in lower 323 * ELs that have not been updated since the introduction of 324 * this feature if not properly initialized, especially when 325 * it comes to those bits that enable/disable traps. 326 */ 327 write_el2_ctx_hcx(get_el2_sysregs_ctx(ctx), hcrx_el2, 328 HCRX_EL2_INIT_VAL); 329 } 330 331 if (is_feat_fgt_supported()) { 332 /* 333 * Initialize HFG*_EL2 registers with a default value so legacy 334 * systems unaware of FEAT_FGT do not get trapped due to their lack 335 * of initialization for this feature. 336 */ 337 write_el2_ctx_fgt(get_el2_sysregs_ctx(ctx), hfgitr_el2, 338 HFGITR_EL2_INIT_VAL); 339 write_el2_ctx_fgt(get_el2_sysregs_ctx(ctx), hfgrtr_el2, 340 HFGRTR_EL2_INIT_VAL); 341 write_el2_ctx_fgt(get_el2_sysregs_ctx(ctx), hfgwtr_el2, 342 HFGWTR_EL2_INIT_VAL); 343 } 344 #else 345 /* Initialize EL1 context registers */ 346 setup_el1_context(ctx, ep); 347 #endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */ 348 349 manage_extensions_nonsecure(ctx); 350 } 351 352 /******************************************************************************* 353 * The following function performs initialization of the cpu_context 'ctx' 354 * for first use that is common to all security states, and sets the 355 * initial entrypoint state as specified by the entry_point_info structure. 356 * 357 * The EE and ST attributes are used to configure the endianness and secure 358 * timer availability for the new execution context. 359 ******************************************************************************/ 360 static void setup_context_common(cpu_context_t *ctx, const entry_point_info_t *ep) 361 { 362 u_register_t scr_el3; 363 u_register_t mdcr_el3; 364 el3_state_t *state; 365 gp_regs_t *gp_regs; 366 367 state = get_el3state_ctx(ctx); 368 369 /* Clear any residual register values from the context */ 370 zeromem(ctx, sizeof(*ctx)); 371 372 /* 373 * The lower-EL context is zeroed so that no stale values leak to a world. 374 * It is assumed that an all-zero lower-EL context is good enough for it 375 * to boot correctly. However, there are very few registers where this 376 * is not true and some values need to be recreated. 377 */ 378 #if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) 379 el2_sysregs_t *el2_ctx = get_el2_sysregs_ctx(ctx); 380 381 /* 382 * These bits are set in the gicv3 driver. Losing them (especially the 383 * SRE bit) is problematic for all worlds. Henceforth recreate them. 384 */ 385 u_register_t icc_sre_el2_val = ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT | 386 ICC_SRE_EN_BIT | ICC_SRE_SRE_BIT; 387 write_el2_ctx_common(el2_ctx, icc_sre_el2, icc_sre_el2_val); 388 389 /* 390 * The actlr_el2 register can be initialized in platform's reset handler 391 * and it may contain access control bits (e.g. CLUSTERPMUEN bit). 392 */ 393 write_el2_ctx_common(el2_ctx, actlr_el2, read_actlr_el2()); 394 #endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */ 395 396 /* Start with a clean SCR_EL3 copy as all relevant values are set */ 397 scr_el3 = SCR_RESET_VAL; 398 399 /* 400 * SCR_EL3.TWE: Set to zero so that execution of WFE instructions at 401 * EL2, EL1 and EL0 are not trapped to EL3. 402 * 403 * SCR_EL3.TWI: Set to zero so that execution of WFI instructions at 404 * EL2, EL1 and EL0 are not trapped to EL3. 405 * 406 * SCR_EL3.SMD: Set to zero to enable SMC calls at EL1 and above, from 407 * both Security states and both Execution states. 408 * 409 * SCR_EL3.SIF: Set to one to disable secure instruction execution from 410 * Non-secure memory. 411 */ 412 scr_el3 &= ~(SCR_TWE_BIT | SCR_TWI_BIT | SCR_SMD_BIT); 413 414 scr_el3 |= SCR_SIF_BIT; 415 416 /* 417 * SCR_EL3.RW: Set the execution state, AArch32 or AArch64, for next 418 * Exception level as specified by SPSR. 419 */ 420 if (GET_RW(ep->spsr) == MODE_RW_64) { 421 scr_el3 |= SCR_RW_BIT; 422 } 423 424 /* 425 * SCR_EL3.ST: Traps Secure EL1 accesses to the Counter-timer Physical 426 * Secure timer registers to EL3, from AArch64 state only, if specified 427 * by the entrypoint attributes. If SEL2 is present and enabled, the ST 428 * bit always behaves as 1 (i.e. secure physical timer register access 429 * is not trapped) 430 */ 431 if (EP_GET_ST(ep->h.attr) != 0U) { 432 scr_el3 |= SCR_ST_BIT; 433 } 434 435 /* 436 * If FEAT_HCX is enabled, enable access to HCRX_EL2 by setting 437 * SCR_EL3.HXEn. 438 */ 439 if (is_feat_hcx_supported()) { 440 scr_el3 |= SCR_HXEn_BIT; 441 } 442 443 /* 444 * If FEAT_LS64_ACCDATA is enabled, enable access to ACCDATA_EL1 by 445 * setting SCR_EL3.ADEn and allow the ST64BV0 instruction by setting 446 * SCR_EL3.EnAS0. 447 */ 448 if (is_feat_ls64_accdata_supported()) { 449 scr_el3 |= SCR_ADEn_BIT | SCR_EnAS0_BIT; 450 } 451 452 /* 453 * If FEAT_RNG_TRAP is enabled, all reads of the RNDR and RNDRRS 454 * registers are trapped to EL3. 455 */ 456 if (is_feat_rng_trap_supported()) { 457 scr_el3 |= SCR_TRNDR_BIT; 458 } 459 460 #if FAULT_INJECTION_SUPPORT 461 /* Enable fault injection from lower ELs */ 462 scr_el3 |= SCR_FIEN_BIT; 463 #endif 464 465 /* 466 * Enable Pointer Authentication globally for all the worlds. 467 * 468 * SCR_EL3.API: Set to one to not trap any PAuth instructions at ELs 469 * other than EL3 470 * 471 * SCR_EL3.APK: Set to one to not trap any PAuth key values at ELs other 472 * than EL3 473 */ 474 if (is_ctx_pauth_supported()) { 475 scr_el3 |= SCR_API_BIT | SCR_APK_BIT; 476 } 477 478 /* 479 * SCR_EL3.PIEN: Enable permission indirection and overlay 480 * registers for AArch64 if present. 481 */ 482 if (is_feat_sxpie_supported() || is_feat_sxpoe_supported()) { 483 scr_el3 |= SCR_PIEN_BIT; 484 } 485 486 /* 487 * SCR_EL3.GCSEn: Enable GCS registers for AArch64 if present. 488 */ 489 if ((is_feat_gcs_supported()) && (GET_RW(ep->spsr) == MODE_RW_64)) { 490 scr_el3 |= SCR_GCSEn_BIT; 491 } 492 493 /* 494 * SCR_EL3.HCE: Enable HVC instructions if next execution state is 495 * AArch64 and next EL is EL2, or if next execution state is AArch32 and 496 * next mode is Hyp. 497 * SCR_EL3.FGTEn: Enable Fine Grained Virtualization Traps under the 498 * same conditions as HVC instructions and when the processor supports 499 * ARMv8.6-FGT. 500 * SCR_EL3.ECVEn: Enable Enhanced Counter Virtualization (ECV) 501 * CNTPOFF_EL2 register under the same conditions as HVC instructions 502 * and when the processor supports ECV. 503 */ 504 if (((GET_RW(ep->spsr) == MODE_RW_64) && (GET_EL(ep->spsr) == MODE_EL2)) 505 || ((GET_RW(ep->spsr) != MODE_RW_64) 506 && (GET_M32(ep->spsr) == MODE32_hyp))) { 507 scr_el3 |= SCR_HCE_BIT; 508 509 if (is_feat_fgt_supported()) { 510 scr_el3 |= SCR_FGTEN_BIT; 511 } 512 513 if (is_feat_ecv_supported()) { 514 scr_el3 |= SCR_ECVEN_BIT; 515 } 516 } 517 518 /* Enable WFE trap delay in SCR_EL3 if supported and configured */ 519 if (is_feat_twed_supported()) { 520 /* Set delay in SCR_EL3 */ 521 scr_el3 &= ~(SCR_TWEDEL_MASK << SCR_TWEDEL_SHIFT); 522 scr_el3 |= ((TWED_DELAY & SCR_TWEDEL_MASK) 523 << SCR_TWEDEL_SHIFT); 524 525 /* Enable WFE delay */ 526 scr_el3 |= SCR_TWEDEn_BIT; 527 } 528 529 #if IMAGE_BL31 && defined(SPD_spmd) && SPMD_SPM_AT_SEL2 530 /* Enable S-EL2 if FEAT_SEL2 is implemented for all the contexts. */ 531 if (is_feat_sel2_supported()) { 532 scr_el3 |= SCR_EEL2_BIT; 533 } 534 #endif /* (IMAGE_BL31 && defined(SPD_spmd) && SPMD_SPM_AT_SEL2) */ 535 536 if (is_feat_mec_supported()) { 537 scr_el3 |= SCR_MECEn_BIT; 538 } 539 540 /* 541 * Populate EL3 state so that we've the right context 542 * before doing ERET 543 */ 544 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 545 write_ctx_reg(state, CTX_ELR_EL3, ep->pc); 546 write_ctx_reg(state, CTX_SPSR_EL3, ep->spsr); 547 548 /* Start with a clean MDCR_EL3 copy as all relevant values are set */ 549 mdcr_el3 = MDCR_EL3_RESET_VAL; 550 551 /* --------------------------------------------------------------------- 552 * Initialise MDCR_EL3, setting all fields rather than relying on hw. 553 * Some fields are architecturally UNKNOWN on reset. 554 * 555 * MDCR_EL3.SDD: Set to one to disable AArch64 Secure self-hosted debug. 556 * Debug exceptions, other than Breakpoint Instruction exceptions, are 557 * disabled from all ELs in Secure state. 558 * 559 * MDCR_EL3.SPD32: Set to 0b10 to disable AArch32 Secure self-hosted 560 * privileged debug from S-EL1. 561 * 562 * MDCR_EL3.TDOSA: Set to zero so that EL2 and EL2 System register 563 * access to the powerdown debug registers do not trap to EL3. 564 * 565 * MDCR_EL3.TDA: Set to zero to allow EL0, EL1 and EL2 access to the 566 * debug registers, other than those registers that are controlled by 567 * MDCR_EL3.TDOSA. 568 */ 569 mdcr_el3 |= ((MDCR_SDD_BIT | MDCR_SPD32(MDCR_SPD32_DISABLE)) 570 & ~(MDCR_TDA_BIT | MDCR_TDOSA_BIT)) ; 571 write_ctx_reg(state, CTX_MDCR_EL3, mdcr_el3); 572 573 #if IMAGE_BL31 574 /* Enable FEAT_TRF for Non-Secure and prohibit for Secure state. */ 575 if (is_feat_trf_supported()) { 576 trf_enable(ctx); 577 } 578 579 if (is_feat_tcr2_supported()) { 580 tcr2_enable(ctx); 581 } 582 583 pmuv3_enable(ctx); 584 #endif /* IMAGE_BL31 */ 585 586 /* 587 * Store the X0-X7 value from the entrypoint into the context 588 * Use memcpy as we are in control of the layout of the structures 589 */ 590 gp_regs = get_gpregs_ctx(ctx); 591 memcpy(gp_regs, (void *)&ep->args, sizeof(aapcs64_params_t)); 592 } 593 594 /******************************************************************************* 595 * Context management library initialization routine. This library is used by 596 * runtime services to share pointers to 'cpu_context' structures for secure 597 * non-secure and realm states. Management of the structures and their associated 598 * memory is not done by the context management library e.g. the PSCI service 599 * manages the cpu context used for entry from and exit to the non-secure state. 600 * The Secure payload dispatcher service manages the context(s) corresponding to 601 * the secure state. It also uses this library to get access to the non-secure 602 * state cpu context pointers. 603 * Lastly, this library provides the API to make SP_EL3 point to the cpu context 604 * which will be used for programming an entry into a lower EL. The same context 605 * will be used to save state upon exception entry from that EL. 606 ******************************************************************************/ 607 void __init cm_init(void) 608 { 609 /* 610 * The context management library has only global data to initialize, but 611 * that will be done when the BSS is zeroed out. 612 */ 613 } 614 615 /******************************************************************************* 616 * This is the high-level function used to initialize the cpu_context 'ctx' for 617 * first use. It performs initializations that are common to all security states 618 * and initializations specific to the security state specified in 'ep' 619 ******************************************************************************/ 620 void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep) 621 { 622 size_t security_state; 623 624 assert(ctx != NULL); 625 626 /* 627 * Perform initializations that are common 628 * to all security states 629 */ 630 setup_context_common(ctx, ep); 631 632 security_state = GET_SECURITY_STATE(ep->h.attr); 633 634 /* Perform security state specific initializations */ 635 switch (security_state) { 636 case SECURE: 637 setup_secure_context(ctx, ep); 638 break; 639 #if ENABLE_RME 640 case REALM: 641 setup_realm_context(ctx, ep); 642 break; 643 #endif 644 case NON_SECURE: 645 setup_ns_context(ctx, ep); 646 break; 647 default: 648 ERROR("Invalid security state\n"); 649 panic(); 650 break; 651 } 652 } 653 654 /******************************************************************************* 655 * Enable architecture extensions for EL3 execution. This function only updates 656 * registers in-place which are expected to either never change or be 657 * overwritten by el3_exit. Expects the core_pos of the current core as argument. 658 ******************************************************************************/ 659 #if IMAGE_BL31 660 void cm_manage_extensions_el3(unsigned int my_idx) 661 { 662 if (is_feat_sve_supported()) { 663 sve_init_el3(); 664 } 665 666 if (is_feat_amu_supported()) { 667 amu_init_el3(my_idx); 668 } 669 670 if (is_feat_sme_supported()) { 671 sme_init_el3(); 672 } 673 674 pmuv3_init_el3(); 675 } 676 677 /****************************************************************************** 678 * Function to initialise the registers with the RESET values in the context 679 * memory, which are maintained per world. 680 ******************************************************************************/ 681 static void cm_el3_arch_init_per_world(per_world_context_t *per_world_ctx) 682 { 683 /* 684 * Initialise CPTR_EL3, setting all fields rather than relying on hw. 685 * 686 * CPTR_EL3.TFP: Set to zero so that accesses to the V- or Z- registers 687 * by Advanced SIMD, floating-point or SVE instructions (if 688 * implemented) do not trap to EL3. 689 * 690 * CPTR_EL3.TCPAC: Set to zero so that accesses to CPACR_EL1, 691 * CPTR_EL2,CPACR, or HCPTR do not trap to EL3. 692 */ 693 uint64_t cptr_el3 = CPTR_EL3_RESET_VAL & ~(TCPAC_BIT | TFP_BIT); 694 695 per_world_ctx->ctx_cptr_el3 = cptr_el3; 696 697 /* 698 * Initialize MPAM3_EL3 to its default reset value 699 * 700 * MPAM3_EL3_RESET_VAL sets the MPAM3_EL3.TRAPLOWER bit that forces 701 * all lower ELn MPAM3_EL3 register access to, trap to EL3 702 */ 703 704 per_world_ctx->ctx_mpam3_el3 = MPAM3_EL3_RESET_VAL; 705 } 706 707 /******************************************************************************* 708 * Initialise per_world_context for Non-Secure world. 709 * This function enables the architecture extensions, which have same value 710 * across the cores for the non-secure world. 711 ******************************************************************************/ 712 static void manage_extensions_nonsecure_per_world(void) 713 { 714 cm_el3_arch_init_per_world(&per_world_context[CPU_CONTEXT_NS]); 715 716 if (is_feat_sme_supported()) { 717 sme_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 718 } 719 720 if (is_feat_sve_supported()) { 721 sve_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 722 } 723 724 if (is_feat_amu_supported()) { 725 amu_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 726 } 727 728 if (is_feat_sys_reg_trace_supported()) { 729 sys_reg_trace_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 730 } 731 732 if (is_feat_mpam_supported()) { 733 mpam_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 734 } 735 736 if (is_feat_fpmr_supported()) { 737 fpmr_enable_per_world(&per_world_context[CPU_CONTEXT_NS]); 738 } 739 } 740 741 /******************************************************************************* 742 * Initialise per_world_context for Secure world. 743 * This function enables the architecture extensions, which have same value 744 * across the cores for the secure world. 745 ******************************************************************************/ 746 static void manage_extensions_secure_per_world(void) 747 { 748 cm_el3_arch_init_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 749 750 if (is_feat_sme_supported()) { 751 752 if (ENABLE_SME_FOR_SWD) { 753 /* 754 * Enable SME, SVE, FPU/SIMD in secure context, SPM must ensure 755 * SME, SVE, and FPU/SIMD context properly managed. 756 */ 757 sme_enable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 758 } else { 759 /* 760 * Disable SME, SVE, FPU/SIMD in secure context so non-secure 761 * world can safely use the associated registers. 762 */ 763 sme_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 764 } 765 } 766 if (is_feat_sve_supported()) { 767 if (ENABLE_SVE_FOR_SWD) { 768 /* 769 * Enable SVE and FPU in secure context, SPM must ensure 770 * that the SVE and FPU register contexts are properly managed. 771 */ 772 sve_enable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 773 } else { 774 /* 775 * Disable SVE and FPU in secure context so non-secure world 776 * can safely use them. 777 */ 778 sve_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 779 } 780 } 781 782 /* NS can access this but Secure shouldn't */ 783 if (is_feat_sys_reg_trace_supported()) { 784 sys_reg_trace_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]); 785 } 786 } 787 788 static void manage_extensions_realm_per_world(void) 789 { 790 #if ENABLE_RME 791 cm_el3_arch_init_per_world(&per_world_context[CPU_CONTEXT_REALM]); 792 793 if (is_feat_sve_supported()) { 794 /* 795 * Enable SVE and FPU in realm context when it is enabled for NS. 796 * Realm manager must ensure that the SVE and FPU register 797 * contexts are properly managed. 798 */ 799 sve_enable_per_world(&per_world_context[CPU_CONTEXT_REALM]); 800 } 801 802 /* NS can access this but Realm shouldn't */ 803 if (is_feat_sys_reg_trace_supported()) { 804 sys_reg_trace_disable_per_world(&per_world_context[CPU_CONTEXT_REALM]); 805 } 806 807 /* 808 * If SME/SME2 is supported and enabled for NS world, then disable trapping 809 * of SME instructions for Realm world. RMM will save/restore required 810 * registers that are shared with SVE/FPU so that Realm can use FPU or SVE. 811 */ 812 if (is_feat_sme_supported()) { 813 sme_enable_per_world(&per_world_context[CPU_CONTEXT_REALM]); 814 } 815 816 /* 817 * If FEAT_MPAM is supported and enabled, then disable trapping access 818 * to the MPAM registers for Realm world. Instead, RMM will configure 819 * the access to be trapped by itself so it can inject undefined aborts 820 * back to the Realm. 821 */ 822 if (is_feat_mpam_supported()) { 823 mpam_enable_per_world(&per_world_context[CPU_CONTEXT_REALM]); 824 } 825 #endif /* ENABLE_RME */ 826 } 827 828 void cm_manage_extensions_per_world(void) 829 { 830 manage_extensions_nonsecure_per_world(); 831 manage_extensions_secure_per_world(); 832 manage_extensions_realm_per_world(); 833 } 834 #endif /* IMAGE_BL31 */ 835 836 /******************************************************************************* 837 * Enable architecture extensions on first entry to Non-secure world. 838 ******************************************************************************/ 839 static void manage_extensions_nonsecure(cpu_context_t *ctx) 840 { 841 #if IMAGE_BL31 842 /* NOTE: registers are not context switched */ 843 if (is_feat_amu_supported()) { 844 amu_enable(ctx); 845 } 846 847 if (is_feat_sme_supported()) { 848 sme_enable(ctx); 849 } 850 851 if (is_feat_fgt2_supported()) { 852 fgt2_enable(ctx); 853 } 854 855 if (is_feat_debugv8p9_supported()) { 856 debugv8p9_extended_bp_wp_enable(ctx); 857 } 858 859 /* 860 * SPE, TRBE, and BRBE have multi-field enables that affect which world 861 * they apply to. Despite this, it is useful to ignore these for 862 * simplicity in determining the feature's per world enablement status. 863 * This is only possible when context is written per-world. Relied on 864 * by SMCCC_ARCH_FEATURE_AVAILABILITY 865 */ 866 if (is_feat_spe_supported()) { 867 spe_enable(ctx); 868 } 869 870 if (!check_if_trbe_disable_affected_core()) { 871 if (is_feat_trbe_supported()) { 872 trbe_enable(ctx); 873 } 874 } 875 876 if (is_feat_brbe_supported()) { 877 brbe_enable(ctx); 878 } 879 #endif /* IMAGE_BL31 */ 880 } 881 882 #if INIT_UNUSED_NS_EL2 883 /******************************************************************************* 884 * Enable architecture extensions in-place at EL2 on first entry to Non-secure 885 * world when EL2 is empty and unused. 886 ******************************************************************************/ 887 static void manage_extensions_nonsecure_el2_unused(void) 888 { 889 #if IMAGE_BL31 890 if (is_feat_spe_supported()) { 891 spe_init_el2_unused(); 892 } 893 894 if (is_feat_amu_supported()) { 895 amu_init_el2_unused(); 896 } 897 898 if (is_feat_mpam_supported()) { 899 mpam_init_el2_unused(); 900 } 901 902 if (is_feat_trbe_supported()) { 903 trbe_init_el2_unused(); 904 } 905 906 if (is_feat_sys_reg_trace_supported()) { 907 sys_reg_trace_init_el2_unused(); 908 } 909 910 if (is_feat_trf_supported()) { 911 trf_init_el2_unused(); 912 } 913 914 pmuv3_init_el2_unused(); 915 916 if (is_feat_sve_supported()) { 917 sve_init_el2_unused(); 918 } 919 920 if (is_feat_sme_supported()) { 921 sme_init_el2_unused(); 922 } 923 924 if (is_feat_mops_supported() && is_feat_hcx_supported()) { 925 write_hcrx_el2(read_hcrx_el2() | HCRX_EL2_MSCEn_BIT); 926 } 927 928 if (is_feat_pauth_supported()) { 929 pauth_enable_el2(); 930 } 931 #endif /* IMAGE_BL31 */ 932 } 933 #endif /* INIT_UNUSED_NS_EL2 */ 934 935 /******************************************************************************* 936 * Enable architecture extensions on first entry to Secure world. 937 ******************************************************************************/ 938 static void manage_extensions_secure(cpu_context_t *ctx) 939 { 940 #if IMAGE_BL31 941 if (is_feat_sme_supported()) { 942 if (ENABLE_SME_FOR_SWD) { 943 /* 944 * Enable SME, SVE, FPU/SIMD in secure context, secure manager 945 * must ensure SME, SVE, and FPU/SIMD context properly managed. 946 */ 947 sme_init_el3(); 948 sme_enable(ctx); 949 } else { 950 /* 951 * Disable SME, SVE, FPU/SIMD in secure context so non-secure 952 * world can safely use the associated registers. 953 */ 954 sme_disable(ctx); 955 } 956 } 957 958 /* 959 * SPE and TRBE cannot be fully disabled from EL3 registers alone, only 960 * sysreg access can. In case the EL1 controls leave them active on 961 * context switch, we want the owning security state to be NS so Secure 962 * can't be DOSed. 963 */ 964 if (is_feat_spe_supported()) { 965 spe_disable(ctx); 966 } 967 968 if (is_feat_trbe_supported()) { 969 trbe_disable(ctx); 970 } 971 #endif /* IMAGE_BL31 */ 972 } 973 974 /******************************************************************************* 975 * The following function initializes the cpu_context for the current CPU 976 * for first use, and sets the initial entrypoint state as specified by the 977 * entry_point_info structure. 978 ******************************************************************************/ 979 void cm_init_my_context(const entry_point_info_t *ep) 980 { 981 cpu_context_t *ctx; 982 ctx = cm_get_context(GET_SECURITY_STATE(ep->h.attr)); 983 cm_setup_context(ctx, ep); 984 } 985 986 /* EL2 present but unused, need to disable safely. SCTLR_EL2 can be ignored */ 987 static void init_nonsecure_el2_unused(cpu_context_t *ctx) 988 { 989 #if INIT_UNUSED_NS_EL2 990 u_register_t hcr_el2 = HCR_RESET_VAL; 991 u_register_t mdcr_el2; 992 u_register_t scr_el3; 993 994 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3); 995 996 /* Set EL2 register width: Set HCR_EL2.RW to match SCR_EL3.RW */ 997 if ((scr_el3 & SCR_RW_BIT) != 0U) { 998 hcr_el2 |= HCR_RW_BIT; 999 } 1000 1001 write_hcr_el2(hcr_el2); 1002 1003 /* 1004 * Initialise CPTR_EL2 setting all fields rather than relying on the hw. 1005 * All fields have architecturally UNKNOWN reset values. 1006 */ 1007 write_cptr_el2(CPTR_EL2_RESET_VAL); 1008 1009 /* 1010 * Initialise CNTHCTL_EL2. All fields are architecturally UNKNOWN on 1011 * reset and are set to zero except for field(s) listed below. 1012 * 1013 * CNTHCTL_EL2.EL1PTEN: Set to one to disable traps to Hyp mode of 1014 * Non-secure EL0 and EL1 accesses to the physical timer registers. 1015 * 1016 * CNTHCTL_EL2.EL1PCTEN: Set to one to disable traps to Hyp mode of 1017 * Non-secure EL0 and EL1 accesses to the physical counter registers. 1018 */ 1019 write_cnthctl_el2(CNTHCTL_RESET_VAL | EL1PCEN_BIT | EL1PCTEN_BIT); 1020 1021 /* 1022 * Initialise CNTVOFF_EL2 to zero as it resets to an architecturally 1023 * UNKNOWN value. 1024 */ 1025 write_cntvoff_el2(0); 1026 1027 /* 1028 * Set VPIDR_EL2 and VMPIDR_EL2 to match MIDR_EL1 and MPIDR_EL1 1029 * respectively. 1030 */ 1031 write_vpidr_el2(read_midr_el1()); 1032 write_vmpidr_el2(read_mpidr_el1()); 1033 1034 /* 1035 * Initialise VTTBR_EL2. All fields are architecturally UNKNOWN on reset. 1036 * 1037 * VTTBR_EL2.VMID: Set to zero. Even though EL1&0 stage 2 address 1038 * translation is disabled, cache maintenance operations depend on the 1039 * VMID. 1040 * 1041 * VTTBR_EL2.BADDR: Set to zero as EL1&0 stage 2 address translation is 1042 * disabled. 1043 */ 1044 write_vttbr_el2(VTTBR_RESET_VAL & 1045 ~((VTTBR_VMID_MASK << VTTBR_VMID_SHIFT) | 1046 (VTTBR_BADDR_MASK << VTTBR_BADDR_SHIFT))); 1047 1048 /* 1049 * Initialise MDCR_EL2, setting all fields rather than relying on hw. 1050 * Some fields are architecturally UNKNOWN on reset. 1051 * 1052 * MDCR_EL2.TDRA: Set to zero so that Non-secure EL0 and EL1 System 1053 * register accesses to the Debug ROM registers are not trapped to EL2. 1054 * 1055 * MDCR_EL2.TDOSA: Set to zero so that Non-secure EL1 System register 1056 * accesses to the powerdown debug registers are not trapped to EL2. 1057 * 1058 * MDCR_EL2.TDA: Set to zero so that System register accesses to the 1059 * debug registers do not trap to EL2. 1060 * 1061 * MDCR_EL2.TDE: Set to zero so that debug exceptions are not routed to 1062 * EL2. 1063 */ 1064 mdcr_el2 = MDCR_EL2_RESET_VAL & 1065 ~(MDCR_EL2_TDRA_BIT | MDCR_EL2_TDOSA_BIT | MDCR_EL2_TDA_BIT | 1066 MDCR_EL2_TDE_BIT); 1067 1068 write_mdcr_el2(mdcr_el2); 1069 1070 /* 1071 * Initialise HSTR_EL2. All fields are architecturally UNKNOWN on reset. 1072 * 1073 * HSTR_EL2.T<n>: Set all these fields to zero so that Non-secure EL0 or 1074 * EL1 accesses to System registers do not trap to EL2. 1075 */ 1076 write_hstr_el2(HSTR_EL2_RESET_VAL & ~(HSTR_EL2_T_MASK)); 1077 1078 /* 1079 * Initialise CNTHP_CTL_EL2. All fields are architecturally UNKNOWN on 1080 * reset. 1081 * 1082 * CNTHP_CTL_EL2:ENABLE: Set to zero to disable the EL2 physical timer 1083 * and prevent timer interrupts. 1084 */ 1085 write_cnthp_ctl_el2(CNTHP_CTL_RESET_VAL & ~(CNTHP_CTL_ENABLE_BIT)); 1086 1087 manage_extensions_nonsecure_el2_unused(); 1088 #endif /* INIT_UNUSED_NS_EL2 */ 1089 } 1090 1091 /******************************************************************************* 1092 * Prepare the CPU system registers for first entry into realm, secure, or 1093 * normal world. 1094 * 1095 * If execution is requested to EL2 or hyp mode, SCTLR_EL2 is initialized 1096 * If execution is requested to non-secure EL1 or svc mode, and the CPU supports 1097 * EL2 then EL2 is disabled by configuring all necessary EL2 registers. 1098 * For all entries, the EL1 registers are initialized from the cpu_context 1099 ******************************************************************************/ 1100 void cm_prepare_el3_exit(size_t security_state) 1101 { 1102 u_register_t sctlr_el2, scr_el3; 1103 cpu_context_t *ctx = cm_get_context(security_state); 1104 1105 assert(ctx != NULL); 1106 1107 if (security_state == NON_SECURE) { 1108 uint64_t el2_implemented = el_implemented(2); 1109 1110 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), 1111 CTX_SCR_EL3); 1112 1113 if (el2_implemented != EL_IMPL_NONE) { 1114 1115 /* 1116 * If context is not being used for EL2, initialize 1117 * HCRX_EL2 with its init value here. 1118 */ 1119 if (is_feat_hcx_supported()) { 1120 write_hcrx_el2(HCRX_EL2_INIT_VAL); 1121 } 1122 1123 /* 1124 * Initialize Fine-grained trap registers introduced 1125 * by FEAT_FGT so all traps are initially disabled when 1126 * switching to EL2 or a lower EL, preventing undesired 1127 * behavior. 1128 */ 1129 if (is_feat_fgt_supported()) { 1130 /* 1131 * Initialize HFG*_EL2 registers with a default 1132 * value so legacy systems unaware of FEAT_FGT 1133 * do not get trapped due to their lack of 1134 * initialization for this feature. 1135 */ 1136 write_hfgitr_el2(HFGITR_EL2_INIT_VAL); 1137 write_hfgrtr_el2(HFGRTR_EL2_INIT_VAL); 1138 write_hfgwtr_el2(HFGWTR_EL2_INIT_VAL); 1139 } 1140 1141 /* Condition to ensure EL2 is being used. */ 1142 if ((scr_el3 & SCR_HCE_BIT) != 0U) { 1143 /* Initialize SCTLR_EL2 register with reset value. */ 1144 sctlr_el2 = SCTLR_EL2_RES1; 1145 1146 /* 1147 * If workaround of errata 764081 for Cortex-A75 1148 * is used then set SCTLR_EL2.IESB to enable 1149 * Implicit Error Synchronization Barrier. 1150 */ 1151 if (errata_a75_764081_applies()) { 1152 sctlr_el2 |= SCTLR_IESB_BIT; 1153 } 1154 1155 write_sctlr_el2(sctlr_el2); 1156 } else { 1157 /* 1158 * (scr_el3 & SCR_HCE_BIT==0) 1159 * EL2 implemented but unused. 1160 */ 1161 init_nonsecure_el2_unused(ctx); 1162 } 1163 } 1164 } 1165 #if (!CTX_INCLUDE_EL2_REGS) 1166 /* Restore EL1 system registers, only when CTX_INCLUDE_EL2_REGS=0 */ 1167 cm_el1_sysregs_context_restore(security_state); 1168 #endif 1169 cm_set_next_eret_context(security_state); 1170 } 1171 1172 #if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) 1173 1174 static void el2_sysregs_context_save_fgt(el2_sysregs_t *ctx) 1175 { 1176 write_el2_ctx_fgt(ctx, hdfgrtr_el2, read_hdfgrtr_el2()); 1177 if (is_feat_amu_supported()) { 1178 write_el2_ctx_fgt(ctx, hafgrtr_el2, read_hafgrtr_el2()); 1179 } 1180 write_el2_ctx_fgt(ctx, hdfgwtr_el2, read_hdfgwtr_el2()); 1181 write_el2_ctx_fgt(ctx, hfgitr_el2, read_hfgitr_el2()); 1182 write_el2_ctx_fgt(ctx, hfgrtr_el2, read_hfgrtr_el2()); 1183 write_el2_ctx_fgt(ctx, hfgwtr_el2, read_hfgwtr_el2()); 1184 } 1185 1186 static void el2_sysregs_context_restore_fgt(el2_sysregs_t *ctx) 1187 { 1188 write_hdfgrtr_el2(read_el2_ctx_fgt(ctx, hdfgrtr_el2)); 1189 if (is_feat_amu_supported()) { 1190 write_hafgrtr_el2(read_el2_ctx_fgt(ctx, hafgrtr_el2)); 1191 } 1192 write_hdfgwtr_el2(read_el2_ctx_fgt(ctx, hdfgwtr_el2)); 1193 write_hfgitr_el2(read_el2_ctx_fgt(ctx, hfgitr_el2)); 1194 write_hfgrtr_el2(read_el2_ctx_fgt(ctx, hfgrtr_el2)); 1195 write_hfgwtr_el2(read_el2_ctx_fgt(ctx, hfgwtr_el2)); 1196 } 1197 1198 static void el2_sysregs_context_save_fgt2(el2_sysregs_t *ctx) 1199 { 1200 write_el2_ctx_fgt2(ctx, hdfgrtr2_el2, read_hdfgrtr2_el2()); 1201 write_el2_ctx_fgt2(ctx, hdfgwtr2_el2, read_hdfgwtr2_el2()); 1202 write_el2_ctx_fgt2(ctx, hfgitr2_el2, read_hfgitr2_el2()); 1203 write_el2_ctx_fgt2(ctx, hfgrtr2_el2, read_hfgrtr2_el2()); 1204 write_el2_ctx_fgt2(ctx, hfgwtr2_el2, read_hfgwtr2_el2()); 1205 } 1206 1207 static void el2_sysregs_context_restore_fgt2(el2_sysregs_t *ctx) 1208 { 1209 write_hdfgrtr2_el2(read_el2_ctx_fgt2(ctx, hdfgrtr2_el2)); 1210 write_hdfgwtr2_el2(read_el2_ctx_fgt2(ctx, hdfgwtr2_el2)); 1211 write_hfgitr2_el2(read_el2_ctx_fgt2(ctx, hfgitr2_el2)); 1212 write_hfgrtr2_el2(read_el2_ctx_fgt2(ctx, hfgrtr2_el2)); 1213 write_hfgwtr2_el2(read_el2_ctx_fgt2(ctx, hfgwtr2_el2)); 1214 } 1215 1216 static void el2_sysregs_context_save_mpam(el2_sysregs_t *ctx) 1217 { 1218 u_register_t mpam_idr = read_mpamidr_el1(); 1219 1220 write_el2_ctx_mpam(ctx, mpam2_el2, read_mpam2_el2()); 1221 1222 /* 1223 * The context registers that we intend to save would be part of the 1224 * PE's system register frame only if MPAMIDR_EL1.HAS_HCR == 1. 1225 */ 1226 if ((mpam_idr & MPAMIDR_HAS_HCR_BIT) == 0U) { 1227 return; 1228 } 1229 1230 /* 1231 * MPAMHCR_EL2, MPAMVPMV_EL2 and MPAMVPM0_EL2 are always present if 1232 * MPAMIDR_HAS_HCR_BIT == 1. 1233 */ 1234 write_el2_ctx_mpam(ctx, mpamhcr_el2, read_mpamhcr_el2()); 1235 write_el2_ctx_mpam(ctx, mpamvpm0_el2, read_mpamvpm0_el2()); 1236 write_el2_ctx_mpam(ctx, mpamvpmv_el2, read_mpamvpmv_el2()); 1237 1238 /* 1239 * The number of MPAMVPM registers is implementation defined, their 1240 * number is stored in the MPAMIDR_EL1 register. 1241 */ 1242 switch ((mpam_idr >> MPAMIDR_EL1_VPMR_MAX_SHIFT) & MPAMIDR_EL1_VPMR_MAX_MASK) { 1243 case 7: 1244 write_el2_ctx_mpam(ctx, mpamvpm7_el2, read_mpamvpm7_el2()); 1245 __fallthrough; 1246 case 6: 1247 write_el2_ctx_mpam(ctx, mpamvpm6_el2, read_mpamvpm6_el2()); 1248 __fallthrough; 1249 case 5: 1250 write_el2_ctx_mpam(ctx, mpamvpm5_el2, read_mpamvpm5_el2()); 1251 __fallthrough; 1252 case 4: 1253 write_el2_ctx_mpam(ctx, mpamvpm4_el2, read_mpamvpm4_el2()); 1254 __fallthrough; 1255 case 3: 1256 write_el2_ctx_mpam(ctx, mpamvpm3_el2, read_mpamvpm3_el2()); 1257 __fallthrough; 1258 case 2: 1259 write_el2_ctx_mpam(ctx, mpamvpm2_el2, read_mpamvpm2_el2()); 1260 __fallthrough; 1261 case 1: 1262 write_el2_ctx_mpam(ctx, mpamvpm1_el2, read_mpamvpm1_el2()); 1263 break; 1264 } 1265 } 1266 1267 static void el2_sysregs_context_restore_mpam(el2_sysregs_t *ctx) 1268 { 1269 u_register_t mpam_idr = read_mpamidr_el1(); 1270 1271 write_mpam2_el2(read_el2_ctx_mpam(ctx, mpam2_el2)); 1272 1273 if ((mpam_idr & MPAMIDR_HAS_HCR_BIT) == 0U) { 1274 return; 1275 } 1276 1277 write_mpamhcr_el2(read_el2_ctx_mpam(ctx, mpamhcr_el2)); 1278 write_mpamvpm0_el2(read_el2_ctx_mpam(ctx, mpamvpm0_el2)); 1279 write_mpamvpmv_el2(read_el2_ctx_mpam(ctx, mpamvpmv_el2)); 1280 1281 switch ((mpam_idr >> MPAMIDR_EL1_VPMR_MAX_SHIFT) & MPAMIDR_EL1_VPMR_MAX_MASK) { 1282 case 7: 1283 write_mpamvpm7_el2(read_el2_ctx_mpam(ctx, mpamvpm7_el2)); 1284 __fallthrough; 1285 case 6: 1286 write_mpamvpm6_el2(read_el2_ctx_mpam(ctx, mpamvpm6_el2)); 1287 __fallthrough; 1288 case 5: 1289 write_mpamvpm5_el2(read_el2_ctx_mpam(ctx, mpamvpm5_el2)); 1290 __fallthrough; 1291 case 4: 1292 write_mpamvpm4_el2(read_el2_ctx_mpam(ctx, mpamvpm4_el2)); 1293 __fallthrough; 1294 case 3: 1295 write_mpamvpm3_el2(read_el2_ctx_mpam(ctx, mpamvpm3_el2)); 1296 __fallthrough; 1297 case 2: 1298 write_mpamvpm2_el2(read_el2_ctx_mpam(ctx, mpamvpm2_el2)); 1299 __fallthrough; 1300 case 1: 1301 write_mpamvpm1_el2(read_el2_ctx_mpam(ctx, mpamvpm1_el2)); 1302 break; 1303 } 1304 } 1305 1306 /* --------------------------------------------------------------------------- 1307 * The following registers are not added: 1308 * ICH_AP0R<n>_EL2 1309 * ICH_AP1R<n>_EL2 1310 * ICH_LR<n>_EL2 1311 * 1312 * NOTE: For a system with S-EL2 present but not enabled, accessing 1313 * ICC_SRE_EL2 is undefined from EL3. To workaround this change the 1314 * SCR_EL3.NS = 1 before accessing this register. 1315 * --------------------------------------------------------------------------- 1316 */ 1317 static void el2_sysregs_context_save_gic(el2_sysregs_t *ctx, uint32_t security_state) 1318 { 1319 u_register_t scr_el3 = read_scr_el3(); 1320 1321 #if defined(SPD_spmd) && SPMD_SPM_AT_SEL2 1322 write_el2_ctx_common(ctx, icc_sre_el2, read_icc_sre_el2()); 1323 #else 1324 write_scr_el3(scr_el3 | SCR_NS_BIT); 1325 isb(); 1326 1327 write_el2_ctx_common(ctx, icc_sre_el2, read_icc_sre_el2()); 1328 1329 write_scr_el3(scr_el3); 1330 isb(); 1331 #endif 1332 write_el2_ctx_common(ctx, ich_hcr_el2, read_ich_hcr_el2()); 1333 1334 if (errata_ich_vmcr_el2_applies()) { 1335 if (security_state == SECURE) { 1336 write_scr_el3(scr_el3 & ~SCR_NS_BIT); 1337 } else { 1338 write_scr_el3(scr_el3 | SCR_NS_BIT); 1339 } 1340 isb(); 1341 } 1342 1343 write_el2_ctx_common(ctx, ich_vmcr_el2, read_ich_vmcr_el2()); 1344 1345 if (errata_ich_vmcr_el2_applies()) { 1346 write_scr_el3(scr_el3); 1347 isb(); 1348 } 1349 } 1350 1351 static void el2_sysregs_context_restore_gic(el2_sysregs_t *ctx, uint32_t security_state) 1352 { 1353 u_register_t scr_el3 = read_scr_el3(); 1354 1355 #if defined(SPD_spmd) && SPMD_SPM_AT_SEL2 1356 write_icc_sre_el2(read_el2_ctx_common(ctx, icc_sre_el2)); 1357 #else 1358 write_scr_el3(scr_el3 | SCR_NS_BIT); 1359 isb(); 1360 1361 write_icc_sre_el2(read_el2_ctx_common(ctx, icc_sre_el2)); 1362 1363 write_scr_el3(scr_el3); 1364 isb(); 1365 #endif 1366 write_ich_hcr_el2(read_el2_ctx_common(ctx, ich_hcr_el2)); 1367 1368 if (errata_ich_vmcr_el2_applies()) { 1369 if (security_state == SECURE) { 1370 write_scr_el3(scr_el3 & ~SCR_NS_BIT); 1371 } else { 1372 write_scr_el3(scr_el3 | SCR_NS_BIT); 1373 } 1374 isb(); 1375 } 1376 1377 write_ich_vmcr_el2(read_el2_ctx_common(ctx, ich_vmcr_el2)); 1378 1379 if (errata_ich_vmcr_el2_applies()) { 1380 write_scr_el3(scr_el3); 1381 isb(); 1382 } 1383 } 1384 1385 /* ----------------------------------------------------- 1386 * The following registers are not added: 1387 * AMEVCNTVOFF0<n>_EL2 1388 * AMEVCNTVOFF1<n>_EL2 1389 * ----------------------------------------------------- 1390 */ 1391 static void el2_sysregs_context_save_common(el2_sysregs_t *ctx) 1392 { 1393 write_el2_ctx_common(ctx, actlr_el2, read_actlr_el2()); 1394 write_el2_ctx_common(ctx, afsr0_el2, read_afsr0_el2()); 1395 write_el2_ctx_common(ctx, afsr1_el2, read_afsr1_el2()); 1396 write_el2_ctx_common(ctx, amair_el2, read_amair_el2()); 1397 write_el2_ctx_common(ctx, cnthctl_el2, read_cnthctl_el2()); 1398 write_el2_ctx_common(ctx, cntvoff_el2, read_cntvoff_el2()); 1399 write_el2_ctx_common(ctx, cptr_el2, read_cptr_el2()); 1400 if (CTX_INCLUDE_AARCH32_REGS) { 1401 write_el2_ctx_common(ctx, dbgvcr32_el2, read_dbgvcr32_el2()); 1402 } 1403 write_el2_ctx_common(ctx, elr_el2, read_elr_el2()); 1404 write_el2_ctx_common(ctx, esr_el2, read_esr_el2()); 1405 write_el2_ctx_common(ctx, far_el2, read_far_el2()); 1406 write_el2_ctx_common(ctx, hacr_el2, read_hacr_el2()); 1407 write_el2_ctx_common(ctx, hcr_el2, read_hcr_el2()); 1408 write_el2_ctx_common(ctx, hpfar_el2, read_hpfar_el2()); 1409 write_el2_ctx_common(ctx, hstr_el2, read_hstr_el2()); 1410 write_el2_ctx_common(ctx, mair_el2, read_mair_el2()); 1411 write_el2_ctx_common(ctx, mdcr_el2, read_mdcr_el2()); 1412 write_el2_ctx_common(ctx, sctlr_el2, read_sctlr_el2()); 1413 write_el2_ctx_common(ctx, spsr_el2, read_spsr_el2()); 1414 write_el2_ctx_common(ctx, sp_el2, read_sp_el2()); 1415 write_el2_ctx_common(ctx, tcr_el2, read_tcr_el2()); 1416 write_el2_ctx_common(ctx, tpidr_el2, read_tpidr_el2()); 1417 write_el2_ctx_common(ctx, vbar_el2, read_vbar_el2()); 1418 write_el2_ctx_common(ctx, vmpidr_el2, read_vmpidr_el2()); 1419 write_el2_ctx_common(ctx, vpidr_el2, read_vpidr_el2()); 1420 write_el2_ctx_common(ctx, vtcr_el2, read_vtcr_el2()); 1421 1422 write_el2_ctx_common_sysreg128(ctx, ttbr0_el2, read_ttbr0_el2()); 1423 write_el2_ctx_common_sysreg128(ctx, vttbr_el2, read_vttbr_el2()); 1424 } 1425 1426 static void el2_sysregs_context_restore_common(el2_sysregs_t *ctx) 1427 { 1428 write_actlr_el2(read_el2_ctx_common(ctx, actlr_el2)); 1429 write_afsr0_el2(read_el2_ctx_common(ctx, afsr0_el2)); 1430 write_afsr1_el2(read_el2_ctx_common(ctx, afsr1_el2)); 1431 write_amair_el2(read_el2_ctx_common(ctx, amair_el2)); 1432 write_cnthctl_el2(read_el2_ctx_common(ctx, cnthctl_el2)); 1433 write_cntvoff_el2(read_el2_ctx_common(ctx, cntvoff_el2)); 1434 write_cptr_el2(read_el2_ctx_common(ctx, cptr_el2)); 1435 if (CTX_INCLUDE_AARCH32_REGS) { 1436 write_dbgvcr32_el2(read_el2_ctx_common(ctx, dbgvcr32_el2)); 1437 } 1438 write_elr_el2(read_el2_ctx_common(ctx, elr_el2)); 1439 write_esr_el2(read_el2_ctx_common(ctx, esr_el2)); 1440 write_far_el2(read_el2_ctx_common(ctx, far_el2)); 1441 write_hacr_el2(read_el2_ctx_common(ctx, hacr_el2)); 1442 write_hcr_el2(read_el2_ctx_common(ctx, hcr_el2)); 1443 write_hpfar_el2(read_el2_ctx_common(ctx, hpfar_el2)); 1444 write_hstr_el2(read_el2_ctx_common(ctx, hstr_el2)); 1445 write_mair_el2(read_el2_ctx_common(ctx, mair_el2)); 1446 write_mdcr_el2(read_el2_ctx_common(ctx, mdcr_el2)); 1447 write_sctlr_el2(read_el2_ctx_common(ctx, sctlr_el2)); 1448 write_spsr_el2(read_el2_ctx_common(ctx, spsr_el2)); 1449 write_sp_el2(read_el2_ctx_common(ctx, sp_el2)); 1450 write_tcr_el2(read_el2_ctx_common(ctx, tcr_el2)); 1451 write_tpidr_el2(read_el2_ctx_common(ctx, tpidr_el2)); 1452 write_ttbr0_el2(read_el2_ctx_common(ctx, ttbr0_el2)); 1453 write_vbar_el2(read_el2_ctx_common(ctx, vbar_el2)); 1454 write_vmpidr_el2(read_el2_ctx_common(ctx, vmpidr_el2)); 1455 write_vpidr_el2(read_el2_ctx_common(ctx, vpidr_el2)); 1456 write_vtcr_el2(read_el2_ctx_common(ctx, vtcr_el2)); 1457 write_vttbr_el2(read_el2_ctx_common(ctx, vttbr_el2)); 1458 } 1459 1460 /******************************************************************************* 1461 * Save EL2 sysreg context 1462 ******************************************************************************/ 1463 void cm_el2_sysregs_context_save(uint32_t security_state) 1464 { 1465 cpu_context_t *ctx; 1466 el2_sysregs_t *el2_sysregs_ctx; 1467 1468 ctx = cm_get_context(security_state); 1469 assert(ctx != NULL); 1470 1471 el2_sysregs_ctx = get_el2_sysregs_ctx(ctx); 1472 1473 el2_sysregs_context_save_common(el2_sysregs_ctx); 1474 el2_sysregs_context_save_gic(el2_sysregs_ctx, security_state); 1475 1476 if (is_feat_mte2_supported()) { 1477 write_el2_ctx_mte2(el2_sysregs_ctx, tfsr_el2, read_tfsr_el2()); 1478 } 1479 1480 if (is_feat_mpam_supported()) { 1481 el2_sysregs_context_save_mpam(el2_sysregs_ctx); 1482 } 1483 1484 if (is_feat_fgt_supported()) { 1485 el2_sysregs_context_save_fgt(el2_sysregs_ctx); 1486 } 1487 1488 if (is_feat_fgt2_supported()) { 1489 el2_sysregs_context_save_fgt2(el2_sysregs_ctx); 1490 } 1491 1492 if (is_feat_ecv_v2_supported()) { 1493 write_el2_ctx_ecv(el2_sysregs_ctx, cntpoff_el2, read_cntpoff_el2()); 1494 } 1495 1496 if (is_feat_vhe_supported()) { 1497 write_el2_ctx_vhe(el2_sysregs_ctx, contextidr_el2, 1498 read_contextidr_el2()); 1499 write_el2_ctx_vhe_sysreg128(el2_sysregs_ctx, ttbr1_el2, read_ttbr1_el2()); 1500 } 1501 1502 if (is_feat_ras_supported()) { 1503 write_el2_ctx_ras(el2_sysregs_ctx, vdisr_el2, read_vdisr_el2()); 1504 write_el2_ctx_ras(el2_sysregs_ctx, vsesr_el2, read_vsesr_el2()); 1505 } 1506 1507 if (is_feat_nv2_supported()) { 1508 write_el2_ctx_neve(el2_sysregs_ctx, vncr_el2, read_vncr_el2()); 1509 } 1510 1511 if (is_feat_trf_supported()) { 1512 write_el2_ctx_trf(el2_sysregs_ctx, trfcr_el2, read_trfcr_el2()); 1513 } 1514 1515 if (is_feat_csv2_2_supported()) { 1516 write_el2_ctx_csv2_2(el2_sysregs_ctx, scxtnum_el2, 1517 read_scxtnum_el2()); 1518 } 1519 1520 if (is_feat_hcx_supported()) { 1521 write_el2_ctx_hcx(el2_sysregs_ctx, hcrx_el2, read_hcrx_el2()); 1522 } 1523 1524 if (is_feat_tcr2_supported()) { 1525 write_el2_ctx_tcr2(el2_sysregs_ctx, tcr2_el2, read_tcr2_el2()); 1526 } 1527 1528 if (is_feat_sxpie_supported()) { 1529 write_el2_ctx_sxpie(el2_sysregs_ctx, pire0_el2, read_pire0_el2()); 1530 write_el2_ctx_sxpie(el2_sysregs_ctx, pir_el2, read_pir_el2()); 1531 } 1532 1533 if (is_feat_sxpoe_supported()) { 1534 write_el2_ctx_sxpoe(el2_sysregs_ctx, por_el2, read_por_el2()); 1535 } 1536 1537 if (is_feat_brbe_supported()) { 1538 write_el2_ctx_brbe(el2_sysregs_ctx, brbcr_el2, read_brbcr_el2()); 1539 } 1540 1541 if (is_feat_s2pie_supported()) { 1542 write_el2_ctx_s2pie(el2_sysregs_ctx, s2pir_el2, read_s2pir_el2()); 1543 } 1544 1545 if (is_feat_gcs_supported()) { 1546 write_el2_ctx_gcs(el2_sysregs_ctx, gcscr_el2, read_gcscr_el2()); 1547 write_el2_ctx_gcs(el2_sysregs_ctx, gcspr_el2, read_gcspr_el2()); 1548 } 1549 1550 if (is_feat_sctlr2_supported()) { 1551 write_el2_ctx_sctlr2(el2_sysregs_ctx, sctlr2_el2, read_sctlr2_el2()); 1552 } 1553 } 1554 1555 /******************************************************************************* 1556 * Restore EL2 sysreg context 1557 ******************************************************************************/ 1558 void cm_el2_sysregs_context_restore(uint32_t security_state) 1559 { 1560 cpu_context_t *ctx; 1561 el2_sysregs_t *el2_sysregs_ctx; 1562 1563 ctx = cm_get_context(security_state); 1564 assert(ctx != NULL); 1565 1566 el2_sysregs_ctx = get_el2_sysregs_ctx(ctx); 1567 1568 el2_sysregs_context_restore_common(el2_sysregs_ctx); 1569 el2_sysregs_context_restore_gic(el2_sysregs_ctx, security_state); 1570 1571 if (is_feat_mte2_supported()) { 1572 write_tfsr_el2(read_el2_ctx_mte2(el2_sysregs_ctx, tfsr_el2)); 1573 } 1574 1575 if (is_feat_mpam_supported()) { 1576 el2_sysregs_context_restore_mpam(el2_sysregs_ctx); 1577 } 1578 1579 if (is_feat_fgt_supported()) { 1580 el2_sysregs_context_restore_fgt(el2_sysregs_ctx); 1581 } 1582 1583 if (is_feat_fgt2_supported()) { 1584 el2_sysregs_context_restore_fgt2(el2_sysregs_ctx); 1585 } 1586 1587 if (is_feat_ecv_v2_supported()) { 1588 write_cntpoff_el2(read_el2_ctx_ecv(el2_sysregs_ctx, cntpoff_el2)); 1589 } 1590 1591 if (is_feat_vhe_supported()) { 1592 write_contextidr_el2(read_el2_ctx_vhe(el2_sysregs_ctx, 1593 contextidr_el2)); 1594 write_ttbr1_el2(read_el2_ctx_vhe(el2_sysregs_ctx, ttbr1_el2)); 1595 } 1596 1597 if (is_feat_ras_supported()) { 1598 write_vdisr_el2(read_el2_ctx_ras(el2_sysregs_ctx, vdisr_el2)); 1599 write_vsesr_el2(read_el2_ctx_ras(el2_sysregs_ctx, vsesr_el2)); 1600 } 1601 1602 if (is_feat_nv2_supported()) { 1603 write_vncr_el2(read_el2_ctx_neve(el2_sysregs_ctx, vncr_el2)); 1604 } 1605 1606 if (is_feat_trf_supported()) { 1607 write_trfcr_el2(read_el2_ctx_trf(el2_sysregs_ctx, trfcr_el2)); 1608 } 1609 1610 if (is_feat_csv2_2_supported()) { 1611 write_scxtnum_el2(read_el2_ctx_csv2_2(el2_sysregs_ctx, 1612 scxtnum_el2)); 1613 } 1614 1615 if (is_feat_hcx_supported()) { 1616 write_hcrx_el2(read_el2_ctx_hcx(el2_sysregs_ctx, hcrx_el2)); 1617 } 1618 1619 if (is_feat_tcr2_supported()) { 1620 write_tcr2_el2(read_el2_ctx_tcr2(el2_sysregs_ctx, tcr2_el2)); 1621 } 1622 1623 if (is_feat_sxpie_supported()) { 1624 write_pire0_el2(read_el2_ctx_sxpie(el2_sysregs_ctx, pire0_el2)); 1625 write_pir_el2(read_el2_ctx_sxpie(el2_sysregs_ctx, pir_el2)); 1626 } 1627 1628 if (is_feat_sxpoe_supported()) { 1629 write_por_el2(read_el2_ctx_sxpoe(el2_sysregs_ctx, por_el2)); 1630 } 1631 1632 if (is_feat_s2pie_supported()) { 1633 write_s2pir_el2(read_el2_ctx_s2pie(el2_sysregs_ctx, s2pir_el2)); 1634 } 1635 1636 if (is_feat_gcs_supported()) { 1637 write_gcscr_el2(read_el2_ctx_gcs(el2_sysregs_ctx, gcscr_el2)); 1638 write_gcspr_el2(read_el2_ctx_gcs(el2_sysregs_ctx, gcspr_el2)); 1639 } 1640 1641 if (is_feat_sctlr2_supported()) { 1642 write_sctlr2_el2(read_el2_ctx_sctlr2(el2_sysregs_ctx, sctlr2_el2)); 1643 } 1644 1645 if (is_feat_brbe_supported()) { 1646 write_brbcr_el2(read_el2_ctx_brbe(el2_sysregs_ctx, brbcr_el2)); 1647 } 1648 } 1649 #endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */ 1650 1651 /******************************************************************************* 1652 * This function is used to exit to Non-secure world. If CTX_INCLUDE_EL2_REGS 1653 * is enabled, it restores EL1 and EL2 sysreg contexts instead of directly 1654 * updating EL1 and EL2 registers. Otherwise, it calls the generic 1655 * cm_prepare_el3_exit function. 1656 ******************************************************************************/ 1657 void cm_prepare_el3_exit_ns(void) 1658 { 1659 #if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) 1660 #if ENABLE_ASSERTIONS 1661 cpu_context_t *ctx = cm_get_context(NON_SECURE); 1662 assert(ctx != NULL); 1663 1664 /* Assert that EL2 is used. */ 1665 u_register_t scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3); 1666 assert(((scr_el3 & SCR_HCE_BIT) != 0UL) && 1667 (el_implemented(2U) != EL_IMPL_NONE)); 1668 #endif /* ENABLE_ASSERTIONS */ 1669 1670 /* Restore EL2 sysreg contexts */ 1671 cm_el2_sysregs_context_restore(NON_SECURE); 1672 cm_set_next_eret_context(NON_SECURE); 1673 #else 1674 cm_prepare_el3_exit(NON_SECURE); 1675 #endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */ 1676 } 1677 1678 #if ((IMAGE_BL1) || (IMAGE_BL31 && (!CTX_INCLUDE_EL2_REGS))) 1679 /******************************************************************************* 1680 * The next set of six functions are used by runtime services to save and restore 1681 * EL1 context on the 'cpu_context' structure for the specified security state. 1682 ******************************************************************************/ 1683 static void el1_sysregs_context_save(el1_sysregs_t *ctx) 1684 { 1685 write_el1_ctx_common(ctx, spsr_el1, read_spsr_el1()); 1686 write_el1_ctx_common(ctx, elr_el1, read_elr_el1()); 1687 1688 #if (!ERRATA_SPECULATIVE_AT) 1689 write_el1_ctx_common(ctx, sctlr_el1, read_sctlr_el1()); 1690 write_el1_ctx_common(ctx, tcr_el1, read_tcr_el1()); 1691 #endif /* (!ERRATA_SPECULATIVE_AT) */ 1692 1693 write_el1_ctx_common(ctx, cpacr_el1, read_cpacr_el1()); 1694 write_el1_ctx_common(ctx, csselr_el1, read_csselr_el1()); 1695 write_el1_ctx_common(ctx, sp_el1, read_sp_el1()); 1696 write_el1_ctx_common(ctx, esr_el1, read_esr_el1()); 1697 write_el1_ctx_common(ctx, mair_el1, read_mair_el1()); 1698 write_el1_ctx_common(ctx, amair_el1, read_amair_el1()); 1699 write_el1_ctx_common(ctx, actlr_el1, read_actlr_el1()); 1700 write_el1_ctx_common(ctx, tpidr_el1, read_tpidr_el1()); 1701 write_el1_ctx_common(ctx, tpidr_el0, read_tpidr_el0()); 1702 write_el1_ctx_common(ctx, tpidrro_el0, read_tpidrro_el0()); 1703 write_el1_ctx_common(ctx, far_el1, read_far_el1()); 1704 write_el1_ctx_common(ctx, afsr0_el1, read_afsr0_el1()); 1705 write_el1_ctx_common(ctx, afsr1_el1, read_afsr1_el1()); 1706 write_el1_ctx_common(ctx, contextidr_el1, read_contextidr_el1()); 1707 write_el1_ctx_common(ctx, vbar_el1, read_vbar_el1()); 1708 write_el1_ctx_common(ctx, mdccint_el1, read_mdccint_el1()); 1709 write_el1_ctx_common(ctx, mdscr_el1, read_mdscr_el1()); 1710 1711 write_el1_ctx_common_sysreg128(ctx, par_el1, read_par_el1()); 1712 write_el1_ctx_common_sysreg128(ctx, ttbr0_el1, read_ttbr0_el1()); 1713 write_el1_ctx_common_sysreg128(ctx, ttbr1_el1, read_ttbr1_el1()); 1714 1715 if (CTX_INCLUDE_AARCH32_REGS) { 1716 /* Save Aarch32 registers */ 1717 write_el1_ctx_aarch32(ctx, spsr_abt, read_spsr_abt()); 1718 write_el1_ctx_aarch32(ctx, spsr_und, read_spsr_und()); 1719 write_el1_ctx_aarch32(ctx, spsr_irq, read_spsr_irq()); 1720 write_el1_ctx_aarch32(ctx, spsr_fiq, read_spsr_fiq()); 1721 write_el1_ctx_aarch32(ctx, dacr32_el2, read_dacr32_el2()); 1722 write_el1_ctx_aarch32(ctx, ifsr32_el2, read_ifsr32_el2()); 1723 } 1724 1725 if (NS_TIMER_SWITCH) { 1726 /* Save NS Timer registers */ 1727 write_el1_ctx_arch_timer(ctx, cntp_ctl_el0, read_cntp_ctl_el0()); 1728 write_el1_ctx_arch_timer(ctx, cntp_cval_el0, read_cntp_cval_el0()); 1729 write_el1_ctx_arch_timer(ctx, cntv_ctl_el0, read_cntv_ctl_el0()); 1730 write_el1_ctx_arch_timer(ctx, cntv_cval_el0, read_cntv_cval_el0()); 1731 write_el1_ctx_arch_timer(ctx, cntkctl_el1, read_cntkctl_el1()); 1732 } 1733 1734 if (is_feat_mte2_supported()) { 1735 write_el1_ctx_mte2(ctx, tfsre0_el1, read_tfsre0_el1()); 1736 write_el1_ctx_mte2(ctx, tfsr_el1, read_tfsr_el1()); 1737 write_el1_ctx_mte2(ctx, rgsr_el1, read_rgsr_el1()); 1738 write_el1_ctx_mte2(ctx, gcr_el1, read_gcr_el1()); 1739 } 1740 1741 if (is_feat_ras_supported()) { 1742 write_el1_ctx_ras(ctx, disr_el1, read_disr_el1()); 1743 } 1744 1745 if (is_feat_s1pie_supported()) { 1746 write_el1_ctx_s1pie(ctx, pire0_el1, read_pire0_el1()); 1747 write_el1_ctx_s1pie(ctx, pir_el1, read_pir_el1()); 1748 } 1749 1750 if (is_feat_s1poe_supported()) { 1751 write_el1_ctx_s1poe(ctx, por_el1, read_por_el1()); 1752 } 1753 1754 if (is_feat_s2poe_supported()) { 1755 write_el1_ctx_s2poe(ctx, s2por_el1, read_s2por_el1()); 1756 } 1757 1758 if (is_feat_tcr2_supported()) { 1759 write_el1_ctx_tcr2(ctx, tcr2_el1, read_tcr2_el1()); 1760 } 1761 1762 if (is_feat_trf_supported()) { 1763 write_el1_ctx_trf(ctx, trfcr_el1, read_trfcr_el1()); 1764 } 1765 1766 if (is_feat_csv2_2_supported()) { 1767 write_el1_ctx_csv2_2(ctx, scxtnum_el0, read_scxtnum_el0()); 1768 write_el1_ctx_csv2_2(ctx, scxtnum_el1, read_scxtnum_el1()); 1769 } 1770 1771 if (is_feat_gcs_supported()) { 1772 write_el1_ctx_gcs(ctx, gcscr_el1, read_gcscr_el1()); 1773 write_el1_ctx_gcs(ctx, gcscre0_el1, read_gcscre0_el1()); 1774 write_el1_ctx_gcs(ctx, gcspr_el1, read_gcspr_el1()); 1775 write_el1_ctx_gcs(ctx, gcspr_el0, read_gcspr_el0()); 1776 } 1777 1778 if (is_feat_the_supported()) { 1779 write_el1_ctx_the_sysreg128(ctx, rcwmask_el1, read_rcwmask_el1()); 1780 write_el1_ctx_the_sysreg128(ctx, rcwsmask_el1, read_rcwsmask_el1()); 1781 } 1782 1783 if (is_feat_sctlr2_supported()) { 1784 write_el1_ctx_sctlr2(ctx, sctlr2_el1, read_sctlr2_el1()); 1785 } 1786 1787 if (is_feat_ls64_accdata_supported()) { 1788 write_el1_ctx_ls64(ctx, accdata_el1, read_accdata_el1()); 1789 } 1790 } 1791 1792 static void el1_sysregs_context_restore(el1_sysregs_t *ctx) 1793 { 1794 write_spsr_el1(read_el1_ctx_common(ctx, spsr_el1)); 1795 write_elr_el1(read_el1_ctx_common(ctx, elr_el1)); 1796 1797 #if (!ERRATA_SPECULATIVE_AT) 1798 write_sctlr_el1(read_el1_ctx_common(ctx, sctlr_el1)); 1799 write_tcr_el1(read_el1_ctx_common(ctx, tcr_el1)); 1800 #endif /* (!ERRATA_SPECULATIVE_AT) */ 1801 1802 write_cpacr_el1(read_el1_ctx_common(ctx, cpacr_el1)); 1803 write_csselr_el1(read_el1_ctx_common(ctx, csselr_el1)); 1804 write_sp_el1(read_el1_ctx_common(ctx, sp_el1)); 1805 write_esr_el1(read_el1_ctx_common(ctx, esr_el1)); 1806 write_ttbr0_el1(read_el1_ctx_common(ctx, ttbr0_el1)); 1807 write_ttbr1_el1(read_el1_ctx_common(ctx, ttbr1_el1)); 1808 write_mair_el1(read_el1_ctx_common(ctx, mair_el1)); 1809 write_amair_el1(read_el1_ctx_common(ctx, amair_el1)); 1810 write_actlr_el1(read_el1_ctx_common(ctx, actlr_el1)); 1811 write_tpidr_el1(read_el1_ctx_common(ctx, tpidr_el1)); 1812 write_tpidr_el0(read_el1_ctx_common(ctx, tpidr_el0)); 1813 write_tpidrro_el0(read_el1_ctx_common(ctx, tpidrro_el0)); 1814 write_par_el1(read_el1_ctx_common(ctx, par_el1)); 1815 write_far_el1(read_el1_ctx_common(ctx, far_el1)); 1816 write_afsr0_el1(read_el1_ctx_common(ctx, afsr0_el1)); 1817 write_afsr1_el1(read_el1_ctx_common(ctx, afsr1_el1)); 1818 write_contextidr_el1(read_el1_ctx_common(ctx, contextidr_el1)); 1819 write_vbar_el1(read_el1_ctx_common(ctx, vbar_el1)); 1820 write_mdccint_el1(read_el1_ctx_common(ctx, mdccint_el1)); 1821 write_mdscr_el1(read_el1_ctx_common(ctx, mdscr_el1)); 1822 1823 if (CTX_INCLUDE_AARCH32_REGS) { 1824 /* Restore Aarch32 registers */ 1825 write_spsr_abt(read_el1_ctx_aarch32(ctx, spsr_abt)); 1826 write_spsr_und(read_el1_ctx_aarch32(ctx, spsr_und)); 1827 write_spsr_irq(read_el1_ctx_aarch32(ctx, spsr_irq)); 1828 write_spsr_fiq(read_el1_ctx_aarch32(ctx, spsr_fiq)); 1829 write_dacr32_el2(read_el1_ctx_aarch32(ctx, dacr32_el2)); 1830 write_ifsr32_el2(read_el1_ctx_aarch32(ctx, ifsr32_el2)); 1831 } 1832 1833 if (NS_TIMER_SWITCH) { 1834 /* Restore NS Timer registers */ 1835 write_cntp_ctl_el0(read_el1_ctx_arch_timer(ctx, cntp_ctl_el0)); 1836 write_cntp_cval_el0(read_el1_ctx_arch_timer(ctx, cntp_cval_el0)); 1837 write_cntv_ctl_el0(read_el1_ctx_arch_timer(ctx, cntv_ctl_el0)); 1838 write_cntv_cval_el0(read_el1_ctx_arch_timer(ctx, cntv_cval_el0)); 1839 write_cntkctl_el1(read_el1_ctx_arch_timer(ctx, cntkctl_el1)); 1840 } 1841 1842 if (is_feat_mte2_supported()) { 1843 write_tfsre0_el1(read_el1_ctx_mte2(ctx, tfsre0_el1)); 1844 write_tfsr_el1(read_el1_ctx_mte2(ctx, tfsr_el1)); 1845 write_rgsr_el1(read_el1_ctx_mte2(ctx, rgsr_el1)); 1846 write_gcr_el1(read_el1_ctx_mte2(ctx, gcr_el1)); 1847 } 1848 1849 if (is_feat_ras_supported()) { 1850 write_disr_el1(read_el1_ctx_ras(ctx, disr_el1)); 1851 } 1852 1853 if (is_feat_s1pie_supported()) { 1854 write_pire0_el1(read_el1_ctx_s1pie(ctx, pire0_el1)); 1855 write_pir_el1(read_el1_ctx_s1pie(ctx, pir_el1)); 1856 } 1857 1858 if (is_feat_s1poe_supported()) { 1859 write_por_el1(read_el1_ctx_s1poe(ctx, por_el1)); 1860 } 1861 1862 if (is_feat_s2poe_supported()) { 1863 write_s2por_el1(read_el1_ctx_s2poe(ctx, s2por_el1)); 1864 } 1865 1866 if (is_feat_tcr2_supported()) { 1867 write_tcr2_el1(read_el1_ctx_tcr2(ctx, tcr2_el1)); 1868 } 1869 1870 if (is_feat_trf_supported()) { 1871 write_trfcr_el1(read_el1_ctx_trf(ctx, trfcr_el1)); 1872 } 1873 1874 if (is_feat_csv2_2_supported()) { 1875 write_scxtnum_el0(read_el1_ctx_csv2_2(ctx, scxtnum_el0)); 1876 write_scxtnum_el1(read_el1_ctx_csv2_2(ctx, scxtnum_el1)); 1877 } 1878 1879 if (is_feat_gcs_supported()) { 1880 write_gcscr_el1(read_el1_ctx_gcs(ctx, gcscr_el1)); 1881 write_gcscre0_el1(read_el1_ctx_gcs(ctx, gcscre0_el1)); 1882 write_gcspr_el1(read_el1_ctx_gcs(ctx, gcspr_el1)); 1883 write_gcspr_el0(read_el1_ctx_gcs(ctx, gcspr_el0)); 1884 } 1885 1886 if (is_feat_the_supported()) { 1887 write_rcwmask_el1(read_el1_ctx_the(ctx, rcwmask_el1)); 1888 write_rcwsmask_el1(read_el1_ctx_the(ctx, rcwsmask_el1)); 1889 } 1890 1891 if (is_feat_sctlr2_supported()) { 1892 write_sctlr2_el1(read_el1_ctx_sctlr2(ctx, sctlr2_el1)); 1893 } 1894 1895 if (is_feat_ls64_accdata_supported()) { 1896 write_accdata_el1(read_el1_ctx_ls64(ctx, accdata_el1)); 1897 } 1898 } 1899 1900 /******************************************************************************* 1901 * The next couple of functions are used by runtime services to save and restore 1902 * EL1 context on the 'cpu_context' structure for the specified security state. 1903 ******************************************************************************/ 1904 void cm_el1_sysregs_context_save(uint32_t security_state) 1905 { 1906 cpu_context_t *ctx; 1907 1908 ctx = cm_get_context(security_state); 1909 assert(ctx != NULL); 1910 1911 el1_sysregs_context_save(get_el1_sysregs_ctx(ctx)); 1912 1913 #if IMAGE_BL31 1914 if (security_state == SECURE) { 1915 PUBLISH_EVENT(cm_exited_secure_world); 1916 } else { 1917 PUBLISH_EVENT(cm_exited_normal_world); 1918 } 1919 #endif 1920 } 1921 1922 void cm_el1_sysregs_context_restore(uint32_t security_state) 1923 { 1924 cpu_context_t *ctx; 1925 1926 ctx = cm_get_context(security_state); 1927 assert(ctx != NULL); 1928 1929 el1_sysregs_context_restore(get_el1_sysregs_ctx(ctx)); 1930 1931 #if IMAGE_BL31 1932 if (security_state == SECURE) { 1933 PUBLISH_EVENT(cm_entering_secure_world); 1934 } else { 1935 PUBLISH_EVENT(cm_entering_normal_world); 1936 } 1937 #endif 1938 } 1939 1940 #endif /* ((IMAGE_BL1) || (IMAGE_BL31 && (!CTX_INCLUDE_EL2_REGS))) */ 1941 1942 /******************************************************************************* 1943 * This function populates ELR_EL3 member of 'cpu_context' pertaining to the 1944 * given security state with the given entrypoint 1945 ******************************************************************************/ 1946 void cm_set_elr_el3(uint32_t security_state, uintptr_t entrypoint) 1947 { 1948 cpu_context_t *ctx; 1949 el3_state_t *state; 1950 1951 ctx = cm_get_context(security_state); 1952 assert(ctx != NULL); 1953 1954 /* Populate EL3 state so that ERET jumps to the correct entry */ 1955 state = get_el3state_ctx(ctx); 1956 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 1957 } 1958 1959 /******************************************************************************* 1960 * This function populates ELR_EL3 and SPSR_EL3 members of 'cpu_context' 1961 * pertaining to the given security state 1962 ******************************************************************************/ 1963 void cm_set_elr_spsr_el3(uint32_t security_state, 1964 uintptr_t entrypoint, uint32_t spsr) 1965 { 1966 cpu_context_t *ctx; 1967 el3_state_t *state; 1968 1969 ctx = cm_get_context(security_state); 1970 assert(ctx != NULL); 1971 1972 /* Populate EL3 state so that ERET jumps to the correct entry */ 1973 state = get_el3state_ctx(ctx); 1974 write_ctx_reg(state, CTX_ELR_EL3, entrypoint); 1975 write_ctx_reg(state, CTX_SPSR_EL3, spsr); 1976 } 1977 1978 /******************************************************************************* 1979 * This function updates a single bit in the SCR_EL3 member of the 'cpu_context' 1980 * pertaining to the given security state using the value and bit position 1981 * specified in the parameters. It preserves all other bits. 1982 ******************************************************************************/ 1983 void cm_write_scr_el3_bit(uint32_t security_state, 1984 uint32_t bit_pos, 1985 uint32_t value) 1986 { 1987 cpu_context_t *ctx; 1988 el3_state_t *state; 1989 u_register_t scr_el3; 1990 1991 ctx = cm_get_context(security_state); 1992 assert(ctx != NULL); 1993 1994 /* Ensure that the bit position is a valid one */ 1995 assert(((1UL << bit_pos) & SCR_VALID_BIT_MASK) != 0U); 1996 1997 /* Ensure that the 'value' is only a bit wide */ 1998 assert(value <= 1U); 1999 2000 /* 2001 * Get the SCR_EL3 value from the cpu context, clear the desired bit 2002 * and set it to its new value. 2003 */ 2004 state = get_el3state_ctx(ctx); 2005 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); 2006 scr_el3 &= ~(1UL << bit_pos); 2007 scr_el3 |= (u_register_t)value << bit_pos; 2008 write_ctx_reg(state, CTX_SCR_EL3, scr_el3); 2009 } 2010 2011 /******************************************************************************* 2012 * This function retrieves SCR_EL3 member of 'cpu_context' pertaining to the 2013 * given security state. 2014 ******************************************************************************/ 2015 u_register_t cm_get_scr_el3(uint32_t security_state) 2016 { 2017 const cpu_context_t *ctx; 2018 const el3_state_t *state; 2019 2020 ctx = cm_get_context(security_state); 2021 assert(ctx != NULL); 2022 2023 /* Populate EL3 state so that ERET jumps to the correct entry */ 2024 state = get_el3state_ctx(ctx); 2025 return read_ctx_reg(state, CTX_SCR_EL3); 2026 } 2027 2028 /******************************************************************************* 2029 * This function is used to program the context that's used for exception 2030 * return. This initializes the SP_EL3 to a pointer to a 'cpu_context' set for 2031 * the required security state 2032 ******************************************************************************/ 2033 void cm_set_next_eret_context(uint32_t security_state) 2034 { 2035 cpu_context_t *ctx; 2036 2037 ctx = cm_get_context(security_state); 2038 assert(ctx != NULL); 2039 2040 cm_set_next_context(ctx); 2041 } 2042