1 /* 2 * Copyright (c) 2019-2023, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2019-2023, Intel Corporation. All rights reserved. 4 * Copyright (c) 2024-2025, Altera Corporation. All rights reserved. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #include <assert.h> 10 #include <common/debug.h> 11 #include <common/runtime_svc.h> 12 #include <lib/mmio.h> 13 #include <tools_share/uuid.h> 14 15 #include "socfpga_fcs.h" 16 #include "socfpga_mailbox.h" 17 #include "socfpga_plat_def.h" 18 #include "socfpga_reset_manager.h" 19 #include "socfpga_sip_svc.h" 20 #include "socfpga_system_manager.h" 21 22 /* Total buffer the driver can hold */ 23 #define FPGA_CONFIG_BUFFER_SIZE 4 24 25 static config_type request_type = NO_REQUEST; 26 static int current_block, current_buffer; 27 static int read_block, max_blocks; 28 static uint32_t send_id, rcv_id; 29 static uint32_t bytes_per_block, blocks_submitted; 30 static bool bridge_disable; 31 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 32 static uint32_t g_remapper_bypass; 33 #endif 34 35 /* RSU static variables */ 36 static uint32_t rsu_dcmf_ver[4] = {0}; 37 static uint16_t rsu_dcmf_stat[4] = {0}; 38 static uint32_t rsu_max_retry; 39 40 /* SiP Service UUID */ 41 DEFINE_SVC_UUID2(intl_svc_uid, 42 0xa85273b0, 0xe85a, 0x4862, 0xa6, 0x2a, 43 0xfa, 0x88, 0x88, 0x17, 0x68, 0x81); 44 45 static uint64_t socfpga_sip_handler(uint32_t smc_fid, 46 uint64_t x1, 47 uint64_t x2, 48 uint64_t x3, 49 uint64_t x4, 50 void *cookie, 51 void *handle, 52 uint64_t flags) 53 { 54 ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid); 55 SMC_RET1(handle, SMC_UNK); 56 } 57 58 struct fpga_config_info fpga_config_buffers[FPGA_CONFIG_BUFFER_SIZE]; 59 60 static int intel_fpga_sdm_write_buffer(struct fpga_config_info *buffer) 61 { 62 uint32_t args[3]; 63 64 while (max_blocks > 0 && buffer->size > buffer->size_written) { 65 args[0] = (1<<8); 66 args[1] = buffer->addr + buffer->size_written; 67 if (buffer->size - buffer->size_written <= bytes_per_block) { 68 args[2] = buffer->size - buffer->size_written; 69 current_buffer++; 70 current_buffer %= FPGA_CONFIG_BUFFER_SIZE; 71 } else { 72 args[2] = bytes_per_block; 73 } 74 75 buffer->size_written += args[2]; 76 mailbox_send_cmd_async(&send_id, MBOX_RECONFIG_DATA, args, 77 3U, CMD_INDIRECT); 78 79 buffer->subblocks_sent++; 80 max_blocks--; 81 } 82 83 return !max_blocks; 84 } 85 86 static int intel_fpga_sdm_write_all(void) 87 { 88 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 89 if (intel_fpga_sdm_write_buffer( 90 &fpga_config_buffers[current_buffer])) { 91 break; 92 } 93 } 94 return 0; 95 } 96 97 static uint32_t intel_mailbox_fpga_config_isdone(uint32_t *err_states) 98 { 99 uint32_t ret; 100 101 if (err_states == NULL) 102 return INTEL_SIP_SMC_STATUS_REJECTED; 103 104 switch (request_type) { 105 case RECONFIGURATION: 106 ret = intel_mailbox_get_config_status(MBOX_RECONFIG_STATUS, 107 true, err_states); 108 break; 109 case BITSTREAM_AUTH: 110 ret = intel_mailbox_get_config_status(MBOX_RECONFIG_STATUS, 111 false, err_states); 112 break; 113 default: 114 ret = intel_mailbox_get_config_status(MBOX_CONFIG_STATUS, 115 false, err_states); 116 break; 117 } 118 119 if (ret != 0U) { 120 if (ret == MBOX_CFGSTAT_STATE_CONFIG) { 121 return INTEL_SIP_SMC_STATUS_BUSY; 122 } else { 123 request_type = NO_REQUEST; 124 return INTEL_SIP_SMC_STATUS_ERROR; 125 } 126 } 127 128 if (bridge_disable != 0U) { 129 socfpga_bridges_enable(~0); /* Enable bridge */ 130 bridge_disable = false; 131 } 132 request_type = NO_REQUEST; 133 134 return INTEL_SIP_SMC_STATUS_OK; 135 } 136 137 static int mark_last_buffer_xfer_completed(uint32_t *buffer_addr_completed) 138 { 139 int i; 140 141 for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 142 if (fpga_config_buffers[i].block_number == current_block) { 143 fpga_config_buffers[i].subblocks_sent--; 144 if (fpga_config_buffers[i].subblocks_sent == 0 145 && fpga_config_buffers[i].size <= 146 fpga_config_buffers[i].size_written) { 147 fpga_config_buffers[i].write_requested = 0; 148 current_block++; 149 *buffer_addr_completed = 150 fpga_config_buffers[i].addr; 151 return 0; 152 } 153 } 154 } 155 156 return -1; 157 } 158 159 static int intel_fpga_config_completed_write(uint32_t *completed_addr, 160 uint32_t *count, uint32_t *job_id) 161 { 162 uint32_t resp[5]; 163 unsigned int resp_len = ARRAY_SIZE(resp); 164 int status = INTEL_SIP_SMC_STATUS_OK; 165 int all_completed = 1; 166 *count = 0; 167 168 while (*count < 3) { 169 170 status = mailbox_read_response(job_id, 171 resp, &resp_len); 172 173 if (status < 0) { 174 break; 175 } 176 177 max_blocks++; 178 179 if (mark_last_buffer_xfer_completed( 180 &completed_addr[*count]) == 0) { 181 *count = *count + 1; 182 } else { 183 break; 184 } 185 } 186 187 if (*count <= 0) { 188 if (status != MBOX_NO_RESPONSE && 189 status != MBOX_TIMEOUT && resp_len != 0) { 190 mailbox_clear_response(); 191 request_type = NO_REQUEST; 192 return INTEL_SIP_SMC_STATUS_ERROR; 193 } 194 195 *count = 0; 196 } 197 198 intel_fpga_sdm_write_all(); 199 200 if (*count > 0) { 201 status = INTEL_SIP_SMC_STATUS_OK; 202 } else if (*count == 0) { 203 status = INTEL_SIP_SMC_STATUS_BUSY; 204 } 205 206 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 207 if (fpga_config_buffers[i].write_requested != 0) { 208 all_completed = 0; 209 break; 210 } 211 } 212 213 if (all_completed == 1) { 214 return INTEL_SIP_SMC_STATUS_OK; 215 } 216 217 return status; 218 } 219 220 static int intel_fpga_config_start(uint32_t flag) 221 { 222 uint32_t argument = 0x1; 223 uint32_t response[3]; 224 int status = 0; 225 unsigned int size = 0; 226 unsigned int resp_len = ARRAY_SIZE(response); 227 228 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 229 /* 230 * To trigger isolation 231 * FPGA configuration complete signal should be de-asserted 232 */ 233 INFO("SOCFPGA: Request SDM to trigger isolation\n"); 234 status = mailbox_send_fpga_config_comp(); 235 236 if (status < 0) { 237 INFO("SOCFPGA: Isolation for FPGA configuration complete is not executed\n"); 238 } 239 #endif 240 241 request_type = RECONFIGURATION; 242 243 if (!CONFIG_TEST_FLAG(flag, PARTIAL_CONFIG)) { 244 bridge_disable = true; 245 } 246 247 if (CONFIG_TEST_FLAG(flag, AUTHENTICATION)) { 248 size = 1; 249 bridge_disable = false; 250 request_type = BITSTREAM_AUTH; 251 } 252 253 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 254 intel_smmu_hps_remapper_init(0U); 255 #endif 256 257 mailbox_clear_response(); 258 259 mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_CANCEL, NULL, 0U, 260 CMD_CASUAL, NULL, NULL); 261 262 status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_RECONFIG, &argument, size, 263 CMD_CASUAL, response, &resp_len); 264 265 if (status < 0) { 266 bridge_disable = false; 267 request_type = NO_REQUEST; 268 return INTEL_SIP_SMC_STATUS_ERROR; 269 } 270 271 max_blocks = response[0]; 272 bytes_per_block = response[1]; 273 274 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 275 fpga_config_buffers[i].size = 0; 276 fpga_config_buffers[i].size_written = 0; 277 fpga_config_buffers[i].addr = 0; 278 fpga_config_buffers[i].write_requested = 0; 279 fpga_config_buffers[i].block_number = 0; 280 fpga_config_buffers[i].subblocks_sent = 0; 281 } 282 283 blocks_submitted = 0; 284 current_block = 0; 285 read_block = 0; 286 current_buffer = 0; 287 288 /* Disable bridge on full reconfiguration */ 289 if (bridge_disable) { 290 socfpga_bridges_disable(~0); 291 } 292 293 return INTEL_SIP_SMC_STATUS_OK; 294 } 295 296 static bool is_fpga_config_buffer_full(void) 297 { 298 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 299 if (!fpga_config_buffers[i].write_requested) { 300 return false; 301 } 302 } 303 return true; 304 } 305 306 bool is_address_in_ddr_range(uint64_t addr, uint64_t size) 307 { 308 uint128_t dram_max_sz = (uint128_t)DRAM_BASE + (uint128_t)DRAM_SIZE; 309 uint128_t dram_region_end = (uint128_t)addr + (uint128_t)size; 310 311 if (!addr && !size) { 312 return true; 313 } 314 if (size > (UINT64_MAX - addr)) { 315 return false; 316 } 317 if (addr < BL31_LIMIT) { 318 return false; 319 } 320 if (dram_region_end > dram_max_sz) { 321 return false; 322 } 323 324 return true; 325 } 326 327 static uint32_t intel_fpga_config_write(uint64_t mem, uint64_t size) 328 { 329 int i; 330 331 intel_fpga_sdm_write_all(); 332 333 if (!is_address_in_ddr_range(mem, size) || 334 is_fpga_config_buffer_full()) { 335 return INTEL_SIP_SMC_STATUS_REJECTED; 336 } 337 338 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 339 intel_smmu_hps_remapper_init(&mem); 340 #endif 341 342 for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 343 int j = (i + current_buffer) % FPGA_CONFIG_BUFFER_SIZE; 344 345 if (!fpga_config_buffers[j].write_requested) { 346 fpga_config_buffers[j].addr = mem; 347 fpga_config_buffers[j].size = size; 348 fpga_config_buffers[j].size_written = 0; 349 fpga_config_buffers[j].write_requested = 1; 350 fpga_config_buffers[j].block_number = 351 blocks_submitted++; 352 fpga_config_buffers[j].subblocks_sent = 0; 353 break; 354 } 355 } 356 357 if (is_fpga_config_buffer_full()) { 358 return INTEL_SIP_SMC_STATUS_BUSY; 359 } 360 361 return INTEL_SIP_SMC_STATUS_OK; 362 } 363 364 static int is_out_of_sec_range(uint64_t reg_addr) 365 { 366 #if DEBUG 367 return 0; 368 #endif 369 370 #if PLATFORM_MODEL != PLAT_SOCFPGA_AGILEX5 371 switch (reg_addr) { 372 case(0xF8011100): /* ECCCTRL1 */ 373 case(0xF8011104): /* ECCCTRL2 */ 374 case(0xF8011110): /* ERRINTEN */ 375 case(0xF8011114): /* ERRINTENS */ 376 case(0xF8011118): /* ERRINTENR */ 377 case(0xF801111C): /* INTMODE */ 378 case(0xF8011120): /* INTSTAT */ 379 case(0xF8011124): /* DIAGINTTEST */ 380 case(0xF801112C): /* DERRADDRA */ 381 case(0xFA000000): /* SMMU SCR0 */ 382 case(0xFA000004): /* SMMU SCR1 */ 383 case(0xFA000400): /* SMMU NSCR0 */ 384 case(0xFA004000): /* SMMU SSD0_REG */ 385 case(0xFA000820): /* SMMU SMR8 */ 386 case(0xFA000c20): /* SMMU SCR8 */ 387 case(0xFA028000): /* SMMU CB8_SCTRL */ 388 case(0xFA001020): /* SMMU CBAR8 */ 389 case(0xFA028030): /* SMMU TCR_LPAE */ 390 case(0xFA028020): /* SMMU CB8_TTBR0_LOW */ 391 case(0xFA028024): /* SMMU CB8_PRRR_HIGH */ 392 case(0xFA028038): /* SMMU CB8_PRRR_MIR0 */ 393 case(0xFA02803C): /* SMMU CB8_PRRR_MIR1 */ 394 case(0xFA028010): /* SMMU_CB8)TCR2 */ 395 case(0xFFD080A4): /* SDM SMMU STREAM ID REG */ 396 case(0xFA001820): /* SMMU_CBA2R8 */ 397 case(0xFA000074): /* SMMU_STLBGSTATUS */ 398 case(0xFA0287F4): /* SMMU_CB8_TLBSTATUS */ 399 case(0xFA000060): /* SMMU_STLBIALL */ 400 case(0xFA000070): /* SMMU_STLBGSYNC */ 401 case(0xFA028618): /* CB8_TLBALL */ 402 case(0xFA0287F0): /* CB8_TLBSYNC */ 403 case(0xFFD12028): /* SDMMCGRP_CTRL */ 404 case(0xFFD12044): /* EMAC0 */ 405 case(0xFFD12048): /* EMAC1 */ 406 case(0xFFD1204C): /* EMAC2 */ 407 case(0xFFD12090): /* ECC_INT_MASK_VALUE */ 408 case(0xFFD12094): /* ECC_INT_MASK_SET */ 409 case(0xFFD12098): /* ECC_INT_MASK_CLEAR */ 410 case(0xFFD1209C): /* ECC_INTSTATUS_SERR */ 411 case(0xFFD120A0): /* ECC_INTSTATUS_DERR */ 412 case(0xFFD120C0): /* NOC_TIMEOUT */ 413 case(0xFFD120C4): /* NOC_IDLEREQ_SET */ 414 case(0xFFD120C8): /* NOC_IDLEREQ_CLR */ 415 case(0xFFD120D0): /* NOC_IDLEACK */ 416 case(0xFFD120D4): /* NOC_IDLESTATUS */ 417 case(0xFFD12200): /* BOOT_SCRATCH_COLD0 */ 418 case(0xFFD12204): /* BOOT_SCRATCH_COLD1 */ 419 case(0xFFD12220): /* BOOT_SCRATCH_COLD8 */ 420 case(0xFFD12224): /* BOOT_SCRATCH_COLD9 */ 421 return 0; 422 #else 423 switch (reg_addr) { 424 425 case(0xF8011104): /* ECCCTRL2 */ 426 case(0xFFD12028): /* SDMMCGRP_CTRL */ 427 case(0xFFD120C4): /* NOC_IDLEREQ_SET */ 428 case(0xFFD120C8): /* NOC_IDLEREQ_CLR */ 429 case(0xFFD120D0): /* NOC_IDLEACK */ 430 431 432 case(SOCFPGA_MEMCTRL(ECCCTRL1)): /* ECCCTRL1 */ 433 case(SOCFPGA_MEMCTRL(ERRINTEN)): /* ERRINTEN */ 434 case(SOCFPGA_MEMCTRL(ERRINTENS)): /* ERRINTENS */ 435 case(SOCFPGA_MEMCTRL(ERRINTENR)): /* ERRINTENR */ 436 case(SOCFPGA_MEMCTRL(INTMODE)): /* INTMODE */ 437 case(SOCFPGA_MEMCTRL(INTSTAT)): /* INTSTAT */ 438 case(SOCFPGA_MEMCTRL(DIAGINTTEST)): /* DIAGINTTEST */ 439 case(SOCFPGA_MEMCTRL(DERRADDRA)): /* DERRADDRA */ 440 441 case(SOCFPGA_ECC_QSPI(INITSTAT)): /* ECC_QSPI_INITSTAT */ 442 case(SOCFPGA_SYSMGR(EMAC_0)): /* EMAC0 */ 443 case(SOCFPGA_SYSMGR(EMAC_1)): /* EMAC1 */ 444 case(SOCFPGA_SYSMGR(EMAC_2)): /* EMAC2 */ 445 case(SOCFPGA_SYSMGR(ECC_INTMASK_VALUE)): /* ECC_INT_MASK_VALUE */ 446 case(SOCFPGA_SYSMGR(ECC_INTMASK_SET)): /* ECC_INT_MASK_SET */ 447 case(SOCFPGA_SYSMGR(ECC_INTMASK_CLR)): /* ECC_INT_MASK_CLEAR */ 448 case(SOCFPGA_SYSMGR(ECC_INTMASK_SERR)): /* ECC_INTSTATUS_SERR */ 449 case(SOCFPGA_SYSMGR(ECC_INTMASK_DERR)): /* ECC_INTSTATUS_DERR */ 450 case(SOCFPGA_SYSMGR(NOC_TIMEOUT)): /* NOC_TIMEOUT */ 451 case(SOCFPGA_SYSMGR(NOC_IDLESTATUS)): /* NOC_IDLESTATUS */ 452 case(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_0)): /* BOOT_SCRATCH_COLD0 */ 453 case(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_1)): /* BOOT_SCRATCH_COLD1 */ 454 case(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_8)): /* BOOT_SCRATCH_COLD8 */ 455 case(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_9)): /* BOOT_SCRATCH_COLD9 */ 456 #endif 457 case(SOCFPGA_ECC_QSPI(CTRL)): /* ECC_QSPI_CTRL */ 458 case(SOCFPGA_ECC_QSPI(ERRINTEN)): /* ECC_QSPI_ERRINTEN */ 459 case(SOCFPGA_ECC_QSPI(ERRINTENS)): /* ECC_QSPI_ERRINTENS */ 460 case(SOCFPGA_ECC_QSPI(ERRINTENR)): /* ECC_QSPI_ERRINTENR */ 461 case(SOCFPGA_ECC_QSPI(INTMODE)): /* ECC_QSPI_INTMODE */ 462 case(SOCFPGA_ECC_QSPI(ECC_ACCCTRL)): /* ECC_QSPI_ECC_ACCCTRL */ 463 case(SOCFPGA_ECC_QSPI(ECC_STARTACC)): /* ECC_QSPI_ECC_STARTACC */ 464 case(SOCFPGA_ECC_QSPI(ECC_WDCTRL)): /* ECC_QSPI_ECC_WDCTRL */ 465 case(SOCFPGA_ECC_QSPI(INTSTAT)): /* ECC_QSPI_INTSTAT */ 466 case(SOCFPGA_ECC_QSPI(INTTEST)): /* ECC_QSPI_INTMODE */ 467 return 0; 468 469 default: 470 break; 471 } 472 473 return -1; 474 } 475 476 /* Secure register access */ 477 uint32_t intel_secure_reg_read(uint64_t reg_addr, uint32_t *retval) 478 { 479 if (is_out_of_sec_range(reg_addr)) { 480 return INTEL_SIP_SMC_STATUS_ERROR; 481 } 482 483 *retval = mmio_read_32(reg_addr); 484 485 return INTEL_SIP_SMC_STATUS_OK; 486 } 487 488 uint32_t intel_secure_reg_write(uint64_t reg_addr, uint32_t val, 489 uint32_t *retval) 490 { 491 if (is_out_of_sec_range(reg_addr)) { 492 return INTEL_SIP_SMC_STATUS_ERROR; 493 } 494 495 switch (reg_addr) { 496 case(SOCFPGA_ECC_QSPI(INTSTAT)): /* ECC_QSPI_INTSTAT */ 497 case(SOCFPGA_ECC_QSPI(INTTEST)): /* ECC_QSPI_INTMODE */ 498 mmio_write_16(reg_addr, val); 499 break; 500 default: 501 mmio_write_32(reg_addr, val); 502 break; 503 } 504 505 return intel_secure_reg_read(reg_addr, retval); 506 } 507 508 uint32_t intel_secure_reg_update(uint64_t reg_addr, uint32_t mask, 509 uint32_t val, uint32_t *retval) 510 { 511 if (!intel_secure_reg_read(reg_addr, retval)) { 512 *retval &= ~mask; 513 *retval |= val & mask; 514 return intel_secure_reg_write(reg_addr, *retval, retval); 515 } 516 517 return INTEL_SIP_SMC_STATUS_ERROR; 518 } 519 520 /* Intel Remote System Update (RSU) services */ 521 uint64_t intel_rsu_update_address; 522 523 static uint32_t intel_rsu_status(uint64_t *respbuf, unsigned int respbuf_sz) 524 { 525 if (mailbox_rsu_status((uint32_t *)respbuf, respbuf_sz) < 0) { 526 return INTEL_SIP_SMC_RSU_ERROR; 527 } 528 529 return INTEL_SIP_SMC_STATUS_OK; 530 } 531 532 static uint32_t intel_rsu_get_device_info(uint32_t *respbuf, 533 unsigned int respbuf_sz) 534 { 535 if (mailbox_rsu_get_device_info((uint32_t *)respbuf, respbuf_sz) < 0) { 536 return INTEL_SIP_SMC_RSU_ERROR; 537 } 538 539 return INTEL_SIP_SMC_STATUS_OK; 540 } 541 542 uint32_t intel_rsu_update(uint64_t update_address) 543 { 544 if (update_address > SIZE_MAX) { 545 return INTEL_SIP_SMC_STATUS_REJECTED; 546 } 547 548 intel_rsu_update_address = update_address; 549 return INTEL_SIP_SMC_STATUS_OK; 550 } 551 552 static uint32_t intel_rsu_notify(uint32_t execution_stage) 553 { 554 if (mailbox_hps_stage_notify(execution_stage) < 0) { 555 return INTEL_SIP_SMC_RSU_ERROR; 556 } 557 558 return INTEL_SIP_SMC_STATUS_OK; 559 } 560 561 static uint32_t intel_rsu_retry_counter(uint32_t *respbuf, uint32_t respbuf_sz, 562 uint32_t *ret_stat) 563 { 564 if (mailbox_rsu_status((uint32_t *)respbuf, respbuf_sz) < 0) { 565 return INTEL_SIP_SMC_RSU_ERROR; 566 } 567 568 *ret_stat = respbuf[8]; 569 return INTEL_SIP_SMC_STATUS_OK; 570 } 571 572 static uint32_t intel_rsu_copy_dcmf_version(uint64_t dcmf_ver_1_0, 573 uint64_t dcmf_ver_3_2) 574 { 575 rsu_dcmf_ver[0] = dcmf_ver_1_0; 576 rsu_dcmf_ver[1] = dcmf_ver_1_0 >> 32; 577 rsu_dcmf_ver[2] = dcmf_ver_3_2; 578 rsu_dcmf_ver[3] = dcmf_ver_3_2 >> 32; 579 580 return INTEL_SIP_SMC_STATUS_OK; 581 } 582 583 static uint32_t intel_rsu_copy_dcmf_status(uint64_t dcmf_stat) 584 { 585 rsu_dcmf_stat[0] = 0xFFFF & (dcmf_stat >> (0 * 16)); 586 rsu_dcmf_stat[1] = 0xFFFF & (dcmf_stat >> (1 * 16)); 587 rsu_dcmf_stat[2] = 0xFFFF & (dcmf_stat >> (2 * 16)); 588 rsu_dcmf_stat[3] = 0xFFFF & (dcmf_stat >> (3 * 16)); 589 590 return INTEL_SIP_SMC_STATUS_OK; 591 } 592 593 /* Intel HWMON services */ 594 static uint32_t intel_hwmon_readtemp(uint32_t chan, uint32_t *retval) 595 { 596 if (mailbox_hwmon_readtemp(chan, retval) < 0) { 597 return INTEL_SIP_SMC_STATUS_ERROR; 598 } 599 600 return INTEL_SIP_SMC_STATUS_OK; 601 } 602 603 static uint32_t intel_hwmon_readvolt(uint32_t chan, uint32_t *retval) 604 { 605 if (mailbox_hwmon_readvolt(chan, retval) < 0) { 606 return INTEL_SIP_SMC_STATUS_ERROR; 607 } 608 609 return INTEL_SIP_SMC_STATUS_OK; 610 } 611 612 /* Mailbox services */ 613 static uint32_t intel_smc_fw_version(uint32_t *fw_version) 614 { 615 int status; 616 unsigned int resp_len = CONFIG_STATUS_WORD_SIZE; 617 uint32_t resp_data[CONFIG_STATUS_WORD_SIZE] = {0U}; 618 619 status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_CONFIG_STATUS, NULL, 0U, 620 CMD_CASUAL, resp_data, &resp_len); 621 622 if (status < 0) { 623 return INTEL_SIP_SMC_STATUS_ERROR; 624 } 625 626 if (resp_len <= CONFIG_STATUS_FW_VER_OFFSET) { 627 return INTEL_SIP_SMC_STATUS_ERROR; 628 } 629 630 *fw_version = resp_data[CONFIG_STATUS_FW_VER_OFFSET] & CONFIG_STATUS_FW_VER_MASK; 631 632 return INTEL_SIP_SMC_STATUS_OK; 633 } 634 635 static uint32_t intel_mbox_send_cmd(uint32_t cmd, uint32_t *args, 636 unsigned int len, uint32_t urgent, uint64_t response, 637 unsigned int resp_len, int *mbox_status, 638 unsigned int *len_in_resp) 639 { 640 *len_in_resp = 0; 641 *mbox_status = GENERIC_RESPONSE_ERROR; 642 643 if (!is_address_in_ddr_range((uint64_t)args, sizeof(uint32_t) * len)) { 644 return INTEL_SIP_SMC_STATUS_REJECTED; 645 } 646 647 int status = mailbox_send_cmd(MBOX_JOB_ID, cmd, args, len, urgent, 648 (uint32_t *) response, &resp_len); 649 650 if (status < 0) { 651 *mbox_status = -status; 652 return INTEL_SIP_SMC_STATUS_ERROR; 653 } 654 655 *mbox_status = 0; 656 *len_in_resp = resp_len; 657 658 flush_dcache_range(response, resp_len * MBOX_WORD_BYTE); 659 660 return INTEL_SIP_SMC_STATUS_OK; 661 } 662 663 static int intel_smc_get_usercode(uint32_t *user_code) 664 { 665 int status; 666 unsigned int resp_len = sizeof(user_code) / MBOX_WORD_BYTE; 667 668 status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_GET_USERCODE, NULL, 669 0U, CMD_CASUAL, user_code, &resp_len); 670 671 if (status < 0) { 672 return INTEL_SIP_SMC_STATUS_ERROR; 673 } 674 675 return INTEL_SIP_SMC_STATUS_OK; 676 } 677 678 uint32_t intel_smc_service_completed(uint64_t addr, uint32_t size, 679 uint32_t mode, uint32_t *job_id, 680 uint32_t *ret_size, uint32_t *mbox_error) 681 { 682 int status = 0; 683 uint32_t resp_len = size / MBOX_WORD_BYTE; 684 685 if (resp_len > MBOX_DATA_MAX_LEN) { 686 return INTEL_SIP_SMC_STATUS_REJECTED; 687 } 688 689 if (!is_address_in_ddr_range(addr, size)) { 690 return INTEL_SIP_SMC_STATUS_REJECTED; 691 } 692 693 if (mode == SERVICE_COMPLETED_MODE_ASYNC) { 694 status = mailbox_read_response_async(job_id, 695 NULL, (uint32_t *) addr, &resp_len, 0); 696 } else { 697 status = mailbox_read_response(job_id, 698 (uint32_t *) addr, &resp_len); 699 700 if (status == MBOX_NO_RESPONSE) { 701 status = MBOX_BUSY; 702 } 703 } 704 705 if (status == MBOX_NO_RESPONSE) { 706 return INTEL_SIP_SMC_STATUS_NO_RESPONSE; 707 } 708 709 if (status == MBOX_BUSY) { 710 return INTEL_SIP_SMC_STATUS_BUSY; 711 } 712 713 *ret_size = resp_len * MBOX_WORD_BYTE; 714 flush_dcache_range(addr, *ret_size); 715 716 if (status == MBOX_RET_SDOS_DECRYPTION_ERROR_102 || 717 status == MBOX_RET_SDOS_DECRYPTION_ERROR_103) { 718 *mbox_error = -status; 719 } else if (status != MBOX_RET_OK) { 720 *mbox_error = -status; 721 return INTEL_SIP_SMC_STATUS_ERROR; 722 } 723 724 return INTEL_SIP_SMC_STATUS_OK; 725 } 726 727 /* Miscellaneous HPS services */ 728 uint32_t intel_hps_set_bridges(uint64_t enable, uint64_t mask) 729 { 730 int status = 0; 731 732 if ((enable & SOCFPGA_BRIDGE_ENABLE) != 0U) { 733 if ((enable & SOCFPGA_BRIDGE_HAS_MASK) != 0U) { 734 status = socfpga_bridges_enable((uint32_t)mask); 735 } else { 736 status = socfpga_bridges_enable(~0); 737 } 738 } else { 739 if ((enable & SOCFPGA_BRIDGE_HAS_MASK) != 0U) { 740 status = socfpga_bridges_disable((uint32_t)mask); 741 } else { 742 status = socfpga_bridges_disable(~0); 743 } 744 } 745 746 if (status < 0) { 747 return INTEL_SIP_SMC_STATUS_ERROR; 748 } 749 750 return INTEL_SIP_SMC_STATUS_OK; 751 } 752 753 /* SDM SEU Error services */ 754 static uint32_t intel_sdm_seu_err_read(uint32_t *respbuf, unsigned int respbuf_sz) 755 { 756 if (mailbox_seu_err_status(respbuf, respbuf_sz) < 0) { 757 return INTEL_SIP_SMC_SEU_ERR_READ_ERROR; 758 } 759 760 return INTEL_SIP_SMC_STATUS_OK; 761 } 762 763 /* SDM SAFE SEU Error inject services */ 764 static uint32_t intel_sdm_safe_inject_seu_err(uint32_t *command, uint32_t len) 765 { 766 if (mailbox_safe_inject_seu_err(command, len) < 0) { 767 return INTEL_SIP_SMC_SEU_ERR_READ_ERROR; 768 } 769 770 return INTEL_SIP_SMC_STATUS_OK; 771 } 772 773 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 774 /* SMMU HPS Remapper */ 775 void intel_smmu_hps_remapper_init(uint64_t *mem) 776 { 777 /* Read out Bit 1 value */ 778 uint32_t remap = (mmio_read_32(SOCFPGA_SYSMGR(BOOT_SCRATCH_POR_1)) & 0x02); 779 780 if ((remap == 0x00) && (g_remapper_bypass == 0x00)) { 781 /* Update DRAM Base address for SDM SMMU */ 782 mmio_write_32(SOCFPGA_SYSMGR(SDM_BE_ARADDR_REMAP), DRAM_BASE); 783 mmio_write_32(SOCFPGA_SYSMGR(SDM_BE_AWADDR_REMAP), DRAM_BASE); 784 *mem = *mem - DRAM_BASE; 785 } else { 786 *mem = *mem - DRAM_BASE; 787 } 788 } 789 790 int intel_smmu_hps_remapper_config(uint32_t remapper_bypass) 791 { 792 /* Read out the JTAG-ID from boot scratch register */ 793 if (is_agilex5_A5F0() || is_agilex5_A5F4()) { 794 if (remapper_bypass == 0x01) { 795 g_remapper_bypass = remapper_bypass; 796 mmio_write_32(SOCFPGA_SYSMGR(SDM_BE_ARADDR_REMAP), 0); 797 mmio_write_32(SOCFPGA_SYSMGR(SDM_BE_AWADDR_REMAP), 0); 798 } 799 } 800 return INTEL_SIP_SMC_STATUS_OK; 801 } 802 #endif 803 804 /* 805 * This function is responsible for handling all SiP calls from the NS world 806 */ 807 808 uintptr_t sip_smc_handler_v1(uint32_t smc_fid, 809 u_register_t x1, 810 u_register_t x2, 811 u_register_t x3, 812 u_register_t x4, 813 void *cookie, 814 void *handle, 815 u_register_t flags) 816 { 817 uint32_t retval = 0, completed_addr[3]; 818 uint32_t retval2 = 0; 819 uint32_t mbox_error = 0; 820 uint32_t err_states = 0; 821 uint64_t retval64, rsu_respbuf[9]; 822 uint32_t seu_respbuf[3]; 823 int status = INTEL_SIP_SMC_STATUS_OK; 824 int mbox_status; 825 unsigned int len_in_resp; 826 u_register_t x5, x6, x7; 827 828 switch (smc_fid) { 829 case SIP_SVC_UID: 830 /* Return UID to the caller */ 831 SMC_UUID_RET(handle, intl_svc_uid); 832 833 case INTEL_SIP_SMC_FPGA_CONFIG_ISDONE: 834 status = intel_mailbox_fpga_config_isdone(&err_states); 835 SMC_RET4(handle, status, err_states, 0, 0); 836 837 case INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM: 838 SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK, 839 INTEL_SIP_SMC_FPGA_CONFIG_ADDR, 840 INTEL_SIP_SMC_FPGA_CONFIG_SIZE - 841 INTEL_SIP_SMC_FPGA_CONFIG_ADDR); 842 843 case INTEL_SIP_SMC_FPGA_CONFIG_START: 844 status = intel_fpga_config_start(x1); 845 SMC_RET4(handle, status, 0, 0, 0); 846 847 case INTEL_SIP_SMC_FPGA_CONFIG_WRITE: 848 status = intel_fpga_config_write(x1, x2); 849 SMC_RET4(handle, status, 0, 0, 0); 850 851 case INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE: 852 status = intel_fpga_config_completed_write(completed_addr, 853 &retval, &rcv_id); 854 switch (retval) { 855 case 1: 856 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, 857 completed_addr[0], 0, 0); 858 859 case 2: 860 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, 861 completed_addr[0], 862 completed_addr[1], 0); 863 864 case 3: 865 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, 866 completed_addr[0], 867 completed_addr[1], 868 completed_addr[2]); 869 870 case 0: 871 SMC_RET4(handle, status, 0, 0, 0); 872 873 default: 874 mailbox_clear_response(); 875 SMC_RET1(handle, INTEL_SIP_SMC_STATUS_ERROR); 876 } 877 878 case INTEL_SIP_SMC_REG_READ: 879 status = intel_secure_reg_read(x1, &retval); 880 SMC_RET3(handle, status, retval, x1); 881 882 case INTEL_SIP_SMC_REG_WRITE: 883 status = intel_secure_reg_write(x1, (uint32_t)x2, &retval); 884 SMC_RET3(handle, status, retval, x1); 885 886 case INTEL_SIP_SMC_REG_UPDATE: 887 status = intel_secure_reg_update(x1, (uint32_t)x2, 888 (uint32_t)x3, &retval); 889 SMC_RET3(handle, status, retval, x1); 890 891 case INTEL_SIP_SMC_RSU_STATUS: 892 status = intel_rsu_status(rsu_respbuf, 893 ARRAY_SIZE(rsu_respbuf)); 894 if (status) { 895 SMC_RET1(handle, status); 896 } else { 897 SMC_RET4(handle, rsu_respbuf[0], rsu_respbuf[1], 898 rsu_respbuf[2], rsu_respbuf[3]); 899 } 900 901 case INTEL_SIP_SMC_RSU_UPDATE: 902 status = intel_rsu_update(x1); 903 SMC_RET1(handle, status); 904 905 case INTEL_SIP_SMC_RSU_NOTIFY: 906 status = intel_rsu_notify(x1); 907 SMC_RET1(handle, status); 908 909 case INTEL_SIP_SMC_RSU_RETRY_COUNTER: 910 status = intel_rsu_retry_counter((uint32_t *)rsu_respbuf, 911 ARRAY_SIZE(rsu_respbuf), &retval); 912 if (status) { 913 SMC_RET1(handle, status); 914 } else { 915 SMC_RET2(handle, status, retval); 916 } 917 918 case INTEL_SIP_SMC_RSU_DCMF_VERSION: 919 SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK, 920 ((uint64_t)rsu_dcmf_ver[1] << 32) | rsu_dcmf_ver[0], 921 ((uint64_t)rsu_dcmf_ver[3] << 32) | rsu_dcmf_ver[2]); 922 923 case INTEL_SIP_SMC_RSU_COPY_DCMF_VERSION: 924 status = intel_rsu_copy_dcmf_version(x1, x2); 925 SMC_RET1(handle, status); 926 927 case INTEL_SIP_SMC_RSU_GET_DEVICE_INFO: 928 status = intel_rsu_get_device_info((uint32_t *)rsu_respbuf, 929 ARRAY_SIZE(rsu_respbuf)); 930 if (status) { 931 SMC_RET1(handle, status); 932 } else { 933 SMC_RET5(handle, status, rsu_respbuf[0], rsu_respbuf[1], 934 rsu_respbuf[2], rsu_respbuf[3]); 935 } 936 937 case INTEL_SIP_SMC_RSU_DCMF_STATUS: 938 SMC_RET2(handle, INTEL_SIP_SMC_STATUS_OK, 939 ((uint64_t)rsu_dcmf_stat[3] << 48) | 940 ((uint64_t)rsu_dcmf_stat[2] << 32) | 941 ((uint64_t)rsu_dcmf_stat[1] << 16) | 942 rsu_dcmf_stat[0]); 943 944 case INTEL_SIP_SMC_RSU_COPY_DCMF_STATUS: 945 status = intel_rsu_copy_dcmf_status(x1); 946 SMC_RET1(handle, status); 947 948 case INTEL_SIP_SMC_RSU_MAX_RETRY: 949 SMC_RET2(handle, INTEL_SIP_SMC_STATUS_OK, rsu_max_retry); 950 951 case INTEL_SIP_SMC_RSU_COPY_MAX_RETRY: 952 rsu_max_retry = x1; 953 SMC_RET1(handle, INTEL_SIP_SMC_STATUS_OK); 954 955 case INTEL_SIP_SMC_ECC_DBE: 956 status = intel_ecc_dbe_notification(x1); 957 SMC_RET1(handle, status); 958 959 case INTEL_SIP_SMC_SERVICE_COMPLETED: 960 status = intel_smc_service_completed(x1, x2, x3, &rcv_id, 961 &len_in_resp, &mbox_error); 962 SMC_RET4(handle, status, mbox_error, x1, len_in_resp); 963 964 case INTEL_SIP_SMC_FIRMWARE_VERSION: 965 status = intel_smc_fw_version(&retval); 966 SMC_RET2(handle, status, retval); 967 968 case INTEL_SIP_SMC_MBOX_SEND_CMD: 969 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 970 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 971 status = intel_mbox_send_cmd(x1, (uint32_t *)x2, x3, x4, x5, x6, 972 &mbox_status, &len_in_resp); 973 SMC_RET3(handle, status, mbox_status, len_in_resp); 974 975 case INTEL_SIP_SMC_GET_USERCODE: 976 status = intel_smc_get_usercode(&retval); 977 SMC_RET2(handle, status, retval); 978 979 case INTEL_SIP_SMC_FCS_CRYPTION: 980 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 981 982 if (x1 == FCS_MODE_DECRYPT) { 983 status = intel_fcs_decryption(x2, x3, x4, x5, &send_id); 984 } else if (x1 == FCS_MODE_ENCRYPT) { 985 status = intel_fcs_encryption(x2, x3, x4, x5, &send_id); 986 } else { 987 status = INTEL_SIP_SMC_STATUS_REJECTED; 988 } 989 990 SMC_RET3(handle, status, x4, x5); 991 992 case INTEL_SIP_SMC_FCS_CRYPTION_EXT: 993 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 994 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 995 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 996 997 if (x3 == FCS_MODE_DECRYPT) { 998 status = intel_fcs_decryption_ext(x1, x2, x4, x5, x6, 999 (uint32_t *) &x7, &mbox_error); 1000 } else if (x3 == FCS_MODE_ENCRYPT) { 1001 status = intel_fcs_encryption_ext(x1, x2, x4, x5, x6, 1002 (uint32_t *) &x7, &mbox_error); 1003 } else { 1004 status = INTEL_SIP_SMC_STATUS_REJECTED; 1005 } 1006 1007 SMC_RET4(handle, status, mbox_error, x6, x7); 1008 1009 case INTEL_SIP_SMC_FCS_RANDOM_NUMBER: 1010 status = intel_fcs_random_number_gen(x1, &retval64, 1011 &mbox_error); 1012 SMC_RET4(handle, status, mbox_error, x1, retval64); 1013 1014 case INTEL_SIP_SMC_FCS_RANDOM_NUMBER_EXT: 1015 status = intel_fcs_random_number_gen_ext(x1, x2, x3, 1016 &send_id); 1017 SMC_RET1(handle, status); 1018 1019 case INTEL_SIP_SMC_FCS_SEND_CERTIFICATE: 1020 status = intel_fcs_send_cert(x1, x2, &send_id); 1021 SMC_RET1(handle, status); 1022 1023 case INTEL_SIP_SMC_FCS_GET_PROVISION_DATA: 1024 status = intel_fcs_get_provision_data(&send_id); 1025 SMC_RET1(handle, status); 1026 1027 case INTEL_SIP_SMC_FCS_CNTR_SET_PREAUTH: 1028 status = intel_fcs_cntr_set_preauth(x1, x2, x3, 1029 &mbox_error); 1030 SMC_RET2(handle, status, mbox_error); 1031 1032 case INTEL_SIP_SMC_HPS_SET_BRIDGES: 1033 status = intel_hps_set_bridges(x1, x2); 1034 SMC_RET1(handle, status); 1035 1036 case INTEL_SIP_SMC_HWMON_READTEMP: 1037 status = intel_hwmon_readtemp(x1, &retval); 1038 SMC_RET2(handle, status, retval); 1039 1040 case INTEL_SIP_SMC_HWMON_READVOLT: 1041 status = intel_hwmon_readvolt(x1, &retval); 1042 SMC_RET2(handle, status, retval); 1043 1044 case INTEL_SIP_SMC_FCS_PSGSIGMA_TEARDOWN: 1045 status = intel_fcs_sigma_teardown(x1, &mbox_error); 1046 SMC_RET2(handle, status, mbox_error); 1047 1048 case INTEL_SIP_SMC_FCS_CHIP_ID: 1049 status = intel_fcs_chip_id(&retval, &retval2, &mbox_error); 1050 SMC_RET4(handle, status, mbox_error, retval, retval2); 1051 1052 case INTEL_SIP_SMC_FCS_ATTESTATION_SUBKEY: 1053 status = intel_fcs_attestation_subkey(x1, x2, x3, 1054 (uint32_t *) &x4, &mbox_error); 1055 SMC_RET4(handle, status, mbox_error, x3, x4); 1056 1057 case INTEL_SIP_SMC_FCS_ATTESTATION_MEASUREMENTS: 1058 status = intel_fcs_get_measurement(x1, x2, x3, 1059 (uint32_t *) &x4, &mbox_error); 1060 SMC_RET4(handle, status, mbox_error, x3, x4); 1061 1062 case INTEL_SIP_SMC_FCS_GET_ATTESTATION_CERT: 1063 status = intel_fcs_get_attestation_cert(x1, x2, 1064 (uint32_t *) &x3, &mbox_error); 1065 SMC_RET4(handle, status, mbox_error, x2, x3); 1066 1067 case INTEL_SIP_SMC_FCS_CREATE_CERT_ON_RELOAD: 1068 status = intel_fcs_create_cert_on_reload(x1, &mbox_error); 1069 SMC_RET2(handle, status, mbox_error); 1070 1071 case INTEL_SIP_SMC_FCS_OPEN_CS_SESSION: 1072 status = intel_fcs_open_crypto_service_session(&retval, &mbox_error); 1073 SMC_RET3(handle, status, mbox_error, retval); 1074 1075 case INTEL_SIP_SMC_FCS_CLOSE_CS_SESSION: 1076 status = intel_fcs_close_crypto_service_session(x1, &mbox_error); 1077 SMC_RET2(handle, status, mbox_error); 1078 1079 case INTEL_SIP_SMC_FCS_IMPORT_CS_KEY: 1080 status = intel_fcs_import_crypto_service_key(x1, x2, &send_id); 1081 SMC_RET1(handle, status); 1082 1083 case INTEL_SIP_SMC_FCS_EXPORT_CS_KEY: 1084 status = intel_fcs_export_crypto_service_key(x1, x2, x3, 1085 (uint32_t *) &x4, &mbox_error); 1086 SMC_RET4(handle, status, mbox_error, x3, x4); 1087 1088 case INTEL_SIP_SMC_FCS_REMOVE_CS_KEY: 1089 status = intel_fcs_remove_crypto_service_key(x1, x2, 1090 &mbox_error); 1091 SMC_RET2(handle, status, mbox_error); 1092 1093 case INTEL_SIP_SMC_FCS_GET_CS_KEY_INFO: 1094 status = intel_fcs_get_crypto_service_key_info(x1, x2, x3, 1095 (uint32_t *) &x4, &mbox_error); 1096 SMC_RET4(handle, status, mbox_error, x3, x4); 1097 1098 case INTEL_SIP_SMC_FCS_GET_DIGEST_INIT: 1099 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1100 status = intel_fcs_get_digest_init(x1, x2, x3, 1101 x4, x5, &mbox_error); 1102 SMC_RET2(handle, status, mbox_error); 1103 1104 case INTEL_SIP_SMC_FCS_GET_DIGEST_UPDATE: 1105 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1106 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1107 status = intel_fcs_get_digest_update_finalize(x1, x2, x3, 1108 x4, x5, (uint32_t *) &x6, false, 1109 &mbox_error); 1110 SMC_RET4(handle, status, mbox_error, x5, x6); 1111 1112 case INTEL_SIP_SMC_FCS_GET_DIGEST_FINALIZE: 1113 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1114 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1115 status = intel_fcs_get_digest_update_finalize(x1, x2, x3, 1116 x4, x5, (uint32_t *) &x6, true, 1117 &mbox_error); 1118 SMC_RET4(handle, status, mbox_error, x5, x6); 1119 1120 case INTEL_SIP_SMC_FCS_GET_DIGEST_SMMU_UPDATE: 1121 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1122 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1123 status = intel_fcs_get_digest_smmu_update_finalize(x1, x2, x3, 1124 x4, x5, (uint32_t *) &x6, false, 1125 &mbox_error, &send_id); 1126 SMC_RET4(handle, status, mbox_error, x5, x6); 1127 1128 case INTEL_SIP_SMC_FCS_GET_DIGEST_SMMU_FINALIZE: 1129 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1130 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1131 status = intel_fcs_get_digest_smmu_update_finalize(x1, x2, x3, 1132 x4, x5, (uint32_t *) &x6, true, 1133 &mbox_error, &send_id); 1134 SMC_RET4(handle, status, mbox_error, x5, x6); 1135 1136 case INTEL_SIP_SMC_FCS_MAC_VERIFY_INIT: 1137 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1138 status = intel_fcs_mac_verify_init(x1, x2, x3, 1139 x4, x5, &mbox_error); 1140 SMC_RET2(handle, status, mbox_error); 1141 1142 case INTEL_SIP_SMC_FCS_MAC_VERIFY_UPDATE: 1143 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1144 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1145 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 1146 status = intel_fcs_mac_verify_update_finalize(x1, x2, x3, 1147 x4, x5, (uint32_t *) &x6, x7, 1148 false, &mbox_error); 1149 SMC_RET4(handle, status, mbox_error, x5, x6); 1150 1151 case INTEL_SIP_SMC_FCS_MAC_VERIFY_FINALIZE: 1152 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1153 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1154 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 1155 status = intel_fcs_mac_verify_update_finalize(x1, x2, x3, 1156 x4, x5, (uint32_t *) &x6, x7, 1157 true, &mbox_error); 1158 SMC_RET4(handle, status, mbox_error, x5, x6); 1159 1160 case INTEL_SIP_SMC_FCS_MAC_VERIFY_SMMU_UPDATE: 1161 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1162 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1163 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 1164 status = intel_fcs_mac_verify_smmu_update_finalize(x1, x2, x3, 1165 x4, x5, (uint32_t *) &x6, x7, 1166 false, &mbox_error, &send_id); 1167 SMC_RET4(handle, status, mbox_error, x5, x6); 1168 1169 case INTEL_SIP_SMC_FCS_MAC_VERIFY_SMMU_FINALIZE: 1170 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1171 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1172 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 1173 status = intel_fcs_mac_verify_smmu_update_finalize(x1, x2, x3, 1174 x4, x5, (uint32_t *) &x6, x7, 1175 true, &mbox_error, &send_id); 1176 SMC_RET4(handle, status, mbox_error, x5, x6); 1177 1178 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_INIT: 1179 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1180 status = intel_fcs_ecdsa_sha2_data_sign_init(x1, x2, x3, 1181 x4, x5, &mbox_error); 1182 SMC_RET2(handle, status, mbox_error); 1183 1184 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_UPDATE: 1185 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1186 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1187 status = intel_fcs_ecdsa_sha2_data_sign_update_finalize(x1, x2, 1188 x3, x4, x5, (uint32_t *) &x6, false, 1189 &mbox_error); 1190 SMC_RET4(handle, status, mbox_error, x5, x6); 1191 1192 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_FINALIZE: 1193 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1194 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1195 status = intel_fcs_ecdsa_sha2_data_sign_update_finalize(x1, x2, 1196 x3, x4, x5, (uint32_t *) &x6, true, 1197 &mbox_error); 1198 SMC_RET4(handle, status, mbox_error, x5, x6); 1199 1200 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_SMMU_UPDATE: 1201 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1202 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1203 status = intel_fcs_ecdsa_sha2_data_sign_smmu_update_finalize(x1, 1204 x2, x3, x4, x5, (uint32_t *) &x6, false, 1205 &mbox_error, &send_id); 1206 SMC_RET4(handle, status, mbox_error, x5, x6); 1207 1208 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_SMMU_FINALIZE: 1209 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1210 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1211 status = intel_fcs_ecdsa_sha2_data_sign_smmu_update_finalize(x1, 1212 x2, x3, x4, x5, (uint32_t *) &x6, true, 1213 &mbox_error, &send_id); 1214 SMC_RET4(handle, status, mbox_error, x5, x6); 1215 1216 case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIGN_INIT: 1217 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1218 status = intel_fcs_ecdsa_hash_sign_init(x1, x2, x3, 1219 x4, x5, &mbox_error); 1220 SMC_RET2(handle, status, mbox_error); 1221 1222 case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIGN_FINALIZE: 1223 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1224 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1225 status = intel_fcs_ecdsa_hash_sign_finalize(x1, x2, x3, 1226 x4, x5, (uint32_t *) &x6, &mbox_error); 1227 SMC_RET4(handle, status, mbox_error, x5, x6); 1228 1229 case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIG_VERIFY_INIT: 1230 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1231 status = intel_fcs_ecdsa_hash_sig_verify_init(x1, x2, x3, 1232 x4, x5, &mbox_error); 1233 SMC_RET2(handle, status, mbox_error); 1234 1235 case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIG_VERIFY_FINALIZE: 1236 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1237 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1238 status = intel_fcs_ecdsa_hash_sig_verify_finalize(x1, x2, x3, 1239 x4, x5, (uint32_t *) &x6, &mbox_error); 1240 SMC_RET4(handle, status, mbox_error, x5, x6); 1241 1242 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_INIT: 1243 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1244 status = intel_fcs_ecdsa_sha2_data_sig_verify_init(x1, x2, x3, 1245 x4, x5, &mbox_error); 1246 SMC_RET2(handle, status, mbox_error); 1247 1248 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_UPDATE: 1249 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1250 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1251 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 1252 status = intel_fcs_ecdsa_sha2_data_sig_verify_update_finalize( 1253 x1, x2, x3, x4, x5, (uint32_t *) &x6, 1254 x7, false, &mbox_error); 1255 SMC_RET4(handle, status, mbox_error, x5, x6); 1256 1257 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_SMMU_UPDATE: 1258 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1259 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1260 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 1261 status = intel_fcs_ecdsa_sha2_data_sig_verify_smmu_update_finalize( 1262 x1, x2, x3, x4, x5, (uint32_t *) &x6, 1263 x7, false, &mbox_error, &send_id); 1264 SMC_RET4(handle, status, mbox_error, x5, x6); 1265 1266 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_SMMU_FINALIZE: 1267 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1268 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1269 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 1270 status = intel_fcs_ecdsa_sha2_data_sig_verify_smmu_update_finalize( 1271 x1, x2, x3, x4, x5, (uint32_t *) &x6, 1272 x7, true, &mbox_error, &send_id); 1273 SMC_RET4(handle, status, mbox_error, x5, x6); 1274 1275 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_FINALIZE: 1276 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1277 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1278 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 1279 status = intel_fcs_ecdsa_sha2_data_sig_verify_update_finalize( 1280 x1, x2, x3, x4, x5, (uint32_t *) &x6, 1281 x7, true, &mbox_error); 1282 SMC_RET4(handle, status, mbox_error, x5, x6); 1283 1284 case INTEL_SIP_SMC_FCS_ECDSA_GET_PUBKEY_INIT: 1285 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1286 status = intel_fcs_ecdsa_get_pubkey_init(x1, x2, x3, 1287 x4, x5, &mbox_error); 1288 SMC_RET2(handle, status, mbox_error); 1289 1290 case INTEL_SIP_SMC_FCS_ECDSA_GET_PUBKEY_FINALIZE: 1291 status = intel_fcs_ecdsa_get_pubkey_finalize(x1, x2, x3, 1292 (uint32_t *) &x4, &mbox_error); 1293 SMC_RET4(handle, status, mbox_error, x3, x4); 1294 1295 case INTEL_SIP_SMC_FCS_ECDH_REQUEST_INIT: 1296 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1297 status = intel_fcs_ecdh_request_init(x1, x2, x3, 1298 x4, x5, &mbox_error); 1299 SMC_RET2(handle, status, mbox_error); 1300 1301 case INTEL_SIP_SMC_FCS_ECDH_REQUEST_FINALIZE: 1302 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1303 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1304 status = intel_fcs_ecdh_request_finalize(x1, x2, x3, 1305 x4, x5, (uint32_t *) &x6, &mbox_error); 1306 SMC_RET4(handle, status, mbox_error, x5, x6); 1307 1308 case INTEL_SIP_SMC_FCS_AES_CRYPT_INIT: 1309 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1310 status = intel_fcs_aes_crypt_init(x1, x2, x3, x4, x5, 1311 &mbox_error); 1312 SMC_RET2(handle, status, mbox_error); 1313 1314 case INTEL_SIP_SMC_FCS_AES_CRYPT_UPDATE: 1315 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1316 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1317 status = intel_fcs_aes_crypt_update_finalize(x1, x2, x3, x4, 1318 x5, x6, false, &send_id); 1319 SMC_RET1(handle, status); 1320 1321 case INTEL_SIP_SMC_FCS_AES_CRYPT_FINALIZE: 1322 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1323 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1324 status = intel_fcs_aes_crypt_update_finalize(x1, x2, x3, x4, 1325 x5, x6, true, &send_id); 1326 SMC_RET1(handle, status); 1327 1328 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 1329 case INTEL_SIP_SMC_FCS_SDM_REMAPPER_CONFIG: 1330 status = intel_smmu_hps_remapper_config(x1); 1331 SMC_RET1(handle, status); 1332 #endif 1333 1334 case INTEL_SIP_SMC_GET_ROM_PATCH_SHA384: 1335 status = intel_fcs_get_rom_patch_sha384(x1, &retval64, 1336 &mbox_error); 1337 SMC_RET4(handle, status, mbox_error, x1, retval64); 1338 1339 case INTEL_SIP_SMC_SVC_VERSION: 1340 SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK, 1341 SIP_SVC_VERSION_MAJOR, 1342 SIP_SVC_VERSION_MINOR); 1343 1344 case INTEL_SIP_SMC_SEU_ERR_STATUS: 1345 status = intel_sdm_seu_err_read(seu_respbuf, 1346 ARRAY_SIZE(seu_respbuf)); 1347 if (status) { 1348 SMC_RET1(handle, status); 1349 } else { 1350 SMC_RET3(handle, seu_respbuf[0], seu_respbuf[1], seu_respbuf[2]); 1351 } 1352 1353 case INTEL_SIP_SMC_SAFE_INJECT_SEU_ERR: 1354 status = intel_sdm_safe_inject_seu_err((uint32_t *)&x1, (uint32_t)x2); 1355 SMC_RET1(handle, status); 1356 1357 case INTEL_SIP_SMC_ATF_BUILD_VER: 1358 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, VERSION_MAJOR, 1359 VERSION_MINOR, VERSION_PATCH); 1360 1361 default: 1362 return socfpga_sip_handler(smc_fid, x1, x2, x3, x4, 1363 cookie, handle, flags); 1364 } 1365 } 1366 1367 uintptr_t sip_smc_handler(uint32_t smc_fid, 1368 u_register_t x1, 1369 u_register_t x2, 1370 u_register_t x3, 1371 u_register_t x4, 1372 void *cookie, 1373 void *handle, 1374 u_register_t flags) 1375 { 1376 uint32_t cmd = smc_fid & INTEL_SIP_SMC_CMD_MASK; 1377 1378 if (cmd >= INTEL_SIP_SMC_CMD_V2_RANGE_BEGIN && 1379 cmd <= INTEL_SIP_SMC_CMD_V2_RANGE_END) { 1380 return sip_smc_handler_v2(smc_fid, x1, x2, x3, x4, 1381 cookie, handle, flags); 1382 } else { 1383 return sip_smc_handler_v1(smc_fid, x1, x2, x3, x4, 1384 cookie, handle, flags); 1385 } 1386 } 1387 1388 DECLARE_RT_SVC( 1389 socfpga_sip_svc, 1390 OEN_SIP_START, 1391 OEN_SIP_END, 1392 SMC_TYPE_FAST, 1393 NULL, 1394 sip_smc_handler 1395 ); 1396 1397 DECLARE_RT_SVC( 1398 socfpga_sip_svc_std, 1399 OEN_SIP_START, 1400 OEN_SIP_END, 1401 SMC_TYPE_YIELD, 1402 NULL, 1403 sip_smc_handler 1404 ); 1405