1 /* 2 * Copyright (c) 2023-2024, STMicroelectronics - All Rights Reserved 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <lib/xlat_tables/xlat_tables_v2.h> 10 11 #include <platform_def.h> 12 13 #define BKPR_FWU_INFO 48U 14 #define BKPR_BOOT_MODE 96U 15 16 #if defined(IMAGE_BL31) 17 /* BL31 only uses the first half of the SYSRAM */ 18 #define MAP_SYSRAM MAP_REGION_FLAT(STM32MP_SYSRAM_BASE, \ 19 STM32MP_SYSRAM_SIZE / 2U, \ 20 MT_MEMORY | \ 21 MT_RW | \ 22 MT_SECURE | \ 23 MT_EXECUTE_NEVER) 24 #else 25 #define MAP_SYSRAM MAP_REGION_FLAT(STM32MP_SYSRAM_BASE, \ 26 STM32MP_SYSRAM_SIZE, \ 27 MT_MEMORY | \ 28 MT_RW | \ 29 MT_SECURE | \ 30 MT_EXECUTE_NEVER) 31 #endif 32 33 #if STM32MP_DDR_FIP_IO_STORAGE 34 #define MAP_SRAM1 MAP_REGION_FLAT(SRAM1_BASE, \ 35 SRAM1_SIZE_FOR_TFA, \ 36 MT_MEMORY | \ 37 MT_RW | \ 38 MT_SECURE | \ 39 MT_EXECUTE_NEVER) 40 #endif 41 42 #define MAP_DEVICE MAP_REGION_FLAT(STM32MP_DEVICE_BASE, \ 43 STM32MP_DEVICE_SIZE, \ 44 MT_DEVICE | \ 45 MT_RW | \ 46 MT_SECURE | \ 47 MT_EXECUTE_NEVER) 48 49 #if defined(IMAGE_BL2) 50 static const mmap_region_t stm32mp2_mmap[] = { 51 MAP_SYSRAM, 52 #if STM32MP_DDR_FIP_IO_STORAGE 53 MAP_SRAM1, 54 #endif 55 MAP_DEVICE, 56 {0} 57 }; 58 #endif 59 #if defined(IMAGE_BL31) 60 static const mmap_region_t stm32mp2_mmap[] = { 61 MAP_SYSRAM, 62 MAP_DEVICE, 63 {0} 64 }; 65 #endif 66 67 void configure_mmu(void) 68 { 69 mmap_add(stm32mp2_mmap); 70 init_xlat_tables(); 71 72 enable_mmu_el3(0); 73 } 74 75 int stm32mp_map_retram(void) 76 { 77 return mmap_add_dynamic_region(RETRAM_BASE, RETRAM_BASE, 78 RETRAM_SIZE, 79 MT_RW | MT_SECURE); 80 } 81 82 int stm32mp_unmap_retram(void) 83 { 84 return mmap_remove_dynamic_region(RETRAM_BASE, 85 RETRAM_SIZE); 86 } 87 88 uintptr_t stm32_get_gpio_bank_base(unsigned int bank) 89 { 90 if (bank == GPIO_BANK_Z) { 91 return GPIOZ_BASE; 92 } 93 94 assert(bank <= GPIO_BANK_K); 95 96 return GPIOA_BASE + (bank * GPIO_BANK_OFFSET); 97 } 98 99 uint32_t stm32_get_gpio_bank_offset(unsigned int bank) 100 { 101 if (bank == GPIO_BANK_Z) { 102 return 0; 103 } 104 105 assert(bank <= GPIO_BANK_K); 106 107 return bank * GPIO_BANK_OFFSET; 108 } 109 110 unsigned long stm32_get_gpio_bank_clock(unsigned int bank) 111 { 112 if (bank == GPIO_BANK_Z) { 113 return CK_BUS_GPIOZ; 114 } 115 116 assert(bank <= GPIO_BANK_K); 117 118 return CK_BUS_GPIOA + (bank - GPIO_BANK_A); 119 } 120 121 #if STM32MP_UART_PROGRAMMER || !defined(IMAGE_BL2) 122 /* 123 * UART Management 124 */ 125 static const uintptr_t stm32mp2_uart_addresses[STM32MP_NB_OF_UART] = { 126 USART1_BASE, 127 USART2_BASE, 128 USART3_BASE, 129 UART4_BASE, 130 UART5_BASE, 131 USART6_BASE, 132 UART7_BASE, 133 UART8_BASE, 134 UART9_BASE, 135 }; 136 137 uintptr_t get_uart_address(uint32_t instance_nb) 138 { 139 if ((instance_nb == 0U) || 140 (instance_nb > STM32MP_NB_OF_UART)) { 141 return 0U; 142 } 143 144 return stm32mp2_uart_addresses[instance_nb - 1U]; 145 } 146 #endif 147 148 uint32_t stm32mp_get_chip_version(void) 149 { 150 static uint32_t rev; 151 152 if (rev != 0U) { 153 return rev; 154 } 155 156 if (stm32_get_otp_value(REVISION_OTP, &rev) != 0) { 157 panic(); 158 } 159 160 return rev; 161 } 162 163 uint32_t stm32mp_get_chip_dev_id(void) 164 { 165 return stm32mp_syscfg_get_chip_dev_id(); 166 } 167 168 static uint32_t get_part_number(void) 169 { 170 static uint32_t part_number; 171 172 if (part_number != 0U) { 173 return part_number; 174 } 175 176 if (stm32_get_otp_value(PART_NUMBER_OTP, &part_number) != 0) { 177 panic(); 178 } 179 180 return part_number; 181 } 182 183 static uint32_t get_cpu_package(void) 184 { 185 static uint32_t package = UINT32_MAX; 186 187 if (package == UINT32_MAX) { 188 if (stm32_get_otp_value(PACKAGE_OTP, &package) != 0) { 189 panic(); 190 } 191 } 192 193 return (package & PACKAGE_OTP_PKG_MASK) >> PACKAGE_OTP_PKG_SHIFT; 194 } 195 196 void stm32mp_get_soc_name(char name[STM32_SOC_NAME_SIZE]) 197 { 198 char *cpu_s, *cpu_r, *pkg; 199 200 /* MPUs Part Numbers */ 201 switch (get_part_number()) { 202 case STM32MP251A_PART_NB: 203 cpu_s = "251A"; 204 break; 205 case STM32MP251C_PART_NB: 206 cpu_s = "251C"; 207 break; 208 case STM32MP251D_PART_NB: 209 cpu_s = "251D"; 210 break; 211 case STM32MP251F_PART_NB: 212 cpu_s = "251F"; 213 break; 214 case STM32MP253A_PART_NB: 215 cpu_s = "253A"; 216 break; 217 case STM32MP253C_PART_NB: 218 cpu_s = "253C"; 219 break; 220 case STM32MP253D_PART_NB: 221 cpu_s = "253D"; 222 break; 223 case STM32MP253F_PART_NB: 224 cpu_s = "253F"; 225 break; 226 case STM32MP255A_PART_NB: 227 cpu_s = "255A"; 228 break; 229 case STM32MP255C_PART_NB: 230 cpu_s = "255C"; 231 break; 232 case STM32MP255D_PART_NB: 233 cpu_s = "255D"; 234 break; 235 case STM32MP255F_PART_NB: 236 cpu_s = "255F"; 237 break; 238 case STM32MP257A_PART_NB: 239 cpu_s = "257A"; 240 break; 241 case STM32MP257C_PART_NB: 242 cpu_s = "257C"; 243 break; 244 case STM32MP257D_PART_NB: 245 cpu_s = "257D"; 246 break; 247 case STM32MP257F_PART_NB: 248 cpu_s = "257F"; 249 break; 250 default: 251 cpu_s = "????"; 252 break; 253 } 254 255 /* Package */ 256 switch (get_cpu_package()) { 257 case STM32MP25_PKG_CUSTOM: 258 pkg = "XX"; 259 break; 260 case STM32MP25_PKG_AL_VFBGA361: 261 pkg = "AL"; 262 break; 263 case STM32MP25_PKG_AK_VFBGA424: 264 pkg = "AK"; 265 break; 266 case STM32MP25_PKG_AI_TFBGA436: 267 pkg = "AI"; 268 break; 269 default: 270 pkg = "??"; 271 break; 272 } 273 274 /* REVISION */ 275 switch (stm32mp_get_chip_version()) { 276 case STM32MP2_REV_A: 277 cpu_r = "A"; 278 break; 279 case STM32MP2_REV_B: 280 cpu_r = "B"; 281 break; 282 case STM32MP2_REV_X: 283 cpu_r = "X"; 284 break; 285 case STM32MP2_REV_Y: 286 cpu_r = "Y"; 287 break; 288 case STM32MP2_REV_Z: 289 cpu_r = "Z"; 290 break; 291 default: 292 cpu_r = "?"; 293 break; 294 } 295 296 snprintf(name, STM32_SOC_NAME_SIZE, 297 "STM32MP%s%s Rev.%s", cpu_s, pkg, cpu_r); 298 } 299 300 void stm32mp_print_cpuinfo(void) 301 { 302 char name[STM32_SOC_NAME_SIZE]; 303 304 stm32mp_get_soc_name(name); 305 NOTICE("CPU: %s\n", name); 306 } 307 308 void stm32mp_print_boardinfo(void) 309 { 310 uint32_t board_id = 0U; 311 312 if (stm32_get_otp_value(BOARD_ID_OTP, &board_id) != 0) { 313 return; 314 } 315 316 if (board_id != 0U) { 317 stm32_display_board_info(board_id); 318 } 319 } 320 321 bool stm32mp_is_wakeup_from_standby(void) 322 { 323 /* TODO add source code to determine if platform is waking up from standby mode */ 324 return false; 325 } 326 327 uintptr_t stm32_get_bkpr_boot_mode_addr(void) 328 { 329 return tamp_bkpr(BKPR_BOOT_MODE); 330 } 331 332 #if PSA_FWU_SUPPORT 333 uintptr_t stm32_get_bkpr_fwu_info_addr(void) 334 { 335 return tamp_bkpr(BKPR_FWU_INFO); 336 } 337 #endif /* PSA_FWU_SUPPORT */ 338 339 uintptr_t stm32_ddrdbg_get_base(void) 340 { 341 return DDRDBG_BASE; 342 } 343