1# 2# Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7include common/fdt_wrappers.mk 8 9# Use the GICv3 driver on the FVP by default 10FVP_USE_GIC_DRIVER := FVP_GICV3 11 12# Default cluster count for FVP 13FVP_CLUSTER_COUNT := 2 14 15# Default number of CPUs per cluster on FVP 16FVP_MAX_CPUS_PER_CLUSTER := 4 17 18# Default number of threads per CPU on FVP 19FVP_MAX_PE_PER_CPU := 1 20 21# Disable redistributor frame of inactive/fused CPU cores by marking it as read 22# only; enable redistributor frames of all CPU cores by default. 23FVP_GICR_REGION_PROTECTION := 0 24 25ifeq (${HW_ASSISTED_COHERENCY}, 0) 26FVP_DT_PREFIX := fvp-base-gicv3-psci 27else 28FVP_DT_PREFIX := fvp-base-gicv3-psci-dynamiq 29endif 30# fdts is wrong otherwise 31 32# Size (in kilobytes) of the Trusted SRAM region to utilize when building for 33# the FVP platform. 34ifeq (${ENABLE_RME},1) 35FVP_TRUSTED_SRAM_SIZE := 384 36else 37FVP_TRUSTED_SRAM_SIZE := 256 38endif 39 40# Macro to enable helpers for running SPM tests. Disabled by default. 41PLAT_TEST_SPM := 0 42 43# By default dont build CPUs with no FVP model. 44BUILD_CPUS_WITH_NO_FVP_MODEL ?= 0 45 46ENABLE_FEAT_AMU := 2 47ENABLE_FEAT_AMUv1p1 := 2 48ENABLE_FEAT_HCX := 2 49ENABLE_FEAT_RNG := 2 50ENABLE_FEAT_TWED := 2 51ENABLE_FEAT_GCS := 2 52 53ifeq (${ARCH}, aarch64) 54 55ifeq (${SPM_MM}, 0) 56ifeq (${CTX_INCLUDE_FPREGS}, 0) 57 ENABLE_SME_FOR_NS := 2 58 ENABLE_SME2_FOR_NS := 2 59else 60 ENABLE_SVE_FOR_NS := 0 61 ENABLE_SME_FOR_NS := 0 62 ENABLE_SME2_FOR_NS := 0 63endif 64endif 65 66 ENABLE_BRBE_FOR_NS := 2 67 ENABLE_TRBE_FOR_NS := 2 68 ENABLE_FEAT_D128 := 2 69 ENABLE_FEAT_FPMR := 2 70 ENABLE_FEAT_MOPS := 2 71endif 72 73ENABLE_SYS_REG_TRACE_FOR_NS := 2 74ENABLE_FEAT_CSV2_2 := 2 75ENABLE_FEAT_CSV2_3 := 2 76ENABLE_FEAT_DEBUGV8P9 := 2 77ENABLE_FEAT_DIT := 2 78ENABLE_FEAT_PAN := 2 79ENABLE_FEAT_VHE := 2 80CTX_INCLUDE_NEVE_REGS := 2 81ENABLE_FEAT_SEL2 := 2 82ENABLE_TRF_FOR_NS := 2 83ENABLE_FEAT_ECV := 2 84ENABLE_FEAT_FGT := 2 85ENABLE_FEAT_FGT2 := 2 86ENABLE_FEAT_THE := 2 87ENABLE_FEAT_TCR2 := 2 88ENABLE_FEAT_S2PIE := 2 89ENABLE_FEAT_S1PIE := 2 90ENABLE_FEAT_S2POE := 2 91ENABLE_FEAT_S1POE := 2 92ENABLE_FEAT_SCTLR2 := 2 93ENABLE_FEAT_MTE2 := 2 94ENABLE_FEAT_LS64_ACCDATA := 2 95 96ifeq (${ENABLE_RME},1) 97 ENABLE_FEAT_MEC := 2 98endif 99 100# The FVP platform depends on this macro to build with correct GIC driver. 101$(eval $(call add_define,FVP_USE_GIC_DRIVER)) 102 103# Pass FVP_CLUSTER_COUNT to the build system. 104$(eval $(call add_define,FVP_CLUSTER_COUNT)) 105 106# Pass FVP_MAX_CPUS_PER_CLUSTER to the build system. 107$(eval $(call add_define,FVP_MAX_CPUS_PER_CLUSTER)) 108 109# Pass FVP_MAX_PE_PER_CPU to the build system. 110$(eval $(call add_define,FVP_MAX_PE_PER_CPU)) 111 112# Pass FVP_GICR_REGION_PROTECTION to the build system. 113$(eval $(call add_define,FVP_GICR_REGION_PROTECTION)) 114 115# Pass FVP_TRUSTED_SRAM_SIZE to the build system. 116$(eval $(call add_define,FVP_TRUSTED_SRAM_SIZE)) 117 118# Sanity check the cluster count and if FVP_CLUSTER_COUNT <= 2, 119# choose the CCI driver , else the CCN driver 120ifeq ($(FVP_CLUSTER_COUNT), 0) 121$(error "Incorrect cluster count specified for FVP port") 122else ifeq ($(FVP_CLUSTER_COUNT),$(filter $(FVP_CLUSTER_COUNT),1 2)) 123FVP_INTERCONNECT_DRIVER := FVP_CCI 124else 125FVP_INTERCONNECT_DRIVER := FVP_CCN 126endif 127 128$(eval $(call add_define,FVP_INTERCONNECT_DRIVER)) 129 130# Choose the GIC sources depending upon the how the FVP will be invoked 131ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV3) 132 133# The GIC model (GIC-600 or GIC-500) will be detected at runtime 134GICV3_SUPPORT_GIC600 := 1 135GICV3_OVERRIDE_DISTIF_PWR_OPS := 1 136 137# Include GICv3 driver files 138include drivers/arm/gic/v3/gicv3.mk 139 140FVP_GIC_SOURCES := ${GICV3_SOURCES} \ 141 plat/common/plat_gicv3.c \ 142 plat/arm/common/arm_gicv3.c 143 144 ifeq ($(filter 1,${RESET_TO_BL2} \ 145 ${RESET_TO_BL31} ${RESET_TO_SP_MIN}),) 146 FVP_GIC_SOURCES += plat/arm/board/fvp/fvp_gicv3.c 147 endif 148 149else ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV2) 150 151# No GICv4 extension 152GIC_ENABLE_V4_EXTN := 0 153$(eval $(call add_define,GIC_ENABLE_V4_EXTN)) 154 155# Include GICv2 driver files 156include drivers/arm/gic/v2/gicv2.mk 157 158FVP_GIC_SOURCES := ${GICV2_SOURCES} \ 159 plat/common/plat_gicv2.c \ 160 plat/arm/common/arm_gicv2.c 161 162FVP_DT_PREFIX := fvp-base-gicv2-psci 163else 164$(error "Incorrect GIC driver chosen on FVP port") 165endif 166 167ifeq (${FVP_INTERCONNECT_DRIVER}, FVP_CCI) 168FVP_INTERCONNECT_SOURCES := drivers/arm/cci/cci.c 169else ifeq (${FVP_INTERCONNECT_DRIVER}, FVP_CCN) 170FVP_INTERCONNECT_SOURCES := drivers/arm/ccn/ccn.c \ 171 plat/arm/common/arm_ccn.c 172else 173$(error "Incorrect CCN driver chosen on FVP port") 174endif 175 176FVP_SECURITY_SOURCES := drivers/arm/tzc/tzc400.c \ 177 plat/arm/board/fvp/fvp_security.c \ 178 plat/arm/common/arm_tzc400.c 179 180 181PLAT_INCLUDES := -Iplat/arm/board/fvp/include \ 182 -Iinclude/lib/psa 183 184 185PLAT_BL_COMMON_SOURCES := plat/arm/board/fvp/fvp_common.c 186 187FVP_CPU_LIBS := lib/cpus/${ARCH}/aem_generic.S 188 189ifeq (${ARCH}, aarch64) 190 191# select a different set of CPU files, depending on whether we compile for 192# hardware assisted coherency cores or not 193ifeq (${HW_ASSISTED_COHERENCY}, 0) 194# Cores used without DSU 195 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a35.S \ 196 lib/cpus/aarch64/cortex_a53.S \ 197 lib/cpus/aarch64/cortex_a57.S \ 198 lib/cpus/aarch64/cortex_a72.S \ 199 lib/cpus/aarch64/cortex_a73.S 200else 201# Cores used with DSU only 202 ifeq (${CTX_INCLUDE_AARCH32_REGS}, 0) 203 # AArch64-only cores 204 # TODO: add all cores to the appropriate lists 205 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a65.S \ 206 lib/cpus/aarch64/cortex_a65ae.S \ 207 lib/cpus/aarch64/cortex_a76.S \ 208 lib/cpus/aarch64/cortex_a76ae.S \ 209 lib/cpus/aarch64/cortex_a77.S \ 210 lib/cpus/aarch64/cortex_a78.S \ 211 lib/cpus/aarch64/cortex_a78_ae.S \ 212 lib/cpus/aarch64/cortex_a78c.S \ 213 lib/cpus/aarch64/cortex_a710.S \ 214 lib/cpus/aarch64/cortex_a715.S \ 215 lib/cpus/aarch64/cortex_a720.S \ 216 lib/cpus/aarch64/cortex_a720_ae.S \ 217 lib/cpus/aarch64/neoverse_n1.S \ 218 lib/cpus/aarch64/neoverse_n2.S \ 219 lib/cpus/aarch64/neoverse_v1.S \ 220 lib/cpus/aarch64/neoverse_e1.S \ 221 lib/cpus/aarch64/cortex_x2.S \ 222 lib/cpus/aarch64/cortex_x4.S 223 endif 224 # AArch64/AArch32 cores 225 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a55.S \ 226 lib/cpus/aarch64/cortex_a75.S 227endif 228 229#Include all CPUs to build to support all-errata build. 230ifeq (${ENABLE_ERRATA_ALL},1) 231 BUILD_CPUS_WITH_NO_FVP_MODEL = 1 232 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a320.S \ 233 lib/cpus/aarch64/cortex_a510.S \ 234 lib/cpus/aarch64/cortex_a520.S \ 235 lib/cpus/aarch64/cortex_a725.S \ 236 lib/cpus/aarch64/cortex_x1.S \ 237 lib/cpus/aarch64/cortex_x3.S \ 238 lib/cpus/aarch64/cortex_x925.S \ 239 lib/cpus/aarch64/neoverse_n3.S \ 240 lib/cpus/aarch64/neoverse_v2.S \ 241 lib/cpus/aarch64/neoverse_v3.S 242endif 243 244#Build AArch64-only CPUs with no FVP model yet. 245ifeq (${BUILD_CPUS_WITH_NO_FVP_MODEL},1) 246 # travis/gelas need these 247 FEAT_PABANDON := 1 248 ERRATA_SME_POWER_DOWN := 1 249 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_gelas.S \ 250 lib/cpus/aarch64/nevis.S \ 251 lib/cpus/aarch64/travis.S \ 252 lib/cpus/aarch64/cortex_alto.S 253endif 254 255else 256FVP_CPU_LIBS += lib/cpus/aarch32/cortex_a32.S \ 257 lib/cpus/aarch32/cortex_a57.S \ 258 lib/cpus/aarch32/cortex_a53.S 259endif 260 261BL1_SOURCES += drivers/arm/smmu/smmu_v3.c \ 262 drivers/arm/sp805/sp805.c \ 263 drivers/delay_timer/delay_timer.c \ 264 drivers/io/io_semihosting.c \ 265 lib/semihosting/semihosting.c \ 266 lib/semihosting/${ARCH}/semihosting_call.S \ 267 plat/arm/board/fvp/${ARCH}/fvp_helpers.S \ 268 plat/arm/board/fvp/fvp_bl1_setup.c \ 269 plat/arm/board/fvp/fvp_cpu_pwr.c \ 270 plat/arm/board/fvp/fvp_err.c \ 271 plat/arm/board/fvp/fvp_io_storage.c \ 272 plat/arm/board/fvp/fvp_topology.c \ 273 ${FVP_CPU_LIBS} \ 274 ${FVP_INTERCONNECT_SOURCES} 275 276ifeq (${USE_SP804_TIMER},1) 277BL1_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 278else 279BL1_SOURCES += drivers/delay_timer/generic_delay_timer.c 280endif 281 282 283BL2_SOURCES += drivers/arm/sp805/sp805.c \ 284 drivers/io/io_semihosting.c \ 285 lib/utils/mem_region.c \ 286 lib/semihosting/semihosting.c \ 287 lib/semihosting/${ARCH}/semihosting_call.S \ 288 plat/arm/board/fvp/fvp_bl2_setup.c \ 289 plat/arm/board/fvp/fvp_err.c \ 290 plat/arm/board/fvp/fvp_io_storage.c \ 291 plat/arm/common/arm_nor_psci_mem_protect.c \ 292 ${FVP_SECURITY_SOURCES} 293 294 295ifeq (${COT_DESC_IN_DTB},1) 296BL2_SOURCES += plat/arm/common/fconf/fconf_nv_cntr_getter.c 297endif 298 299ifeq (${ENABLE_RME},1) 300BL2_SOURCES += plat/arm/board/fvp/aarch64/fvp_helpers.S \ 301 plat/arm/board/fvp/fvp_cpu_pwr.c 302 303BL31_SOURCES += plat/arm/board/fvp/fvp_plat_attest_token.c \ 304 plat/arm/board/fvp/fvp_realm_attest_key.c \ 305 plat/arm/board/fvp/fvp_el3_token_sign.c 306endif 307 308ifeq (${ENABLE_FEAT_RNG_TRAP},1) 309BL31_SOURCES += plat/arm/board/fvp/fvp_sync_traps.c 310endif 311 312ifeq (${RESET_TO_BL2},1) 313BL2_SOURCES += plat/arm/board/fvp/${ARCH}/fvp_helpers.S \ 314 plat/arm/board/fvp/fvp_cpu_pwr.c \ 315 plat/arm/board/fvp/fvp_bl2_el3_setup.c \ 316 ${FVP_CPU_LIBS} \ 317 ${FVP_INTERCONNECT_SOURCES} 318endif 319 320ifeq (${USE_SP804_TIMER},1) 321BL2_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 322endif 323 324BL2U_SOURCES += plat/arm/board/fvp/fvp_bl2u_setup.c \ 325 ${FVP_SECURITY_SOURCES} 326 327ifeq (${USE_SP804_TIMER},1) 328BL2U_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 329endif 330 331BL31_SOURCES += drivers/arm/fvp/fvp_pwrc.c \ 332 drivers/arm/smmu/smmu_v3.c \ 333 drivers/delay_timer/delay_timer.c \ 334 drivers/cfi/v2m/v2m_flash.c \ 335 lib/utils/mem_region.c \ 336 plat/arm/board/fvp/fvp_bl31_setup.c \ 337 plat/arm/board/fvp/fvp_console.c \ 338 plat/arm/board/fvp/fvp_pm.c \ 339 plat/arm/board/fvp/fvp_topology.c \ 340 plat/arm/board/fvp/aarch64/fvp_helpers.S \ 341 plat/arm/board/fvp/fvp_cpu_pwr.c \ 342 plat/arm/common/arm_nor_psci_mem_protect.c \ 343 ${FVP_CPU_LIBS} \ 344 ${FVP_GIC_SOURCES} \ 345 ${FVP_INTERCONNECT_SOURCES} \ 346 ${FVP_SECURITY_SOURCES} 347 348# Support for fconf in BL31 349# Added separately from the above list for better readability 350ifeq ($(filter 1,${RESET_TO_BL2} ${RESET_TO_BL31}),) 351BL31_SOURCES += lib/fconf/fconf.c \ 352 lib/fconf/fconf_dyn_cfg_getter.c \ 353 plat/arm/board/fvp/fconf/fconf_hw_config_getter.c 354 355BL31_SOURCES += ${FDT_WRAPPERS_SOURCES} 356 357ifeq (${SEC_INT_DESC_IN_FCONF},1) 358BL31_SOURCES += plat/arm/common/fconf/fconf_sec_intr_config.c 359endif 360 361endif 362 363ifeq (${USE_SP804_TIMER},1) 364BL31_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 365else 366BL31_SOURCES += drivers/delay_timer/generic_delay_timer.c 367endif 368 369# Add the FDT_SOURCES and options for Dynamic Config (only for Unix env) 370FVP_HW_CONFIG_DTS := fdts/${FVP_DT_PREFIX}.dts 371 372FDT_SOURCES += ${FVP_HW_CONFIG_DTS} 373$(eval FVP_HW_CONFIG := ${BUILD_PLAT}/$(patsubst %.dts,%.dtb,$(FVP_HW_CONFIG_DTS))) 374HW_CONFIG := ${FVP_HW_CONFIG} 375 376# Set default initrd base 128MiB offset of the default kernel address in FVP 377INITRD_BASE ?= 0x90000000 378 379# Kernel base address supports Linux kernels before v5.7 380# DTB base 1MiB before normal base kernel address in FVP (0x88000000) 381ifeq (${ARM_LINUX_KERNEL_AS_BL33},1) 382 PRELOADED_BL33_BASE ?= 0x80080000 383 ifeq (${RESET_TO_BL31},1) 384 ARM_PRELOADED_DTB_BASE ?= 0x87F00000 385 endif 386endif 387 388ifeq (${TRANSFER_LIST}, 0) 389FDT_SOURCES += $(addprefix plat/arm/board/fvp/fdts/, \ 390 ${PLAT}_fw_config.dts \ 391 ${PLAT}_tb_fw_config.dts \ 392 ${PLAT}_soc_fw_config.dts \ 393 ${PLAT}_nt_fw_config.dts \ 394 ) 395 396FVP_TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb 397FVP_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb 398FVP_SOC_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_soc_fw_config.dtb 399FVP_NT_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb 400 401ifeq (${SPD},tspd) 402FDT_SOURCES += plat/arm/board/fvp/fdts/${PLAT}_tsp_fw_config.dts 403FVP_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tsp_fw_config.dtb 404 405# Add the TOS_FW_CONFIG to FIP and specify the same to certtool 406$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TOS_FW_CONFIG},--tos-fw-config,${FVP_TOS_FW_CONFIG})) 407endif 408 409ifeq (${SPD},spmd) 410 411ifeq ($(ARM_SPMC_MANIFEST_DTS),) 412ARM_SPMC_MANIFEST_DTS := plat/arm/board/fvp/fdts/${PLAT}_spmc_manifest.dts 413endif 414 415FDT_SOURCES += ${ARM_SPMC_MANIFEST_DTS} 416FVP_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/$(notdir $(basename ${ARM_SPMC_MANIFEST_DTS})).dtb 417 418# Add the TOS_FW_CONFIG to FIP and specify the same to certtool 419$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TOS_FW_CONFIG},--tos-fw-config,${FVP_TOS_FW_CONFIG})) 420endif 421 422# Add the FW_CONFIG to FIP and specify the same to certtool 423$(eval $(call TOOL_ADD_PAYLOAD,${FVP_FW_CONFIG},--fw-config,${FVP_FW_CONFIG})) 424# Add the SOC_FW_CONFIG to FIP and specify the same to certtool 425$(eval $(call TOOL_ADD_PAYLOAD,${FVP_SOC_FW_CONFIG},--soc-fw-config,${FVP_SOC_FW_CONFIG})) 426# Add the NT_FW_CONFIG to FIP and specify the same to certtool 427$(eval $(call TOOL_ADD_PAYLOAD,${FVP_NT_FW_CONFIG},--nt-fw-config,${FVP_NT_FW_CONFIG})) 428# Add the TB_FW_CONFIG to FIP and specify the same to certtool 429$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TB_FW_CONFIG},--tb-fw-config,${FVP_TB_FW_CONFIG})) 430endif 431 432# Add the HW_CONFIG to FIP and specify the same to certtool 433$(eval $(call TOOL_ADD_PAYLOAD,${FVP_HW_CONFIG},--hw-config,${FVP_HW_CONFIG})) 434 435ifeq (${TRANSFER_LIST}, 1) 436 437ifeq ($(RESET_TO_BL31), 1) 438FW_HANDOFF_SIZE := 20000 439 440TRANSFER_LIST_DTB_OFFSET := 0x20 441$(eval $(call add_define,TRANSFER_LIST_DTB_OFFSET)) 442endif 443endif 444 445ifeq (${HOB_LIST}, 1) 446include lib/hob/hob.mk 447endif 448 449# Enable dynamic mitigation support by default 450DYNAMIC_WORKAROUND_CVE_2018_3639 := 1 451 452ifneq (${ENABLE_FEAT_AMU},0) 453BL31_SOURCES += lib/cpus/aarch64/cpuamu.c \ 454 lib/cpus/aarch64/cpuamu_helpers.S 455 456ifeq (${HW_ASSISTED_COHERENCY}, 1) 457BL31_SOURCES += lib/cpus/aarch64/cortex_a75_pubsub.c \ 458 lib/cpus/aarch64/neoverse_n1_pubsub.c 459endif 460endif 461 462ifeq (${HANDLE_EA_EL3_FIRST_NS},1) 463 ifeq (${ENABLE_FEAT_RAS},1) 464 ifeq (${PLATFORM_TEST_FFH_LSP_RAS_SP},1) 465 BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_lsp_ras_sp.c 466 else 467 BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_ras.c 468 endif 469 else 470 BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_ea.c 471 endif 472endif 473 474ifneq (${ENABLE_STACK_PROTECTOR},0) 475PLAT_BL_COMMON_SOURCES += plat/arm/board/fvp/fvp_stack_protector.c 476endif 477 478# Enable the dynamic translation tables library. 479ifeq ($(filter 1,${RESET_TO_BL2} ${ARM_XLAT_TABLES_LIB_V1}),) 480 ifeq (${ARCH},aarch32) 481 BL32_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 482 else # AArch64 483 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 484 endif 485endif 486 487ifeq (${ALLOW_RO_XLAT_TABLES}, 1) 488 ifeq (${ARCH},aarch32) 489 BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 490 else # AArch64 491 BL31_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 492 ifeq (${SPD},tspd) 493 BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 494 endif 495 endif 496endif 497 498ifeq (${USE_DEBUGFS},1) 499 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 500endif 501 502# Add support for platform supplied linker script for BL31 build 503$(eval $(call add_define,PLAT_EXTRA_LD_SCRIPT)) 504 505ifneq (${RESET_TO_BL2}, 0) 506 override BL1_SOURCES = 507endif 508 509include plat/arm/board/common/board_common.mk 510include plat/arm/common/arm_common.mk 511 512ifeq (${MEASURED_BOOT},1) 513BL1_SOURCES += plat/arm/board/fvp/fvp_common_measured_boot.c \ 514 plat/arm/board/fvp/fvp_bl1_measured_boot.c \ 515 lib/psa/measured_boot.c 516 517BL2_SOURCES += plat/arm/board/fvp/fvp_common_measured_boot.c \ 518 plat/arm/board/fvp/fvp_bl2_measured_boot.c \ 519 lib/psa/measured_boot.c 520endif 521 522ifeq (${DRTM_SUPPORT}, 1) 523BL31_SOURCES += plat/arm/board/fvp/fvp_drtm_addr.c \ 524 plat/arm/board/fvp/fvp_drtm_dma_prot.c \ 525 plat/arm/board/fvp/fvp_drtm_err.c \ 526 plat/arm/board/fvp/fvp_drtm_measurement.c \ 527 plat/arm/board/fvp/fvp_drtm_stub.c \ 528 plat/arm/common/arm_dyn_cfg.c \ 529 plat/arm/board/fvp/fvp_err.c 530endif 531 532ifeq (${TRUSTED_BOARD_BOOT}, 1) 533BL1_SOURCES += plat/arm/board/fvp/fvp_trusted_boot.c 534BL2_SOURCES += plat/arm/board/fvp/fvp_trusted_boot.c 535 536# FVP being a development platform, enable capability to disable Authentication 537# dynamically if TRUSTED_BOARD_BOOT is set. 538DYN_DISABLE_AUTH := 1 539endif 540 541ifeq (${SPMC_AT_EL3}, 1) 542PLAT_BL_COMMON_SOURCES += plat/arm/board/fvp/fvp_el3_spmc.c 543endif 544 545PSCI_OS_INIT_MODE := 1 546 547ifeq (${SPD},spmd) 548BL31_SOURCES += plat/arm/board/fvp/fvp_spmd.c 549endif 550 551# Test specific macros, keep them at bottom of this file 552$(eval $(call add_define,PLATFORM_TEST_EA_FFH)) 553ifeq (${PLATFORM_TEST_EA_FFH}, 1) 554 ifeq (${FFH_SUPPORT}, 0) 555 $(error "PLATFORM_TEST_EA_FFH expects FFH_SUPPORT to be 1") 556 endif 557 558endif 559 560$(eval $(call add_define,PLATFORM_TEST_RAS_FFH)) 561ifeq (${PLATFORM_TEST_RAS_FFH}, 1) 562 ifeq (${ENABLE_FEAT_RAS}, 0) 563 $(error "PLATFORM_TEST_RAS_FFH expects ENABLE_FEAT_RAS to be 1") 564 endif 565 ifeq (${HANDLE_EA_EL3_FIRST_NS}, 0) 566 $(error "PLATFORM_TEST_RAS_FFH expects HANDLE_EA_EL3_FIRST_NS to be 1") 567 endif 568endif 569 570$(eval $(call add_define,PLATFORM_TEST_FFH_LSP_RAS_SP)) 571ifeq (${PLATFORM_TEST_FFH_LSP_RAS_SP}, 1) 572 ifeq (${PLATFORM_TEST_RAS_FFH}, 1) 573 $(error "PLATFORM_TEST_RAS_FFH is incompatible with PLATFORM_TEST_FFH_LSP_RAS_SP") 574 endif 575 ifeq (${ENABLE_SPMD_LP}, 0) 576 $(error "PLATFORM_TEST_FFH_LSP_RAS_SP expects ENABLE_SPMD_LP to be 1") 577 endif 578 ifeq (${ENABLE_FEAT_RAS}, 0) 579 $(error "PLATFORM_TEST_FFH_LSP_RAS_SP expects ENABLE_FEAT_RAS to be 1") 580 endif 581 ifeq (${HANDLE_EA_EL3_FIRST_NS}, 0) 582 $(error "PLATFORM_TEST_FFH_LSP_RAS_SP expects HANDLE_EA_EL3_FIRST_NS to be 1") 583 endif 584endif 585 586ifeq (${ERRATA_ABI_SUPPORT}, 1) 587include plat/arm/board/fvp/fvp_cpu_errata.mk 588endif 589 590# Build macro necessary for running SPM tests on FVP platform 591$(eval $(call add_define,PLAT_TEST_SPM)) 592