1 /* 2 * Copyright (c) 2013-2025, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2015-2025, Renesas Electronics Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <stddef.h> 9 10 #include <arch.h> 11 #include <arch_helpers.h> 12 #include <bl31/bl31.h> 13 #include <common/bl_common.h> 14 #include <common/debug.h> 15 #include <drivers/arm/cci.h> 16 #include <drivers/console.h> 17 #include <lib/mmio.h> 18 #include "mssr.h" 19 #include <plat/arm/common/plat_arm.h> 20 #include <plat/common/platform.h> 21 #include "ptp.h" 22 #include "pwrc.h" 23 24 #include "rcar_def.h" 25 #include "rcar_private.h" 26 #include "rcar_version.h" 27 28 struct entry_point_info *bl31_plat_get_next_image_ep_info(uint32_t type) 29 { 30 bl2_to_bl31_params_mem_t *from_bl2 = 31 (bl2_to_bl31_params_mem_t *)PARAMS_BASE; 32 entry_point_info_t *next_image_info = (type == NON_SECURE) ? 33 &from_bl2->bl33_ep_info : 34 &from_bl2->bl32_ep_info; 35 36 return next_image_info->pc ? next_image_info : NULL; 37 } 38 39 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 40 u_register_t arg2, u_register_t arg3) 41 { 42 rcar_console_boot_init(); 43 44 NOTICE("BL3-1 : Rev.%s\n", version_of_renesas); 45 } 46 47 void bl31_plat_arch_setup(void) 48 { 49 static const uintptr_t BL31_RO_BASE = BL_CODE_BASE; 50 static const uintptr_t BL31_RO_LIMIT = BL_CODE_END; 51 52 rcar_configure_mmu_el3(BL31_BASE, 53 BL31_LIMIT - BL31_BASE, 54 BL31_RO_BASE, BL31_RO_LIMIT); 55 56 rcar_pwrc_code_copy_to_system_ram(); 57 } 58 59 static const uintptr_t gicr_base_addrs[2] = { 60 PLAT_ARM_GICR_BASE, /* GICR Base address of the primary CPU */ 61 0U /* Zero Termination */ 62 }; 63 64 void bl31_platform_setup(void) 65 { 66 /* Initialize generic timer */ 67 u_register_t reg_cntfid = RCAR_CNTC_EXTAL; 68 69 rcar_mssr_setup(); 70 71 /* Update memory mapped and register based frequency */ 72 write_cntfrq_el0(reg_cntfid); 73 mmio_write_32(ARM_SYS_CNTCTL_BASE + CNTFID_OFF, reg_cntfid); 74 75 /* Enable the system level generic timer */ 76 mmio_write_32(RCAR_CNTC_BASE + CNTCR_OFF, CNTCR_FCREQ(0) | CNTCR_EN); 77 78 gic_set_gicr_frames(gicr_base_addrs); 79 80 rcar_pwrc_setup(); 81 rcar_ptp_setup(); 82 } 83 84 const spd_pm_ops_t rcar_pm = { 85 .svc_migrate_info = rcar_pwrc_cpu_migrate_info, 86 }; 87 88 void bl31_plat_runtime_setup(void) 89 { 90 psci_register_spd_pm_hook(&rcar_pm); 91 92 rcar_console_runtime_init(); 93 console_switch_state(CONSOLE_FLAG_RUNTIME); 94 } 95