1 /* 2 * Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2023, Advanced Micro Devices, Inc. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /* 9 * Top-level SMC handler for ZynqMP power management calls and 10 * IPI setup functions for communication with PMU. 11 */ 12 13 #include <errno.h> 14 15 #include <arch_helpers.h> 16 #include <common/runtime_svc.h> 17 #include <drivers/arm/gicv2.h> 18 #include <lib/mmio.h> 19 #include <lib/spinlock.h> 20 #include <plat/common/platform.h> 21 22 #include <plat_private.h> 23 #include "pm_client.h" 24 #include "pm_ipi.h" 25 #include "pm_svc_main.h" 26 #include "zynqmp_pm_api_sys.h" 27 #include "zynqmp_pm_defs.h" 28 29 /* pm_up = !0 - UP, pm_up = 0 - DOWN */ 30 static int32_t pm_up, ipi_irq_flag; 31 32 #if ZYNQMP_WDT_RESTART 33 static spinlock_t inc_lock; 34 static int active_cores = 0; 35 #endif 36 37 /** 38 * typedef pm_ctx_t - Structure which contains data for power management. 39 * @api_version: version of PM API, must match with one on PMU side. 40 * @payload: payload array used to store received. 41 * data from ipi buffer registers. 42 * 43 */ 44 typedef struct { 45 uint32_t api_version; 46 uint32_t payload[PAYLOAD_ARG_CNT]; 47 } pm_ctx_t; 48 49 static pm_ctx_t pm_ctx; 50 51 #if ZYNQMP_WDT_RESTART 52 /** 53 * trigger_wdt_restart() - Trigger warm restart event to APU cores. 54 * 55 * This function triggers SGI for all active APU CPUs. SGI handler then 56 * power down CPU and call system reset. 57 * 58 */ 59 static void trigger_wdt_restart(void) 60 { 61 uint32_t core_count = 0; 62 uint32_t core_status[3]; 63 uint32_t target_cpu_list = 0; 64 int i; 65 66 for (i = 0; i < 4; i++) { 67 pm_get_node_status(NODE_APU_0 + i, core_status); 68 if (core_status[0] == 1) { 69 core_count++; 70 target_cpu_list |= (1 << i); 71 } 72 } 73 74 spin_lock(&inc_lock); 75 active_cores = core_count; 76 spin_unlock(&inc_lock); 77 78 INFO("Active Cores: %d\n", active_cores); 79 80 for (i = PLATFORM_CORE_COUNT - 1; i >= 0; i--) { 81 if (target_cpu_list & (1 << i)) { 82 /* trigger SGI to active cores */ 83 plat_ic_raise_el3_sgi(ARM_IRQ_SEC_SGI_7, i); 84 } 85 } 86 } 87 88 /** 89 * ttc_fiq_handler() - TTC Handler for timer event. 90 * @id: number of the highest priority pending interrupt of the type 91 * that this handler was registered for. 92 * @flags: security state, bit[0]. 93 * @handle: pointer to 'cpu_context' structure of the current CPU for the 94 * security state specified in the 'flags' parameter. 95 * @cookie: unused. 96 * 97 * Function registered as INTR_TYPE_EL3 interrupt handler. 98 * 99 * When WDT event is received in PMU, PMU needs to notify master to do cleanup 100 * if required. PMU sets up timer and starts timer to overflow in zero time upon 101 * WDT event. TF-A handles this timer event and takes necessary action required 102 * for warm restart. 103 * 104 * In presence of non-secure software layers (EL1/2) sets the interrupt 105 * at registered entrance in GIC and informs that PMU responded or demands 106 * action. 107 * 108 * Return: 0 on success. 109 * 110 */ 111 static uint64_t ttc_fiq_handler(uint32_t id, uint32_t flags, void *handle, 112 void *cookie) 113 { 114 INFO("BL31: Got TTC FIQ\n"); 115 116 plat_ic_end_of_interrupt(id); 117 118 /* Clear TTC interrupt by reading interrupt register */ 119 mmio_read_32(TTC3_INTR_REGISTER_1); 120 121 /* Disable the timer interrupts */ 122 mmio_write_32(TTC3_INTR_ENABLE_1, 0); 123 124 trigger_wdt_restart(); 125 126 return 0; 127 } 128 129 /** 130 * zynqmp_sgi7_irq() - Handler for SGI7 IRQ. 131 * @id: number of the highest priority pending interrupt of the type 132 * that this handler was registered for. 133 * @flags: security state, bit[0]. 134 * @handle: pointer to 'cpu_context' structure of the current CPU for the 135 * security state specified in the 'flags' parameter. 136 * @cookie: unused. 137 * 138 * Function registered as INTR_TYPE_EL3 interrupt handler 139 * 140 * On receiving WDT event from PMU, TF-A generates SGI7 to all running CPUs. 141 * In response to SGI7 interrupt, each CPUs do clean up if required and last 142 * running CPU calls system restart. 143 * 144 * Return: This function does not return a value and it enters into wfi. 145 */ 146 static uint64_t __unused __dead2 zynqmp_sgi7_irq(uint32_t id, uint32_t flags, 147 void *handle, void *cookie) 148 { 149 int i; 150 uint32_t value; 151 152 /* enter wfi and stay there */ 153 INFO("Entering wfi\n"); 154 155 spin_lock(&inc_lock); 156 active_cores--; 157 158 for (i = 0; i < 4; i++) { 159 mmio_write_32(BASE_GICD_BASE + GICD_CPENDSGIR + 4 * i, 160 0xffffffff); 161 } 162 163 dsb(); 164 165 spin_unlock(&inc_lock); 166 167 if (active_cores == 0) { 168 pm_mmio_read(PMU_GLOBAL_GEN_STORAGE4, &value); 169 value = (value & RESTART_SCOPE_MASK) >> RESTART_SCOPE_SHIFT; 170 pm_system_shutdown(PMF_SHUTDOWN_TYPE_RESET, value); 171 } 172 173 /* enter wfi and stay there */ 174 while (1) 175 wfi(); 176 } 177 178 /** 179 * pm_wdt_restart_setup() - Setup warm restart interrupts. 180 * 181 * Return: Returns status, 0 on success or error+reason. 182 * 183 * This function sets up handler for SGI7 and TTC interrupts 184 * used for warm restart. 185 */ 186 static int pm_wdt_restart_setup(void) 187 { 188 int ret; 189 190 /* register IRQ handler for SGI7 */ 191 ret = request_intr_type_el3(ARM_IRQ_SEC_SGI_7, zynqmp_sgi7_irq); 192 if (ret) { 193 WARN("BL31: registering SGI7 interrupt failed\n"); 194 goto err; 195 } 196 197 ret = request_intr_type_el3(IRQ_TTC3_1, ttc_fiq_handler); 198 if (ret) 199 WARN("BL31: registering TTC3 interrupt failed\n"); 200 201 err: 202 return ret; 203 } 204 #endif 205 206 /** 207 * pm_setup() - PM service setup. 208 * 209 * Return: On success, the initialization function must return 0. 210 * Any other return value will cause the framework to ignore 211 * the service. 212 * 213 * Initialization functions for ZynqMP power management for 214 * communicaton with PMU. 215 * 216 * Called from sip_svc_setup initialization function with the 217 * rt_svc_init signature. 218 * 219 */ 220 int32_t pm_setup(void) 221 { 222 enum pm_ret_status err; 223 224 pm_ipi_init(primary_proc); 225 226 err = pm_get_api_version(&pm_ctx.api_version); 227 if (err != PM_RET_SUCCESS) { 228 ERROR("BL31: Failed to read Platform Management API version. " 229 "Return: %d\n", err); 230 return -EINVAL; 231 } 232 if (pm_ctx.api_version < PM_VERSION) { 233 ERROR("BL31: Platform Management API version error. Expected: " 234 "v%d.%d - Found: v%d.%d\n", PM_VERSION_MAJOR, 235 PM_VERSION_MINOR, pm_ctx.api_version >> 16, 236 pm_ctx.api_version & 0xFFFFU); 237 return -EINVAL; 238 } 239 240 int32_t status = 0, ret = 0; 241 #if ZYNQMP_WDT_RESTART 242 status = pm_wdt_restart_setup(); 243 if (status) 244 WARN("BL31: warm-restart setup failed\n"); 245 #endif 246 247 if (status >= 0) { 248 INFO("BL31: PM Service Init Complete: API v%d.%d\n", 249 PM_VERSION_MAJOR, PM_VERSION_MINOR); 250 ret = 0; 251 } else { 252 INFO("BL31: PM Service Init Failed, Error Code %d!\n", status); 253 ret = status; 254 } 255 256 pm_up = (status == 0); 257 258 return ret; 259 } 260 261 /** 262 * pm_smc_handler() - SMC handler for PM-API calls coming from EL1/EL2. 263 * @smc_fid: Function Identifier. 264 * @x1: Arguments. 265 * @x2: Arguments. 266 * @x3: Arguments. 267 * @x4: Arguments. 268 * @cookie: Unused. 269 * @handle: Pointer to caller's context structure. 270 * @flags: SECURE_FLAG or NON_SECURE_FLAG. 271 * 272 * Determines that smc_fid is valid and supported PM SMC Function ID from the 273 * list of pm_api_ids, otherwise completes the request with 274 * the unknown SMC Function ID. 275 * 276 * The SMC calls for PM service are forwarded from SIP Service SMC handler 277 * function with rt_svc_handle signature. 278 * 279 * Return: Unused. 280 * 281 */ 282 uint64_t pm_smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3, 283 uint64_t x4, const void *cookie, void *handle, uint64_t flags) 284 { 285 (void)x4; 286 (void)cookie; 287 (void)flags; 288 enum pm_ret_status ret; 289 uint32_t payload[PAYLOAD_ARG_CNT]; 290 291 uint32_t pm_arg[5]; 292 uint32_t result[RET_PAYLOAD_ARG_CNT] = {0}; 293 uint32_t api_id; 294 295 /* Handle case where PM wasn't initialized properly */ 296 if (pm_up == 0) 297 SMC_RET1(handle, SMC_UNK); 298 299 pm_arg[0] = (uint32_t)x1; 300 pm_arg[1] = (uint32_t)(x1 >> 32); 301 pm_arg[2] = (uint32_t)x2; 302 pm_arg[3] = (uint32_t)(x2 >> 32); 303 pm_arg[4] = (uint32_t)x3; 304 305 api_id = smc_fid & FUNCID_NUM_MASK; 306 307 switch (api_id) { 308 /* PM API Functions */ 309 case PM_SELF_SUSPEND: 310 ret = pm_self_suspend(pm_arg[0], pm_arg[1], pm_arg[2], 311 pm_arg[3]); 312 SMC_RET1(handle, (uint64_t)ret); 313 314 case PM_REQ_SUSPEND: 315 ret = pm_req_suspend(pm_arg[0], pm_arg[1], pm_arg[2], 316 pm_arg[3]); 317 SMC_RET1(handle, (uint64_t)ret); 318 319 case PM_REQ_WAKEUP: 320 { 321 /* Use address flag is encoded in the 1st bit of the low-word */ 322 uint32_t set_addr = pm_arg[1] & 0x1U; 323 uint64_t address = (uint64_t)pm_arg[2] << 32U; 324 325 address |= (uint64_t)(pm_arg[1] & (~0x1U)); 326 ret = pm_req_wakeup(pm_arg[0], set_addr, address, 327 pm_arg[3]); 328 SMC_RET1(handle, (uint64_t)ret); 329 } 330 331 case PM_FORCE_POWERDOWN: 332 ret = pm_force_powerdown(pm_arg[0], pm_arg[1]); 333 SMC_RET1(handle, (uint64_t)ret); 334 335 case PM_ABORT_SUSPEND: 336 ret = pm_abort_suspend(pm_arg[0]); 337 SMC_RET1(handle, (uint64_t)ret); 338 339 case PM_SET_WAKEUP_SOURCE: 340 ret = pm_set_wakeup_source(pm_arg[0], pm_arg[1], pm_arg[2]); 341 SMC_RET1(handle, (uint64_t)ret); 342 343 case PM_SYSTEM_SHUTDOWN: 344 ret = pm_system_shutdown(pm_arg[0], pm_arg[1]); 345 SMC_RET1(handle, (uint64_t)ret); 346 347 case PM_REQ_NODE: 348 ret = pm_req_node(pm_arg[0], pm_arg[1], pm_arg[2], pm_arg[3]); 349 SMC_RET1(handle, (uint64_t)ret); 350 351 case PM_SET_REQUIREMENT: 352 ret = pm_set_requirement(pm_arg[0], pm_arg[1], pm_arg[2], 353 pm_arg[3]); 354 SMC_RET1(handle, (uint64_t)ret); 355 356 case PM_GET_API_VERSION: 357 if ((uint32_t)ipi_irq_flag == 0U) { 358 /* 359 * Enable IPI IRQ 360 * assume the rich OS is OK to handle callback IRQs now. 361 * Even if we were wrong, it would not enable the IRQ in 362 * the GIC. 363 */ 364 pm_ipi_irq_enable(primary_proc); 365 ipi_irq_flag = 1U; 366 } 367 SMC_RET1(handle, (uint64_t)PM_RET_SUCCESS | 368 ((uint64_t)pm_ctx.api_version << 32)); 369 case PM_FPGA_LOAD: 370 ret = pm_fpga_load(pm_arg[0], pm_arg[1], pm_arg[2], pm_arg[3]); 371 SMC_RET1(handle, (uint64_t)ret); 372 373 case PM_FPGA_GET_STATUS: 374 { 375 uint32_t value = 0U; 376 377 ret = pm_fpga_get_status(&value); 378 SMC_RET1(handle, ((uint64_t)ret | (((uint64_t)value) << 32))); 379 } 380 381 case PM_SECURE_RSA_AES: 382 ret = pm_secure_rsaaes(pm_arg[0], pm_arg[1], pm_arg[2], 383 pm_arg[3]); 384 SMC_RET1(handle, (uint64_t)ret); 385 386 case PM_GET_CALLBACK_DATA: 387 ret = pm_get_callbackdata(result, ARRAY_SIZE(result)); 388 if (ret != PM_RET_SUCCESS) { 389 result[0] = ret; 390 } 391 392 SMC_RET2(handle, 393 ((uint64_t)result[0] | ((uint64_t)result[1] << 32)), 394 ((uint64_t)result[2] | ((uint64_t)result[3] << 32))); 395 case PM_IOCTL: 396 { 397 uint32_t value = 0U; 398 399 ret = pm_ioctl(pm_arg[0], pm_arg[1], pm_arg[2], 400 pm_arg[3], &value); 401 SMC_RET1(handle, ((uint64_t)ret | (((uint64_t)value) << 32))); 402 } 403 404 case PM_QUERY_DATA: 405 { 406 uint32_t data[4] = { 0 }; 407 408 pm_query_data(pm_arg[0], pm_arg[1], pm_arg[2], 409 pm_arg[3], data); 410 SMC_RET2(handle, ((uint64_t)data[0] | ((uint64_t)data[1] << 32)), 411 ((uint64_t)data[2] | ((uint64_t)data[3] << 32))); 412 } 413 414 case PM_CLOCK_ENABLE: 415 ret = pm_clock_enable(pm_arg[0]); 416 SMC_RET1(handle, (uint64_t)ret); 417 418 case PM_CLOCK_DISABLE: 419 ret = pm_clock_disable(pm_arg[0]); 420 SMC_RET1(handle, (uint64_t)ret); 421 422 case PM_CLOCK_GETSTATE: 423 { 424 uint32_t value = 0U; 425 426 ret = pm_clock_getstate(pm_arg[0], &value); 427 SMC_RET1(handle, ((uint64_t)ret | (((uint64_t)value) << 32))); 428 } 429 430 case PM_CLOCK_SETDIVIDER: 431 ret = pm_clock_setdivider(pm_arg[0], pm_arg[1]); 432 SMC_RET1(handle, (uint64_t)ret); 433 434 case PM_CLOCK_GETDIVIDER: 435 { 436 uint32_t value = 0U; 437 438 ret = pm_clock_getdivider(pm_arg[0], &value); 439 SMC_RET1(handle, ((uint64_t)ret | (((uint64_t)value) << 32))); 440 } 441 442 case PM_CLOCK_SETPARENT: 443 ret = pm_clock_setparent(pm_arg[0], pm_arg[1]); 444 SMC_RET1(handle, (uint64_t)ret); 445 446 case PM_CLOCK_GETPARENT: 447 { 448 uint32_t value = 0U; 449 450 ret = pm_clock_getparent(pm_arg[0], &value); 451 SMC_RET1(handle, ((uint64_t)ret | (((uint64_t)value) << 32U))); 452 } 453 454 case PM_GET_TRUSTZONE_VERSION: 455 SMC_RET1(handle, (uint64_t)PM_RET_SUCCESS | 456 ((uint64_t)ZYNQMP_TZ_VERSION << 32U)); 457 458 case PM_SET_SUSPEND_MODE: 459 ret = pm_set_suspend_mode(pm_arg[0]); 460 SMC_RET1(handle, (uint64_t)ret); 461 462 case PM_SECURE_SHA: 463 ret = pm_sha_hash(pm_arg[0], pm_arg[1], pm_arg[2], 464 pm_arg[3]); 465 SMC_RET1(handle, (uint64_t)ret); 466 467 case PM_SECURE_RSA: 468 ret = pm_rsa_core(pm_arg[0], pm_arg[1], pm_arg[2], 469 pm_arg[3]); 470 SMC_RET1(handle, (uint64_t)ret); 471 472 case PM_SECURE_IMAGE: 473 { 474 ret = pm_secure_image(pm_arg[0], pm_arg[1], pm_arg[2], 475 pm_arg[3], &result[0]); 476 SMC_RET2(handle, ((uint64_t)ret | ((uint64_t)result[0] << 32U)), 477 result[1]); 478 } 479 480 case PM_FPGA_READ: 481 { 482 uint32_t value = 0U; 483 484 ret = pm_fpga_read(pm_arg[0], pm_arg[1], pm_arg[2], pm_arg[3], 485 &value); 486 SMC_RET1(handle, ((uint64_t)ret | (((uint64_t)value) << 32U))); 487 } 488 489 case PM_SECURE_AES: 490 { 491 uint32_t value = 0U; 492 493 ret = pm_aes_engine(pm_arg[0], pm_arg[1], &value); 494 SMC_RET1(handle, ((uint64_t)ret | (((uint64_t)value) << 32U))); 495 } 496 497 case PM_PLL_SET_PARAMETER: 498 ret = pm_pll_set_parameter(pm_arg[0], pm_arg[1], pm_arg[2]); 499 SMC_RET1(handle, (uint64_t)ret); 500 501 case PM_PLL_GET_PARAMETER: 502 { 503 uint32_t value = 0U; 504 505 ret = pm_pll_get_parameter(pm_arg[0], pm_arg[1], &value); 506 SMC_RET1(handle, ((uint64_t)ret | ((uint64_t)value << 32U))); 507 } 508 509 case PM_PLL_SET_MODE: 510 ret = pm_pll_set_mode(pm_arg[0], pm_arg[1]); 511 SMC_RET1(handle, (uint64_t)ret); 512 513 case PM_PLL_GET_MODE: 514 { 515 uint32_t mode = 0U; 516 517 ret = pm_pll_get_mode(pm_arg[0], &mode); 518 SMC_RET1(handle, ((uint64_t)ret | ((uint64_t)mode << 32U))); 519 } 520 521 case PM_REGISTER_ACCESS: 522 { 523 uint32_t value = 0U; 524 525 ret = pm_register_access(pm_arg[0], pm_arg[1], pm_arg[2], 526 pm_arg[3], &value); 527 SMC_RET1(handle, ((uint64_t)ret | (((uint64_t)value) << 32U))); 528 } 529 530 case PM_EFUSE_ACCESS: 531 { 532 uint32_t value = 0U; 533 534 #if defined(ZYNQMP_SECURE_EFUSES) 535 if (is_caller_non_secure(flags)) { 536 SMC_RET1(handle, 537 (((uint64_t)PM_RET_ERROR_NOT_ENABLED) << 32U) | 538 (uint64_t)PM_RET_ERROR_ACCESS); 539 } 540 #endif 541 ret = pm_efuse_access(pm_arg[0], pm_arg[1], &value); 542 SMC_RET1(handle, (uint64_t)ret | (((uint64_t)value) << 32U)); 543 } 544 545 case PM_FPGA_GET_VERSION: 546 case PM_FPGA_GET_FEATURE_LIST: 547 { 548 uint32_t ret_payload[PAYLOAD_ARG_CNT]; 549 550 PM_PACK_PAYLOAD5(payload, smc_fid & FUNCID_NUM_MASK, 551 pm_arg[0], pm_arg[1], pm_arg[2], pm_arg[3]); 552 ret = pm_ipi_send_sync(primary_proc, payload, ret_payload, 3U); 553 SMC_RET2(handle, ((uint64_t)ret | ((uint64_t)ret_payload[0] << 32U)), 554 ((uint64_t)ret_payload[1] | ((uint64_t)ret_payload[2] << 32U))); 555 } 556 557 case PM_FEATURE_CHECK: 558 { 559 uint32_t version_type = 0; 560 uint32_t bit_mask[2] = {0}; 561 562 ret = pm_feature_check(pm_arg[0], &version_type, bit_mask, 563 (uint8_t)ARRAY_SIZE(bit_mask)); 564 SMC_RET2(handle, ((uint64_t)ret | ((uint64_t)version_type << 32U)), 565 ((uint64_t)bit_mask[0] | ((uint64_t)bit_mask[1] << 32U))); 566 } 567 568 default: 569 /* Send request to the PMU */ 570 PM_PACK_PAYLOAD6(payload, api_id, pm_arg[0], pm_arg[1], 571 pm_arg[2], pm_arg[3], pm_arg[4]); 572 ret = pm_ipi_send_sync(primary_proc, payload, result, 573 RET_PAYLOAD_ARG_CNT); 574 SMC_RET2(handle, ((uint64_t)ret | ((uint64_t)result[0] << 32U)), 575 ((uint64_t)result[1] | ((uint64_t)result[2] << 32U))); 576 } 577 } 578