1 /* 2 * Copyright (c) 2014-2024, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <drivers/arm/tzc400.h> 11 #include <lib/utils_def.h> 12 #include <plat/arm/board/common/v2m_def.h> 13 #include <plat/arm/common/arm_def.h> 14 #include <plat/arm/common/arm_spm_def.h> 15 #include <plat/common/common_def.h> 16 17 #include "../fvp_def.h" 18 19 #if TRUSTED_BOARD_BOOT 20 #include MBEDTLS_CONFIG_FILE 21 #endif 22 23 /* Required platform porting definitions */ 24 #define PLATFORM_CORE_COUNT (U(FVP_CLUSTER_COUNT) * \ 25 U(FVP_MAX_CPUS_PER_CLUSTER) * \ 26 U(FVP_MAX_PE_PER_CPU)) 27 28 #define PLAT_NUM_PWR_DOMAINS (U(FVP_CLUSTER_COUNT) + \ 29 PLATFORM_CORE_COUNT + U(1)) 30 31 #define PLAT_MAX_PWR_LVL ARM_PWR_LVL2 32 33 #if PSCI_OS_INIT_MODE 34 #define PLAT_MAX_CPU_SUSPEND_PWR_LVL ARM_PWR_LVL1 35 #endif 36 37 /* 38 * Other platform porting definitions are provided by included headers 39 */ 40 41 /* 42 * Required ARM standard platform porting definitions 43 */ 44 #define PLAT_ARM_CLUSTER_COUNT U(FVP_CLUSTER_COUNT) 45 46 #define PLAT_ARM_TRUSTED_SRAM_SIZE (FVP_TRUSTED_SRAM_SIZE * UL(1024)) 47 48 #define PLAT_ARM_TRUSTED_ROM_BASE UL(0x00000000) 49 #define PLAT_ARM_TRUSTED_ROM_SIZE UL(0x04000000) /* 64 MB */ 50 51 #define PLAT_ARM_TRUSTED_DRAM_BASE UL(0x06000000) 52 #define PLAT_ARM_TRUSTED_DRAM_SIZE UL(0x02000000) /* 32 MB */ 53 54 #if ENABLE_RME 55 #define PLAT_ARM_RMM_BASE (RMM_BASE) 56 #define PLAT_ARM_RMM_SIZE (RMM_LIMIT - RMM_BASE) 57 #endif 58 59 /* 60 * Max size of SPMC is 2MB for fvp. With SPMD enabled this value corresponds to 61 * max size of BL32 image. 62 */ 63 #if defined(SPD_spmd) 64 #define PLAT_ARM_SPMC_BASE PLAT_ARM_TRUSTED_DRAM_BASE 65 #define PLAT_ARM_SPMC_SIZE UL(0x200000) /* 2 MB */ 66 #endif 67 68 /* virtual address used by dynamic mem_protect for chunk_base */ 69 #define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xc0000000) 70 71 /* No SCP in FVP */ 72 #define PLAT_ARM_SCP_TZC_DRAM1_SIZE UL(0x0) 73 74 #define PLAT_ARM_DRAM2_BASE ULL(0x880000000) /* 36-bit range */ 75 #define PLAT_ARM_DRAM2_SIZE ULL(0x780000000) /* 30 GB */ 76 77 #define FVP_DRAM3_BASE ULL(0x8800000000) /* 40-bit range */ 78 #define FVP_DRAM3_SIZE ULL(0x7800000000) /* 480 GB */ 79 #define FVP_DRAM3_END (FVP_DRAM3_BASE + FVP_DRAM3_SIZE - 1U) 80 81 #define FVP_DRAM4_BASE ULL(0x88000000000) /* 44-bit range */ 82 #define FVP_DRAM4_SIZE ULL(0x78000000000) /* 7.5 TB */ 83 #define FVP_DRAM4_END (FVP_DRAM4_BASE + FVP_DRAM4_SIZE - 1U) 84 85 #define FVP_DRAM5_BASE ULL(0x880000000000) /* 48-bit range */ 86 #define FVP_DRAM5_SIZE ULL(0x780000000000) /* 120 TB */ 87 #define FVP_DRAM5_END (FVP_DRAM5_BASE + FVP_DRAM5_SIZE - 1U) 88 89 #define FVP_DRAM6_BASE ULL(0x8800000000000) /* 52-bit range */ 90 #define FVP_DRAM6_SIZE ULL(0x7800000000000) /* 1920 TB */ 91 #define FVP_DRAM6_END (FVP_DRAM6_BASE + FVP_DRAM6_SIZE - 1U) 92 93 /* Range of kernel DTB load address */ 94 #define FVP_DTB_DRAM_MAP_START ULL(0x82000000) 95 #define FVP_DTB_DRAM_MAP_SIZE ULL(0x02000000) /* 32 MB */ 96 97 #define ARM_DTB_DRAM_NS MAP_REGION_FLAT( \ 98 FVP_DTB_DRAM_MAP_START, \ 99 FVP_DTB_DRAM_MAP_SIZE, \ 100 MT_MEMORY | MT_RO | MT_NS) 101 102 /* 103 * On the FVP platform when using the EL3 SPMC implementation allocate the 104 * datastore for tracking shared memory descriptors in the TZC DRAM section 105 * to ensure sufficient storage can be allocated. 106 * Provide an implementation of the accessor method to allow the datastore 107 * details to be retrieved by the SPMC. 108 * The SPMC will take care of initializing the memory region. 109 */ 110 111 #define PLAT_SPMC_SHMEM_DATASTORE_SIZE 512 * 1024 112 113 /* Define memory configuration for device tree files. */ 114 #define PLAT_ARM_HW_CONFIG_SIZE U(0x4000) 115 116 #if SPMC_AT_EL3 117 /* 118 * Number of Secure Partitions supported. 119 * SPMC at EL3, uses this count to configure the maximum number of supported 120 * secure partitions. 121 */ 122 #define SECURE_PARTITION_COUNT 1 123 124 /* 125 * Number of Normal World Partitions supported. 126 * SPMC at EL3, uses this count to configure the maximum number of supported 127 * NWd partitions. 128 */ 129 #define NS_PARTITION_COUNT 1 130 131 /* 132 * Number of Logical Partitions supported. 133 * SPMC at EL3, uses this count to configure the maximum number of supported 134 * logical partitions. 135 */ 136 #define MAX_EL3_LP_DESCS_COUNT 1 137 138 #endif /* SPMC_AT_EL3 */ 139 140 /* 141 * Load address of BL33 for this platform port 142 */ 143 #define PLAT_ARM_NS_IMAGE_BASE (ARM_DRAM1_BASE + UL(0x8000000)) 144 145 #if TRANSFER_LIST 146 #define PLAT_ARM_FW_HANDOFF_SIZE U(0x5000) 147 148 #define FW_NS_HANDOFF_BASE (PLAT_ARM_NS_IMAGE_BASE - PLAT_ARM_FW_HANDOFF_SIZE) 149 #define PLAT_ARM_EL3_FW_HANDOFF_BASE ARM_BL_RAM_BASE 150 #define PLAT_ARM_EL3_FW_HANDOFF_LIMIT PLAT_ARM_EL3_FW_HANDOFF_BASE + PLAT_ARM_FW_HANDOFF_SIZE 151 152 #if RESET_TO_BL31 153 #define PLAT_ARM_TRANSFER_LIST_DTB_OFFSET FW_NS_HANDOFF_BASE + TRANSFER_LIST_DTB_OFFSET 154 #endif 155 156 #else 157 #define PLAT_ARM_FW_HANDOFF_SIZE U(0) 158 #endif 159 160 /* 161 * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the 162 * plat_arm_mmap array defined for each BL stage. 163 */ 164 #if defined(IMAGE_BL31) 165 # if SPM_MM 166 # define PLAT_ARM_MMAP_ENTRIES 10 167 # define MAX_XLAT_TABLES 9 168 # define PLAT_SP_IMAGE_MMAP_REGIONS 30 169 # define PLAT_SP_IMAGE_MAX_XLAT_TABLES 10 170 # elif SPMC_AT_EL3 171 # define PLAT_ARM_MMAP_ENTRIES 13 172 # define MAX_XLAT_TABLES 11 173 # define PLAT_SP_IMAGE_MMAP_REGIONS 30 174 # define PLAT_SP_IMAGE_MAX_XLAT_TABLES 10 175 # else 176 # define PLAT_ARM_MMAP_ENTRIES 9 177 # if USE_DEBUGFS 178 # if ENABLE_RME 179 # define MAX_XLAT_TABLES 9 180 # else 181 # define MAX_XLAT_TABLES 8 182 # endif 183 # else 184 # if ENABLE_RME 185 # define MAX_XLAT_TABLES 8 186 # elif DRTM_SUPPORT 187 # define MAX_XLAT_TABLES 8 188 # else 189 # define MAX_XLAT_TABLES 7 190 # endif 191 # endif 192 # endif 193 #elif defined(IMAGE_BL32) 194 # if SPMC_AT_EL3 195 # define PLAT_ARM_MMAP_ENTRIES 270 196 # define MAX_XLAT_TABLES 10 197 # else 198 # define PLAT_ARM_MMAP_ENTRIES 9 199 # define MAX_XLAT_TABLES 6 200 # endif 201 #elif !USE_ROMLIB 202 # if ENABLE_RME && defined(IMAGE_BL2) 203 # define PLAT_ARM_MMAP_ENTRIES 12 204 # define MAX_XLAT_TABLES 6 205 # else 206 # define PLAT_ARM_MMAP_ENTRIES 11 207 # define MAX_XLAT_TABLES 5 208 # endif /* (IMAGE_BL2 && ENABLE_RME) */ 209 #else 210 # define PLAT_ARM_MMAP_ENTRIES 12 211 # if (defined(SPD_tspd) || defined(SPD_opteed) || defined(SPD_spmd)) && \ 212 defined(IMAGE_BL2) && MEASURED_BOOT 213 # define MAX_XLAT_TABLES 7 214 # else 215 # define MAX_XLAT_TABLES 6 216 # endif /* (SPD_tspd || SPD_opteed || SPD_spmd) && IMAGE_BL2 && MEASURED_BOOT */ 217 #endif 218 219 /* 220 * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size 221 * plus a little space for growth. 222 * In case of PSA Crypto API, few algorithms like ECDSA needs bigger BL1 RW 223 * area. 224 */ 225 #if TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_RSA_AND_ECDSA || PSA_CRYPTO || \ 226 FVP_TRUSTED_SRAM_SIZE == 512 227 #define PLAT_ARM_MAX_BL1_RW_SIZE UL(0xC000) 228 #else 229 #define PLAT_ARM_MAX_BL1_RW_SIZE UL(0xB000) 230 #endif 231 232 /* 233 * PLAT_ARM_MAX_ROMLIB_RW_SIZE is define to use a full page 234 */ 235 236 #if USE_ROMLIB 237 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0x1000) 238 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0xe000) 239 #define FVP_BL2_ROMLIB_OPTIMIZATION UL(0x5000) 240 #else 241 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0) 242 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0) 243 #define FVP_BL2_ROMLIB_OPTIMIZATION UL(0) 244 #endif 245 246 /* 247 * Set the maximum size of BL2 to be close to half of the Trusted SRAM. 248 * Maximum size of BL2 increases as Trusted SRAM size increases. 249 */ 250 #if CRYPTO_SUPPORT 251 #if (TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_RSA_AND_ECDSA) || COT_DESC_IN_DTB 252 # define PLAT_ARM_MAX_BL2_SIZE ((PLAT_ARM_TRUSTED_SRAM_SIZE / 2) - \ 253 (2 * PAGE_SIZE) - \ 254 FVP_BL2_ROMLIB_OPTIMIZATION) 255 #else 256 # define PLAT_ARM_MAX_BL2_SIZE ((PLAT_ARM_TRUSTED_SRAM_SIZE / 2) - \ 257 (3 * PAGE_SIZE) - \ 258 FVP_BL2_ROMLIB_OPTIMIZATION) 259 #endif 260 #elif ARM_BL31_IN_DRAM 261 /* When ARM_BL31_IN_DRAM is set, BL2 can use almost all of Trusted SRAM. */ 262 # define PLAT_ARM_MAX_BL2_SIZE (UL(0x1F000) - FVP_BL2_ROMLIB_OPTIMIZATION) 263 #else 264 /** 265 * Default to just under half of SRAM to ensure there's enough room for really 266 * large BL31 build configurations when using the default SRAM size (256 Kb). 267 */ 268 #define PLAT_ARM_MAX_BL2_SIZE \ 269 (((PLAT_ARM_TRUSTED_SRAM_SIZE / 3) & ~PAGE_SIZE_MASK) - PAGE_SIZE - \ 270 FVP_BL2_ROMLIB_OPTIMIZATION) 271 #endif 272 273 #if RESET_TO_BL31 274 /* Size of Trusted SRAM - the first 4KB of shared memory - GPT L0 Tables */ 275 #define PLAT_ARM_MAX_BL31_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ 276 ARM_SHARED_RAM_SIZE - \ 277 ARM_L0_GPT_SIZE) 278 #else 279 /* 280 * Since BL31 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL31_SIZE is 281 * calculated using the current BL31 PROGBITS debug size plus the sizes of 282 * BL2 and BL1-RW. 283 * Size of the BL31 PROGBITS increases as the SRAM size increases. 284 */ 285 #if TRANSFER_LIST 286 #define PLAT_ARM_MAX_BL31_SIZE \ 287 (PLAT_ARM_TRUSTED_SRAM_SIZE - ARM_SHARED_RAM_SIZE - \ 288 PLAT_ARM_FW_HANDOFF_SIZE - ARM_L0_GPT_SIZE) 289 #else 290 #define PLAT_ARM_MAX_BL31_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ 291 ARM_SHARED_RAM_SIZE - \ 292 ARM_FW_CONFIGS_SIZE - ARM_L0_GPT_SIZE) 293 #endif /* TRANSFER_LIST */ 294 #endif /* RESET_TO_BL31 */ 295 296 #ifndef __aarch64__ 297 #if RESET_TO_SP_MIN 298 /* Size of Trusted SRAM - the first 4KB of shared memory */ 299 #define PLAT_ARM_MAX_BL32_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ 300 ARM_SHARED_RAM_SIZE) 301 #else 302 /* 303 * Since BL32 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL32_SIZE is 304 * calculated using the current SP_MIN PROGBITS debug size plus the sizes of 305 * BL2 and BL1-RW 306 */ 307 # define PLAT_ARM_MAX_BL32_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ 308 ARM_SHARED_RAM_SIZE - \ 309 ARM_FW_CONFIGS_SIZE) 310 #endif /* RESET_TO_SP_MIN */ 311 #endif 312 313 /* 314 * Size of cacheable stacks 315 */ 316 #if defined(IMAGE_BL1) 317 # if CRYPTO_SUPPORT 318 # define PLATFORM_STACK_SIZE UL(0x1000) 319 # else 320 # define PLATFORM_STACK_SIZE UL(0x500) 321 # endif /* CRYPTO_SUPPORT */ 322 #elif defined(IMAGE_BL2) 323 # if CRYPTO_SUPPORT 324 # define PLATFORM_STACK_SIZE UL(0x1000) 325 # else 326 # define PLATFORM_STACK_SIZE UL(0x600) 327 # endif /* CRYPTO_SUPPORT */ 328 #elif defined(IMAGE_BL2U) 329 # define PLATFORM_STACK_SIZE UL(0x400) 330 #elif defined(IMAGE_BL31) 331 # if DRTM_SUPPORT 332 # define PLATFORM_STACK_SIZE UL(0x1000) 333 # else 334 # define PLATFORM_STACK_SIZE UL(0x800) 335 # endif /* DRTM_SUPPORT */ 336 #elif defined(IMAGE_BL32) 337 # if SPMC_AT_EL3 338 # define PLATFORM_STACK_SIZE UL(0x1000) 339 # else 340 # define PLATFORM_STACK_SIZE UL(0x440) 341 # endif /* SPMC_AT_EL3 */ 342 #elif defined(IMAGE_RMM) 343 # define PLATFORM_STACK_SIZE UL(0x440) 344 #endif 345 346 #define MAX_IO_DEVICES 3 347 #define MAX_IO_HANDLES 4 348 349 /* Reserve the last block of flash for PSCI MEM PROTECT flag */ 350 #define PLAT_ARM_FLASH_IMAGE_BASE V2M_FLASH0_BASE 351 #define PLAT_ARM_FLASH_IMAGE_MAX_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) 352 353 #if ARM_GPT_SUPPORT 354 /* 355 * Offset of the FIP in the GPT image. BL1 component uses this option 356 * as it does not load the partition table to get the FIP base 357 * address. At sector 34 by default (i.e. after reserved sectors 0-33) 358 * Offset = 34 * 512(sector size) = 17408 i.e. 0x4400 359 */ 360 #define PLAT_ARM_FIP_OFFSET_IN_GPT 0x4400 361 #endif /* ARM_GPT_SUPPORT */ 362 363 #define PLAT_ARM_NVM_BASE V2M_FLASH0_BASE 364 #define PLAT_ARM_NVM_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) 365 366 /* 367 * PL011 related constants 368 */ 369 #define PLAT_ARM_BOOT_UART_BASE V2M_IOFPGA_UART0_BASE 370 #define PLAT_ARM_BOOT_UART_CLK_IN_HZ V2M_IOFPGA_UART0_CLK_IN_HZ 371 372 #define PLAT_ARM_RUN_UART_BASE V2M_IOFPGA_UART1_BASE 373 #define PLAT_ARM_RUN_UART_CLK_IN_HZ V2M_IOFPGA_UART1_CLK_IN_HZ 374 375 #define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_RUN_UART_BASE 376 #define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_RUN_UART_CLK_IN_HZ 377 378 #define PLAT_ARM_TSP_UART_BASE V2M_IOFPGA_UART2_BASE 379 #define PLAT_ARM_TSP_UART_CLK_IN_HZ V2M_IOFPGA_UART2_CLK_IN_HZ 380 381 #define PLAT_ARM_TRP_UART_BASE V2M_IOFPGA_UART3_BASE 382 #define PLAT_ARM_TRP_UART_CLK_IN_HZ V2M_IOFPGA_UART3_CLK_IN_HZ 383 384 #define PLAT_FVP_SMMUV3_BASE UL(0x2b400000) 385 #define PLAT_ARM_SMMUV3_ROOT_REG_OFFSET UL(0x20000) 386 387 /* CCI related constants */ 388 #define PLAT_FVP_CCI400_BASE UL(0x2c090000) 389 #define PLAT_FVP_CCI400_CLUS0_SL_PORT 3 390 #define PLAT_FVP_CCI400_CLUS1_SL_PORT 4 391 392 /* CCI-500/CCI-550 on Base platform */ 393 #define PLAT_FVP_CCI5XX_BASE UL(0x2a000000) 394 #define PLAT_FVP_CCI5XX_CLUS0_SL_PORT 5 395 #define PLAT_FVP_CCI5XX_CLUS1_SL_PORT 6 396 397 /* CCN related constants. Only CCN 502 is currently supported */ 398 #define PLAT_ARM_CCN_BASE UL(0x2e000000) 399 #define PLAT_ARM_CLUSTER_TO_CCN_ID_MAP 1, 5, 7, 11 400 401 /* System timer related constants */ 402 #define PLAT_ARM_NSTIMER_FRAME_ID U(1) 403 404 /* Mailbox base address */ 405 #define PLAT_ARM_TRUSTED_MAILBOX_BASE ARM_TRUSTED_SRAM_BASE 406 407 408 /* TrustZone controller related constants 409 * 410 * Currently only filters 0 and 2 are connected on Base FVP. 411 * Filter 0 : CPU clusters (no access to DRAM by default) 412 * Filter 1 : not connected 413 * Filter 2 : LCDs (access to VRAM allowed by default) 414 * Filter 3 : not connected 415 * Programming unconnected filters will have no effect at the 416 * moment. These filter could, however, be connected in future. 417 * So care should be taken not to configure the unused filters. 418 * 419 * Allow only non-secure access to all DRAM to supported devices. 420 * Give access to the CPUs and Virtio. Some devices 421 * would normally use the default ID so allow that too. 422 */ 423 #define PLAT_ARM_TZC_BASE UL(0x2a4a0000) 424 #define PLAT_ARM_TZC_FILTERS TZC_400_REGION_ATTR_FILTER_BIT(0) 425 426 #define PLAT_ARM_TZC_NS_DEV_ACCESS ( \ 427 TZC_REGION_ACCESS_RDWR(FVP_NSAID_DEFAULT) | \ 428 TZC_REGION_ACCESS_RDWR(FVP_NSAID_PCI) | \ 429 TZC_REGION_ACCESS_RDWR(FVP_NSAID_AP) | \ 430 TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO) | \ 431 TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO_OLD)) 432 433 /* 434 * GIC related constants to cater for both GICv2 and GICv3 instances of an 435 * FVP. They could be overridden at runtime in case the FVP implements the 436 * legacy VE memory map. 437 */ 438 #define PLAT_ARM_GICD_BASE BASE_GICD_BASE 439 #define PLAT_ARM_GICR_BASE BASE_GICR_BASE 440 #define PLAT_ARM_GICC_BASE BASE_GICC_BASE 441 442 /* 443 * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 444 * terminology. On a GICv2 system or mode, the lists will be merged and treated 445 * as Group 0 interrupts. 446 */ 447 #define PLAT_ARM_G1S_IRQ_PROPS(grp) \ 448 ARM_G1S_IRQ_PROPS(grp), \ 449 INTR_PROP_DESC(FVP_IRQ_TZ_WDOG, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 450 GIC_INTR_CFG_LEVEL), \ 451 INTR_PROP_DESC(FVP_IRQ_SEC_SYS_TIMER, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 452 GIC_INTR_CFG_LEVEL) 453 454 #define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp) 455 456 #if SDEI_IN_FCONF 457 #define PLAT_SDEI_DP_EVENT_MAX_CNT ARM_SDEI_DP_EVENT_MAX_CNT 458 #define PLAT_SDEI_DS_EVENT_MAX_CNT ARM_SDEI_DS_EVENT_MAX_CNT 459 #else 460 #if PLATFORM_TEST_RAS_FFH || PLATFORM_TEST_FFH_LSP_RAS_SP 461 #define PLAT_ARM_PRIVATE_SDEI_EVENTS \ 462 ARM_SDEI_PRIVATE_EVENTS, \ 463 SDEI_EXPLICIT_EVENT(5000, SDEI_MAPF_NORMAL), \ 464 SDEI_EXPLICIT_EVENT(5001, SDEI_MAPF_NORMAL), \ 465 SDEI_EXPLICIT_EVENT(5002, SDEI_MAPF_NORMAL), \ 466 SDEI_EXPLICIT_EVENT(5003, SDEI_MAPF_CRITICAL), \ 467 SDEI_EXPLICIT_EVENT(5004, SDEI_MAPF_CRITICAL) 468 #else 469 #define PLAT_ARM_PRIVATE_SDEI_EVENTS ARM_SDEI_PRIVATE_EVENTS 470 #endif 471 #define PLAT_ARM_SHARED_SDEI_EVENTS ARM_SDEI_SHARED_EVENTS 472 #endif 473 474 #define PLAT_ARM_SP_IMAGE_STACK_BASE (PLAT_SP_IMAGE_NS_BUF_BASE + \ 475 PLAT_SP_IMAGE_NS_BUF_SIZE) 476 477 #define PLAT_SP_PRI 0x20 478 479 /* 480 * Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes 481 */ 482 #ifdef __aarch64__ 483 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 36) 484 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 36) 485 #else 486 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 487 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 488 #endif 489 490 /* 491 * Maximum size of Event Log buffer used in Measured Boot Event Log driver 492 */ 493 #if ENABLE_RME && (defined(SPD_tspd) || defined(SPD_opteed) || defined(SPD_spmd)) 494 /* Account for additional measurements of secure partitions and SPM. */ 495 #define PLAT_ARM_EVENT_LOG_MAX_SIZE UL(0x800) 496 #else 497 #define PLAT_ARM_EVENT_LOG_MAX_SIZE UL(0x400) 498 #endif 499 500 /* 501 * Maximum size of Event Log buffer used for DRTM 502 */ 503 #define PLAT_DRTM_EVENT_LOG_MAX_SIZE UL(0x300) 504 505 /* 506 * Number of MMAP entries used by DRTM implementation 507 */ 508 #define PLAT_DRTM_MMAP_ENTRIES PLAT_ARM_MMAP_ENTRIES 509 510 #endif /* PLATFORM_DEF_H */ 511