1 /* 2 * Copyright (c) 2021-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef CORTEX_X2_H 8 #define CORTEX_X2_H 9 10 #define CORTEX_X2_MIDR U(0x410FD480) 11 12 /* Cortex-X2 loop count for CVE-2022-23960 mitigation */ 13 #define CORTEX_X2_BHB_LOOP_COUNT U(32) 14 15 /******************************************************************************* 16 * CPU Extended Control register specific definitions 17 ******************************************************************************/ 18 #define CORTEX_X2_CPUECTLR_EL1 S3_0_C15_C1_4 19 #define CORTEX_X2_CPUECTLR_EL1_PFSTIDIS_BIT (ULL(1) << 8) 20 21 /******************************************************************************* 22 * CPU Auxiliary Control register 3 specific definitions. 23 ******************************************************************************/ 24 #define CORTEX_X2_CPUACTLR3_EL1 S3_0_C15_C1_2 25 26 /******************************************************************************* 27 * CPU Power Control register specific definitions 28 ******************************************************************************/ 29 #define CORTEX_X2_CPUPWRCTLR_EL1 S3_0_C15_C2_7 30 #define CORTEX_X2_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) 31 32 /******************************************************************************* 33 * CPU Auxiliary Control Register definitions 34 ******************************************************************************/ 35 #define CORTEX_X2_CPUACTLR_EL1 S3_0_C15_C1_0 36 #define CORTEX_X2_CPUACTLR_EL1_BIT_22 (ULL(1) << 22) 37 38 /******************************************************************************* 39 * CPU Auxiliary Control Register 2 definitions 40 ******************************************************************************/ 41 #define CORTEX_X2_CPUACTLR2_EL1 S3_0_C15_C1_1 42 #define CORTEX_X2_CPUACTLR2_EL1_BIT_40 (ULL(1) << 40) 43 44 /******************************************************************************* 45 * CPU Auxiliary Control Register 5 definitions 46 ******************************************************************************/ 47 #define CORTEX_X2_CPUACTLR5_EL1 S3_0_C15_C8_0 48 #define CORTEX_X2_CPUACTLR5_EL1_BIT_17 (ULL(1) << 17) 49 50 /******************************************************************************* 51 * CPU Implementation Specific Selected Instruction registers 52 ******************************************************************************/ 53 #define CORTEX_X2_IMP_CPUPSELR_EL3 S3_6_C15_C8_0 54 #define CORTEX_X2_IMP_CPUPCR_EL3 S3_6_C15_C8_1 55 #define CORTEX_X2_IMP_CPUPOR_EL3 S3_6_C15_C8_2 56 #define CORTEX_X2_IMP_CPUPMR_EL3 S3_6_C15_C8_3 57 58 #ifndef __ASSEMBLER__ 59 long check_erratum_cortex_x2_3701772(long cpu_rev); 60 #endif /* __ASSEMBLER__ */ 61 62 #endif /* CORTEX_X2_H */ 63