1 /* 2 * Copyright (c) 2016-2024, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <stddef.h> 9 #include <stdint.h> 10 #include <string.h> 11 12 #include <platform_def.h> 13 14 #include <arch.h> 15 #include <arch_helpers.h> 16 #include <common/bl_common.h> 17 #include <common/build_message.h> 18 #include <common/debug.h> 19 #include <common/runtime_svc.h> 20 #include <context.h> 21 #include <drivers/console.h> 22 #include <lib/el3_runtime/context_mgmt.h> 23 #include <lib/pmf/pmf.h> 24 #include <lib/psci/psci.h> 25 #include <lib/runtime_instr.h> 26 #include <lib/utils.h> 27 #include <plat/common/platform.h> 28 #include <platform_sp_min.h> 29 #include <services/std_svc.h> 30 #include <smccc_helpers.h> 31 32 #include "sp_min_private.h" 33 34 #if ENABLE_RUNTIME_INSTRUMENTATION 35 PMF_REGISTER_SERVICE_SMC(rt_instr_svc, PMF_RT_INSTR_SVC_ID, 36 RT_INSTR_TOTAL_IDS, PMF_STORE_ENABLE) 37 #endif 38 39 /* Pointers to per-core cpu contexts */ 40 static void *sp_min_cpu_ctx_ptr[PLATFORM_CORE_COUNT]; 41 42 /* SP_MIN only stores the non secure smc context */ 43 static smc_ctx_t sp_min_smc_context[PLATFORM_CORE_COUNT]; 44 45 /****************************************************************************** 46 * Define the smccc helper library APIs 47 *****************************************************************************/ 48 void *smc_get_ctx(unsigned int security_state) 49 { 50 assert(security_state == NON_SECURE); 51 return &sp_min_smc_context[plat_my_core_pos()]; 52 } 53 54 void smc_set_next_ctx(unsigned int security_state) 55 { 56 assert(security_state == NON_SECURE); 57 /* SP_MIN stores only non secure smc context. Nothing to do here */ 58 } 59 60 void *smc_get_next_ctx(void) 61 { 62 return &sp_min_smc_context[plat_my_core_pos()]; 63 } 64 65 /******************************************************************************* 66 * This function returns a pointer to the most recent 'cpu_context' structure 67 * for the calling CPU that was set as the context for the specified security 68 * state. NULL is returned if no such structure has been specified. 69 ******************************************************************************/ 70 void *cm_get_context(uint32_t security_state) 71 { 72 assert(security_state == NON_SECURE); 73 return sp_min_cpu_ctx_ptr[plat_my_core_pos()]; 74 } 75 76 /******************************************************************************* 77 * This function sets the pointer to the current 'cpu_context' structure for the 78 * specified security state for the calling CPU 79 ******************************************************************************/ 80 void cm_set_context(void *context, uint32_t security_state) 81 { 82 assert(security_state == NON_SECURE); 83 sp_min_cpu_ctx_ptr[plat_my_core_pos()] = context; 84 } 85 86 /******************************************************************************* 87 * This function returns a pointer to the most recent 'cpu_context' structure 88 * for the CPU identified by `cpu_idx` that was set as the context for the 89 * specified security state. NULL is returned if no such structure has been 90 * specified. 91 ******************************************************************************/ 92 void *cm_get_context_by_index(unsigned int cpu_idx, 93 unsigned int security_state) 94 { 95 assert(security_state == NON_SECURE); 96 return sp_min_cpu_ctx_ptr[cpu_idx]; 97 } 98 99 /******************************************************************************* 100 * This function sets the pointer to the current 'cpu_context' structure for the 101 * specified security state for the CPU identified by CPU index. 102 ******************************************************************************/ 103 void cm_set_context_by_index(unsigned int cpu_idx, void *context, 104 unsigned int security_state) 105 { 106 assert(security_state == NON_SECURE); 107 sp_min_cpu_ctx_ptr[cpu_idx] = context; 108 } 109 110 static void copy_cpu_ctx_to_smc_stx(const regs_t *cpu_reg_ctx, 111 smc_ctx_t *next_smc_ctx) 112 { 113 next_smc_ctx->r0 = read_ctx_reg(cpu_reg_ctx, CTX_GPREG_R0); 114 next_smc_ctx->r1 = read_ctx_reg(cpu_reg_ctx, CTX_GPREG_R1); 115 next_smc_ctx->r2 = read_ctx_reg(cpu_reg_ctx, CTX_GPREG_R2); 116 next_smc_ctx->lr_mon = read_ctx_reg(cpu_reg_ctx, CTX_LR); 117 next_smc_ctx->spsr_mon = read_ctx_reg(cpu_reg_ctx, CTX_SPSR); 118 next_smc_ctx->scr = read_ctx_reg(cpu_reg_ctx, CTX_SCR); 119 } 120 121 /******************************************************************************* 122 * This function invokes the PSCI library interface to initialize the 123 * non secure cpu context and copies the relevant cpu context register values 124 * to smc context. These registers will get programmed during `smc_exit`. 125 ******************************************************************************/ 126 static void sp_min_prepare_next_image_entry(void) 127 { 128 entry_point_info_t *next_image_info; 129 cpu_context_t *ctx = cm_get_context(NON_SECURE); 130 u_register_t ns_sctlr; 131 132 /* Program system registers to proceed to non-secure */ 133 next_image_info = sp_min_plat_get_bl33_ep_info(); 134 assert(next_image_info); 135 assert(NON_SECURE == GET_SECURITY_STATE(next_image_info->h.attr)); 136 137 INFO("SP_MIN: Preparing exit to normal world\n"); 138 print_entry_point_info(next_image_info); 139 140 psci_prepare_next_non_secure_ctx(next_image_info); 141 smc_set_next_ctx(NON_SECURE); 142 143 /* Copy r0, lr and spsr from cpu context to SMC context */ 144 copy_cpu_ctx_to_smc_stx(get_regs_ctx(cm_get_context(NON_SECURE)), 145 smc_get_next_ctx()); 146 147 /* Temporarily set the NS bit to access NS SCTLR */ 148 write_scr(read_scr() | SCR_NS_BIT); 149 isb(); 150 ns_sctlr = read_ctx_reg(get_regs_ctx(ctx), CTX_NS_SCTLR); 151 write_sctlr(ns_sctlr); 152 isb(); 153 154 write_scr(read_scr() & ~SCR_NS_BIT); 155 isb(); 156 } 157 158 /****************************************************************************** 159 * Implement the ARM Standard Service function to get arguments for a 160 * particular service. 161 *****************************************************************************/ 162 uintptr_t get_arm_std_svc_args(unsigned int svc_mask) 163 { 164 /* Setup the arguments for PSCI Library */ 165 DEFINE_STATIC_PSCI_LIB_ARGS_V1(psci_args, sp_min_warm_entrypoint); 166 167 /* PSCI is the only ARM Standard Service implemented */ 168 assert(svc_mask == PSCI_FID_MASK); 169 170 return (uintptr_t)&psci_args; 171 } 172 173 /****************************************************************************** 174 * The SP_MIN main function. Do the platform and PSCI Library setup. Also 175 * initialize the runtime service framework. 176 *****************************************************************************/ 177 void sp_min_main(void) 178 { 179 NOTICE("SP_MIN: %s\n", build_version_string); 180 NOTICE("SP_MIN: %s\n", build_message); 181 182 /* Perform the SP_MIN platform setup */ 183 sp_min_platform_setup(); 184 185 /* Initialize the runtime services e.g. psci */ 186 INFO("SP_MIN: Initializing runtime services\n"); 187 runtime_svc_init(); 188 189 /* 190 * We are ready to enter the next EL. Prepare entry into the image 191 * corresponding to the desired security state after the next ERET. 192 */ 193 sp_min_prepare_next_image_entry(); 194 195 /* 196 * Perform any platform specific runtime setup prior to cold boot exit 197 * from SP_MIN. 198 */ 199 sp_min_plat_runtime_setup(); 200 201 console_flush(); 202 } 203 204 /****************************************************************************** 205 * This function is invoked during warm boot. Invoke the PSCI library 206 * warm boot entry point which takes care of Architectural and platform setup/ 207 * restore. Copy the relevant cpu_context register values to smc context which 208 * will get programmed during `smc_exit`. 209 *****************************************************************************/ 210 void sp_min_warm_boot(void) 211 { 212 smc_ctx_t *next_smc_ctx; 213 cpu_context_t *ctx = cm_get_context(NON_SECURE); 214 u_register_t ns_sctlr; 215 216 psci_warmboot_entrypoint(); 217 218 smc_set_next_ctx(NON_SECURE); 219 220 next_smc_ctx = smc_get_next_ctx(); 221 zeromem(next_smc_ctx, sizeof(smc_ctx_t)); 222 223 copy_cpu_ctx_to_smc_stx(get_regs_ctx(cm_get_context(NON_SECURE)), 224 next_smc_ctx); 225 226 /* Temporarily set the NS bit to access NS SCTLR */ 227 write_scr(read_scr() | SCR_NS_BIT); 228 isb(); 229 ns_sctlr = read_ctx_reg(get_regs_ctx(ctx), CTX_NS_SCTLR); 230 write_sctlr(ns_sctlr); 231 isb(); 232 233 write_scr(read_scr() & ~SCR_NS_BIT); 234 isb(); 235 } 236 237 #if SP_MIN_WITH_SECURE_FIQ 238 /****************************************************************************** 239 * This function is invoked on secure interrupts. By construction of the 240 * SP_MIN, secure interrupts can only be handled when core executes in non 241 * secure state. 242 *****************************************************************************/ 243 void sp_min_fiq(void) 244 { 245 uint32_t id; 246 247 id = plat_ic_acknowledge_interrupt(); 248 sp_min_plat_fiq_handler(id); 249 plat_ic_end_of_interrupt(id); 250 } 251 #endif /* SP_MIN_WITH_SECURE_FIQ */ 252