1 /* 2 * Copyright (c) 2022, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2021-2022, Xilinx, Inc. All rights reserved. 4 * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #ifndef DEF_H 10 #define DEF_H 11 12 #include <plat/arm/common/smccc_def.h> 13 #include <plat/common/common_def.h> 14 15 #define MAX_INTR_EL3 2U 16 17 /* List all consoles */ 18 #define VERSAL2_CONSOLE_ID_none 0 19 #define VERSAL2_CONSOLE_ID_pl011 1 20 #define VERSAL2_CONSOLE_ID_pl011_0 1 21 #define VERSAL2_CONSOLE_ID_pl011_1 2 22 #define VERSAL2_CONSOLE_ID_dcc 3 23 #define VERSAL2_CONSOLE_ID_dtb 4 24 25 #define CONSOLE_IS(con) (VERSAL2_CONSOLE_ID_ ## con == VERSAL2_CONSOLE) 26 27 /* Runtime console */ 28 #define RT_CONSOLE_ID_pl011 1 29 #define RT_CONSOLE_ID_pl011_0 1 30 #define RT_CONSOLE_ID_pl011_1 2 31 #define RT_CONSOLE_ID_dcc 3 32 #define RT_CONSOLE_ID_dtb 4 33 34 #define RT_CONSOLE_IS(con) (RT_CONSOLE_ID_ ## con == CONSOLE_RUNTIME) 35 36 /* List all platforms */ 37 #define SILICON U(0) 38 #define SPP U(1) 39 #define EMU U(2) 40 #define QEMU U(3) 41 #define SPP_MMD U(5) 42 #define EMU_MMD U(6) 43 #define QEMU_COSIM U(7) 44 45 /* For platform detection */ 46 #define PMC_TAP U(0xF11A0000) 47 #define PMC_TAP_VERSION (PMC_TAP + 0x4U) 48 # define PLATFORM_MASK GENMASK(27U, 24U) 49 # define PLATFORM_VERSION_MASK GENMASK(31U, 28U) 50 51 /* Global timer reset */ 52 #define PSX_CRF U(0xEC200000) 53 #define ACPU0_CLK_CTRL U(0x10C) 54 #define ACPU_CLK_CTRL_CLKACT BIT(25) 55 56 #define RST_APU0_OFFSET U(0x300) 57 #define RST_APU_COLD_RESET BIT(0) 58 #define RST_APU_WARN_RESET BIT(4) 59 #define RST_APU_CLUSTER_COLD_RESET BIT(8) 60 #define RST_APU_CLUSTER_WARM_RESET BIT(9) 61 62 #define PSX_CRF_RST_TIMESTAMP_OFFSET U(0x33C) 63 64 #define APU_PCLI (0xECB10000ULL) 65 #define APU_PCLI_CPU_STEP (0x30ULL) 66 #define APU_PCLI_CLUSTER_CPU_STEP (4ULL * APU_PCLI_CPU_STEP) 67 #define APU_PCLI_CLUSTER_OFFSET U(0x8000) 68 #define APU_PCLI_CLUSTER_STEP U(0x1000) 69 #define PCLI_PREQ_OFFSET U(0x4) 70 #define PREQ_CHANGE_REQUEST BIT(0) 71 #define PCLI_PSTATE_OFFSET U(0x8) 72 #define PCLI_PSTATE_VAL_SET U(0x48) 73 #define PCLI_PSTATE_VAL_CLEAR U(0x38) 74 75 /* Firmware Image Package */ 76 #define PRIMARY_CPU U(0) 77 78 #define CORE_0_ISR_WAKE_OFFSET (0x00000020ULL) 79 #define APU_PCIL_CORE_X_ISR_WAKE_REG(cpu_id) (APU_PCLI + (CORE_0_ISR_WAKE_OFFSET + \ 80 (APU_PCLI_CPU_STEP * (cpu_id)))) 81 #define APU_PCIL_CORE_X_ISR_WAKE_MASK (0x00000001U) 82 #define CORE_0_IEN_WAKE_OFFSET (0x00000028ULL) 83 #define APU_PCIL_CORE_X_IEN_WAKE_REG(cpu_id) (APU_PCLI + (CORE_0_IEN_WAKE_OFFSET + \ 84 (APU_PCLI_CPU_STEP * (cpu_id)))) 85 #define APU_PCIL_CORE_X_IEN_WAKE_MASK (0x00000001U) 86 #define CORE_0_IDS_WAKE_OFFSET (0x0000002CULL) 87 #define APU_PCIL_CORE_X_IDS_WAKE_REG(cpu_id) (APU_PCLI + (CORE_0_IDS_WAKE_OFFSET + \ 88 (APU_PCLI_CPU_STEP * (cpu_id)))) 89 #define APU_PCIL_CORE_X_IDS_WAKE_MASK (0x00000001U) 90 #define CORE_0_ISR_POWER_OFFSET (0x00000010ULL) 91 #define APU_PCIL_CORE_X_ISR_POWER_REG(cpu_id) (APU_PCLI + (CORE_0_ISR_POWER_OFFSET + \ 92 (APU_PCLI_CPU_STEP * (cpu_id)))) 93 #define APU_PCIL_CORE_X_ISR_POWER_MASK U(0x00000001) 94 #define CORE_0_IEN_POWER_OFFSET (0x00000018ULL) 95 #define APU_PCIL_CORE_X_IEN_POWER_REG(cpu_id) (APU_PCLI + (CORE_0_IEN_POWER_OFFSET + \ 96 (APU_PCLI_CPU_STEP * (cpu_id)))) 97 #define APU_PCIL_CORE_X_IEN_POWER_MASK (0x00000001U) 98 #define CORE_0_IDS_POWER_OFFSET (0x0000001CULL) 99 #define APU_PCIL_CORE_X_IDS_POWER_REG(cpu_id) (APU_PCLI + (CORE_0_IDS_POWER_OFFSET + \ 100 (APU_PCLI_CPU_STEP * (cpu_id)))) 101 #define APU_PCIL_CORE_X_IDS_POWER_MASK (0x00000001U) 102 #define CORE_PWRDN_EN_BIT_MASK (0x1U) 103 104 /******************************************************************************* 105 * memory map related constants 106 ******************************************************************************/ 107 /* IPP 1.2/SPP 0.9 mapping */ 108 #define DEVICE0_BASE U(0xE8000000) /* psx, crl, iou */ 109 #define DEVICE0_SIZE U(0x08000000) 110 #define DEVICE1_BASE U(0xE2000000) /* gic */ 111 #define DEVICE1_SIZE U(0x00800000) 112 #define DEVICE2_BASE U(0xF1000000) /* uart, pmc_tap */ 113 #define DEVICE2_SIZE U(0x01000000) 114 #define CRF_BASE U(0xFD1A0000) 115 #define CRF_SIZE U(0x00600000) 116 #define IPI_BASE U(0xEB300000) 117 #define IPI_SIZE U(0x00100000) 118 119 /* CRL */ 120 #define CRL U(0xEB5E0000) 121 #define CRL_TIMESTAMP_REF_CTRL_OFFSET U(0x14C) 122 #define CRL_RST_TIMESTAMP_OFFSET U(0x348) 123 124 #define CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT (1U << 25U) 125 126 /* IOU SCNTRS */ 127 #define IOU_SCNTRS U(0xEC920000) 128 #define IOU_SCNTRS_COUNTER_CONTROL_REG_OFFSET U(0) 129 #define IOU_SCNTRS_BASE_FREQ_OFFSET U(0x20) 130 131 #define IOU_SCNTRS_CONTROL_EN U(1) 132 133 #define APU_CLUSTER0 U(0xECC00000) 134 #define APU_RVBAR_L_0 U(0x40) 135 #define APU_RVBAR_H_0 U(0x44) 136 #define APU_CLUSTER_STEP U(0x100000) 137 138 #define SLCR_OSPI_QSPI_IOU_AXI_MUX_SEL U(0xF1060504) 139 #define PMXC_IOU_SLCR_SRAM_CSR U(0xF106104C) 140 #define PMXC_IOU_SLCR_PHY_RESET U(0xF1061050) 141 #define PMXC_IOU_SLCR_TX_RX_CONFIG_RDY U(0xF1061054) 142 #define PMXC_CRP_RST_UFS U(0xF1260340) 143 144 /******************************************************************************* 145 * IRQ constants 146 ******************************************************************************/ 147 #define IRQ_SEC_PHY_TIMER U(29) 148 149 /******************************************************************************* 150 * UART related constants 151 ******************************************************************************/ 152 #define UART0_BASE U(0xF1920000) 153 #define UART1_BASE U(0xF1930000) 154 155 #define UART_BAUDRATE 115200 156 157 #if CONSOLE_IS(pl011) || CONSOLE_IS(dtb) 158 #define UART_BASE UART0_BASE 159 # define UART_TYPE CONSOLE_PL011 160 #elif CONSOLE_IS(pl011_1) 161 #define UART_BASE UART1_BASE 162 # define UART_TYPE CONSOLE_PL011 163 #elif CONSOLE_IS(dcc) 164 # define UART_BASE 0x0 165 # define UART_TYPE CONSOLE_DCC 166 #elif CONSOLE_IS(none) 167 # define UART_TYPE CONSOLE_NONE 168 #else 169 # error "invalid VERSAL2_CONSOLE" 170 #endif 171 172 /* Runtime console */ 173 #if defined(CONSOLE_RUNTIME) 174 #if RT_CONSOLE_IS(pl011) || RT_CONSOLE_IS(dtb) 175 # define RT_UART_BASE UART0_BASE 176 # define RT_UART_TYPE CONSOLE_PL011 177 #elif RT_CONSOLE_IS(pl011_1) 178 # define RT_UART_BASE UART1_BASE 179 # define RT_UART_TYPE CONSOLE_PL011 180 #elif RT_CONSOLE_IS(dcc) 181 # define RT_UART_BASE 0x0 182 # define RT_UART_TYPE CONSOLE_DCC 183 #else 184 # error "invalid CONSOLE_RUNTIME" 185 #endif 186 #endif 187 188 #endif /* DEF_H */ 189