xref: /rk3399_ARM-atf/plat/mediatek/drivers/apusys/mt8196/apusys_security_ctrl_plat.c (revision 79e7aae82dd173d1ccc63e5d553222f1d58f12f5)
1 /*
2  * Copyright (c) 2024-2025, MediaTek Inc. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #define ENABLE_SMPU_PROTECT	(1)
8 
9 #if ENABLE_SMPU_PROTECT
10 #include "emi.h"
11 #endif
12 
13 #include <common/debug.h>
14 #include <lib/mmio.h>
15 
16 #include <apusys_security_ctrl_plat.h>
17 
18 #define APUSYS_SEC_FW_EMI_REGION	(23)
19 
20 #define bits_clr(x, m, o)	(x & (~(m << o)))
21 #define bits_set(x, v, m, o)	((bits_clr(x, m, o)) | ((v & m) << o))
22 
23 static void sec_sideband_init(void)
24 {
25 	uint32_t value = mmio_read_32(SEC_CTRL_SIDE_BAND);
26 
27 	value = bits_set(value, SEC_CTRL_NARE_DOMAIN, SEC_CTRL_DOMAIN_MASK,
28 			 SEC_CTRL_NARE_DOMAIN_SHF);
29 	value = bits_set(value, SEC_CTRL_NARE_NS, SEC_CTRL_NS_MASK, SEC_CTRL_NARE_NS_SHF);
30 	value = bits_set(value, SEC_CTRL_SARE0_DOMAIN, SEC_CTRL_DOMAIN_MASK,
31 			 SEC_CTRL_SARE0_DOMAIN_SHF);
32 	value = bits_set(value, SEC_CTRL_SARE0_NS, SEC_CTRL_NS_MASK, SEC_CTRL_SARE0_NS_SHF);
33 	value = bits_set(value, SEC_CTRL_SARE1_DOMAIN, SEC_CTRL_DOMAIN_MASK,
34 			 SEC_CTRL_SARE1_DOMAIN_SHF);
35 	value = bits_set(value, SEC_CTRL_SARE1_NS, SEC_CTRL_NS_MASK, SEC_CTRL_SARE1_NS_SHF);
36 
37 	mmio_write_32(SEC_CTRL_SIDE_BAND, value);
38 }
39 
40 static void domain_remap_init(void)
41 {
42 	const uint32_t remap_domains[] = {
43 		D0_REMAP_DOMAIN,  D1_REMAP_DOMAIN,  D2_REMAP_DOMAIN,  D3_REMAP_DOMAIN,
44 		D4_REMAP_DOMAIN,  D5_REMAP_DOMAIN,  D6_REMAP_DOMAIN,  D7_REMAP_DOMAIN,
45 		D8_REMAP_DOMAIN,  D9_REMAP_DOMAIN,  D10_REMAP_DOMAIN, D11_REMAP_DOMAIN,
46 		D12_REMAP_DOMAIN, D13_REMAP_DOMAIN, D14_REMAP_DOMAIN, D15_REMAP_DOMAIN,
47 	};
48 	uint32_t lower_domain = 0;
49 	uint32_t higher_domain = 0;
50 	int i;
51 
52 	for (i = 0; i < ARRAY_SIZE(remap_domains); i++) {
53 		if (i < SEC_CTRL_REG_DOMAIN_NUM)
54 			lower_domain |= (remap_domains[i] << (i * REG_DOMAIN_BITS));
55 		else
56 			higher_domain |= (remap_domains[i] <<
57 					  ((i - SEC_CTRL_REG_DOMAIN_NUM) * REG_DOMAIN_BITS));
58 	}
59 
60 	mmio_write_32(SEC_CTRL_SOC2APU_SET1_0, lower_domain);
61 	mmio_write_32(SEC_CTRL_SOC2APU_SET1_1, higher_domain);
62 	mmio_setbits_32(APU_SEC_CON, SEC_CTRL_DOMAIN_REMAP_SEL);
63 }
64 
65 void apusys_security_ctrl_init(void)
66 {
67 	domain_remap_init();
68 	sec_sideband_init();
69 }
70 
71 int apusys_plat_setup_sec_mem(void)
72 {
73 #if ENABLE_SMPU_PROTECT
74 	return sip_emi_mpu_set_protection(APU_RESERVE_MEMORY >> EMI_MPU_ALIGN_BITS,
75 		(APU_RESERVE_MEMORY + APU_RESERVE_SIZE) >> EMI_MPU_ALIGN_BITS,
76 		APUSYS_SEC_FW_EMI_REGION);
77 #else
78 	INFO("%s: Bypass SMPU protection setup.\n", __func__);
79 	return 0;
80 #endif
81 }
82