1 /* 2 * Copyright (c) 2015-2024, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2020-2023, NVIDIA Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <assert.h> 9 #include <errno.h> 10 #include <inttypes.h> 11 #include <stddef.h> 12 #include <string.h> 13 14 #include <platform_def.h> 15 16 #include <arch.h> 17 #include <arch_helpers.h> 18 #include <bl31/bl31.h> 19 #include <common/bl_common.h> 20 #include <common/debug.h> 21 #include <cortex_a57.h> 22 #include <denver.h> 23 #include <drivers/console.h> 24 #include <lib/mmio.h> 25 #include <lib/utils.h> 26 #include <lib/utils_def.h> 27 #include <plat/common/platform.h> 28 29 #include <memctrl.h> 30 #include <profiler.h> 31 #include <smmu.h> 32 #include <tegra_def.h> 33 #include <tegra_platform.h> 34 #include <tegra_private.h> 35 36 /* length of Trusty's input parameters (in bytes) */ 37 #define TRUSTY_PARAMS_LEN_BYTES (4096*2) 38 39 /******************************************************************************* 40 * Declarations of linker defined symbols which will help us find the layout 41 * of trusted SRAM 42 ******************************************************************************/ 43 IMPORT_SYM(uint64_t, __RW_START__, BL31_RW_START); 44 45 extern uint64_t tegra_bl31_phys_base; 46 47 static entry_point_info_t bl33_image_ep_info, bl32_image_ep_info; 48 static plat_params_from_bl2_t plat_bl31_params_from_bl2 = { 49 .tzdram_size = TZDRAM_SIZE 50 }; 51 #ifdef SPD_trusty 52 static aapcs64_params_t bl32_args; 53 #endif 54 55 /******************************************************************************* 56 * This variable holds the non-secure image entry address 57 ******************************************************************************/ 58 extern uint64_t ns_image_entrypoint; 59 60 /******************************************************************************* 61 * Return a pointer to the 'entry_point_info' structure of the next image for 62 * security state specified. BL33 corresponds to the non-secure image type 63 * while BL32 corresponds to the secure image type. 64 ******************************************************************************/ 65 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 66 { 67 entry_point_info_t *ep = NULL; 68 69 /* return BL32 entry point info if it is valid */ 70 if (type == NON_SECURE) { 71 ep = &bl33_image_ep_info; 72 } else if ((type == SECURE) && (bl32_image_ep_info.pc != 0U)) { 73 ep = &bl32_image_ep_info; 74 } 75 76 return ep; 77 } 78 79 /******************************************************************************* 80 * Return a pointer to the 'plat_params_from_bl2_t' structure. The BL2 image 81 * passes this platform specific information. 82 ******************************************************************************/ 83 plat_params_from_bl2_t *bl31_get_plat_params(void) 84 { 85 return &plat_bl31_params_from_bl2; 86 } 87 88 /******************************************************************************* 89 * Perform any BL31 specific platform actions. Populate the BL33 and BL32 image 90 * info. 91 ******************************************************************************/ 92 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 93 u_register_t arg2, u_register_t arg3) 94 { 95 struct tegra_bl31_params *arg_from_bl2 = plat_get_bl31_params(); 96 plat_params_from_bl2_t *plat_params = plat_get_bl31_plat_params(); 97 int32_t ret; 98 99 /* 100 * Tegra platforms will receive boot parameters through custom 101 * mechanisms. So, we ignore the input parameters. 102 */ 103 (void)arg0; 104 (void)arg1; 105 106 /* 107 * Copy BL3-3, BL3-2 entry point information. 108 * They are stored in Secure RAM, in BL2's address space. 109 */ 110 assert(arg_from_bl2 != NULL); 111 assert(arg_from_bl2->bl33_ep_info != NULL); 112 bl33_image_ep_info = *arg_from_bl2->bl33_ep_info; 113 114 if (arg_from_bl2->bl32_ep_info != NULL) { 115 bl32_image_ep_info = *arg_from_bl2->bl32_ep_info; 116 #ifdef SPD_trusty 117 /* save BL32 boot parameters */ 118 memcpy(&bl32_args, &arg_from_bl2->bl32_ep_info->args, sizeof(bl32_args)); 119 #endif 120 } 121 122 /* 123 * Parse platform specific parameters 124 */ 125 assert(plat_params != NULL); 126 plat_bl31_params_from_bl2.tzdram_base = plat_params->tzdram_base; 127 plat_bl31_params_from_bl2.tzdram_size = plat_params->tzdram_size; 128 plat_bl31_params_from_bl2.uart_id = plat_params->uart_id; 129 plat_bl31_params_from_bl2.l2_ecc_parity_prot_dis = plat_params->l2_ecc_parity_prot_dis; 130 plat_bl31_params_from_bl2.sc7entry_fw_size = plat_params->sc7entry_fw_size; 131 plat_bl31_params_from_bl2.sc7entry_fw_base = plat_params->sc7entry_fw_base; 132 133 /* 134 * It is very important that we run either from TZDRAM or TZSRAM base. 135 * Add an explicit check here. 136 */ 137 if ((plat_bl31_params_from_bl2.tzdram_base != (uint64_t)BL31_BASE) && 138 (TEGRA_TZRAM_BASE != BL31_BASE)) { 139 panic(); 140 } 141 142 /* 143 * Enable console for the platform 144 */ 145 plat_enable_console(plat_params->uart_id); 146 147 /* 148 * The previous bootloader passes the base address of the shared memory 149 * location to store the boot profiler logs. Sanity check the 150 * address and initialise the profiler library, if it looks ok. 151 */ 152 ret = bl31_check_ns_address(plat_params->boot_profiler_shmem_base, 153 PROFILER_SIZE_BYTES); 154 if (ret == (int32_t)0) { 155 156 /* store the membase for the profiler lib */ 157 plat_bl31_params_from_bl2.boot_profiler_shmem_base = 158 plat_params->boot_profiler_shmem_base; 159 160 /* initialise the profiler library */ 161 boot_profiler_init(plat_params->boot_profiler_shmem_base, 162 TEGRA_TMRUS_BASE); 163 } 164 165 /* 166 * Add timestamp for platform early setup entry. 167 */ 168 boot_profiler_add_record("[TF] early setup entry"); 169 170 /* 171 * Initialize delay timer 172 */ 173 tegra_delay_timer_init(); 174 175 /* Early platform setup for Tegra SoCs */ 176 plat_early_platform_setup(); 177 178 /* 179 * Add timestamp for platform early setup exit. 180 */ 181 boot_profiler_add_record("[TF] early setup exit"); 182 183 INFO("BL3-1: Boot CPU: %s Processor [%lx]\n", 184 (((read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK) 185 == DENVER_IMPL) ? "Denver" : "ARM", read_mpidr()); 186 } 187 188 #ifdef SPD_trusty 189 void plat_trusty_set_boot_args(aapcs64_params_t *args) 190 { 191 /* 192 * arg0 = TZDRAM aperture available for BL32 193 * arg1 = BL32 boot params 194 * arg2 = EKS Blob Length 195 * arg3 = Boot Profiler Carveout Base 196 */ 197 args->arg0 = bl32_args.arg0; 198 args->arg1 = bl32_args.arg2; 199 200 /* update EKS size */ 201 args->arg2 = bl32_args.arg4; 202 203 /* Profiler Carveout Base */ 204 args->arg3 = bl32_args.arg5; 205 } 206 #endif 207 208 /******************************************************************************* 209 * Initialize the gic, configure the SCR. 210 ******************************************************************************/ 211 void bl31_platform_setup(void) 212 { 213 /* 214 * Add timestamp for platform setup entry. 215 */ 216 boot_profiler_add_record("[TF] plat setup entry"); 217 218 /* Initialize the gic cpu and distributor interfaces */ 219 plat_gic_setup(); 220 221 /* 222 * Setup secondary CPU POR infrastructure. 223 */ 224 plat_secondary_setup(); 225 226 /* 227 * Initial Memory Controller configuration. 228 */ 229 tegra_memctrl_setup(); 230 231 /* 232 * Late setup handler to allow platforms to performs additional 233 * functionality. 234 * This handler gets called with MMU enabled. 235 */ 236 plat_late_platform_setup(); 237 238 /* 239 * Add timestamp for platform setup exit. 240 */ 241 boot_profiler_add_record("[TF] plat setup exit"); 242 243 INFO("BL3-1: Tegra platform setup complete\n"); 244 } 245 246 /******************************************************************************* 247 * Perform any BL3-1 platform runtime setup prior to BL3-1 cold boot exit 248 ******************************************************************************/ 249 void bl31_plat_runtime_setup(void) 250 { 251 /* 252 * Platform specific runtime setup 253 */ 254 plat_runtime_setup(); 255 256 /* 257 * Add final timestamp before exiting BL31. 258 */ 259 boot_profiler_add_record("[TF] bl31 exit"); 260 boot_profiler_deinit(); 261 } 262 263 /******************************************************************************* 264 * Perform the very early platform specific architectural setup here. At the 265 * moment this only initializes the mmu in a quick and dirty way. 266 ******************************************************************************/ 267 void bl31_plat_arch_setup(void) 268 { 269 uint64_t rw_start = BL31_RW_START; 270 uint64_t rw_size = BL_END - BL31_RW_START; 271 uint64_t rodata_start = BL_RO_DATA_BASE; 272 uint64_t rodata_size = BL_RO_DATA_END - BL_RO_DATA_BASE; 273 uint64_t code_base = BL_CODE_BASE; 274 uint64_t code_size = BL_CODE_END - BL_CODE_BASE; 275 const mmap_region_t *plat_mmio_map = NULL; 276 const plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params(); 277 278 /* 279 * Add timestamp for arch setup entry. 280 */ 281 boot_profiler_add_record("[TF] arch setup entry"); 282 283 /* add MMIO space */ 284 plat_mmio_map = plat_get_mmio_map(); 285 if (plat_mmio_map != NULL) { 286 mmap_add(plat_mmio_map); 287 } else { 288 WARN("MMIO map not available\n"); 289 } 290 291 /* add memory regions */ 292 mmap_add_region(rw_start, rw_start, 293 rw_size, 294 MT_MEMORY | MT_RW | MT_SECURE); 295 mmap_add_region(rodata_start, rodata_start, 296 rodata_size, 297 MT_RO_DATA | MT_SECURE); 298 mmap_add_region(code_base, code_base, 299 code_size, 300 MT_CODE | MT_SECURE); 301 302 /* map TZDRAM used by BL31 as coherent memory */ 303 if (TEGRA_TZRAM_BASE == tegra_bl31_phys_base) { 304 mmap_add_region(params_from_bl2->tzdram_base, 305 params_from_bl2->tzdram_base, 306 BL31_SIZE, 307 MT_DEVICE | MT_RW | MT_SECURE); 308 } 309 310 /* set up translation tables */ 311 init_xlat_tables(); 312 313 /* enable the MMU */ 314 enable_mmu_el3(0); 315 316 /* 317 * Add timestamp for arch setup exit. 318 */ 319 boot_profiler_add_record("[TF] arch setup exit"); 320 321 INFO("BL3-1: Tegra: MMU enabled\n"); 322 } 323 324 /******************************************************************************* 325 * Check if the given NS DRAM range is valid 326 ******************************************************************************/ 327 int32_t bl31_check_ns_address(uint64_t base, uint64_t size_in_bytes) 328 { 329 uint64_t end = base + size_in_bytes - U(1); 330 331 /* 332 * Sanity check the input values 333 */ 334 if ((base == 0U) || (size_in_bytes == 0U)) { 335 ERROR("NS address 0x%" PRIx64 " (%" PRId64 " bytes) is invalid\n", 336 base, size_in_bytes); 337 return -EINVAL; 338 } 339 340 /* 341 * Check if the NS DRAM address is valid 342 */ 343 if ((base < TEGRA_DRAM_BASE) || (base >= TEGRA_DRAM_END) || 344 (end > TEGRA_DRAM_END)) { 345 346 ERROR("NS address 0x%" PRIx64 " is out-of-bounds!\n", base); 347 return -EFAULT; 348 } 349 350 /* 351 * TZDRAM aperture contains the BL31 and BL32 images, so we need 352 * to check if the NS DRAM range overlaps the TZDRAM aperture. 353 */ 354 if ((base < (uint64_t)TZDRAM_END) && (end > tegra_bl31_phys_base)) { 355 ERROR("NS address 0x%" PRIx64 " overlaps TZDRAM!\n", base); 356 return -ENOTSUP; 357 } 358 359 /* valid NS address */ 360 return 0; 361 } 362