1 /* 2 * Copyright (c) 2014-2020, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef ZYNQMP_DEF_H 8 #define ZYNQMP_DEF_H 9 10 #include <plat/arm/common/smccc_def.h> 11 #include <plat/common/common_def.h> 12 13 #define ZYNQMP_CONSOLE_ID_none 0 14 #define ZYNQMP_CONSOLE_ID_cadence 1 15 #define ZYNQMP_CONSOLE_ID_cadence0 1 16 #define ZYNQMP_CONSOLE_ID_cadence1 2 17 #define ZYNQMP_CONSOLE_ID_dcc 3 18 #define ZYNQMP_CONSOLE_ID_dtb 4 19 20 #define CONSOLE_IS(con) (ZYNQMP_CONSOLE_ID_ ## con == ZYNQMP_CONSOLE) 21 22 /* Runtime console */ 23 #define RT_CONSOLE_ID_cadence 1 24 #define RT_CONSOLE_ID_cadence0 1 25 #define RT_CONSOLE_ID_cadence1 2 26 #define RT_CONSOLE_ID_dcc 3 27 #define RT_CONSOLE_ID_dtb 4 28 29 #define RT_CONSOLE_IS(con) (RT_CONSOLE_ID_ ## con == CONSOLE_RUNTIME) 30 31 /* Default counter frequency */ 32 #define ZYNQMP_DEFAULT_COUNTER_FREQ 0U 33 34 /* Firmware Image Package */ 35 #define ZYNQMP_PRIMARY_CPU 0 36 37 /* Memory location options for Shared data and TSP in ZYNQMP */ 38 #define ZYNQMP_IN_TRUSTED_SRAM 0 39 #define ZYNQMP_IN_TRUSTED_DRAM 1 40 41 /******************************************************************************* 42 * ZYNQMP memory map related constants 43 ******************************************************************************/ 44 /* Aggregate of all devices in the first GB */ 45 #define DEVICE0_BASE U(0xFF000000) 46 #define DEVICE0_SIZE U(0x00E00000) 47 #define DEVICE1_BASE U(0xF9000000) 48 #define DEVICE1_SIZE U(0x00800000) 49 50 /* For cpu reset APU space here too 0xFE5F1000 CRF_APB*/ 51 #define CRF_APB_BASE U(0xFD1A0000) 52 #define CRF_APB_SIZE U(0x00600000) 53 #define CRF_APB_CLK_BASE U(0xFD1A0020) 54 55 /* CRF registers and bitfields */ 56 #define CRF_APB_RST_FPD_APU (CRF_APB_BASE + 0X00000104) 57 58 #define CRF_APB_RST_FPD_APU_ACPU_RESET (U(1) << 0) 59 #define CRF_APB_RST_FPD_APU_ACPU_PWRON_RESET (U(1) << 10) 60 61 /* CRL registers and bitfields */ 62 #define CRL_APB_BASE U(0xFF5E0000) 63 #define CRL_APB_BOOT_MODE_USER (CRL_APB_BASE + 0x200) 64 #define CRL_APB_RESET_CTRL (CRL_APB_BASE + 0x218) 65 #define CRL_APB_RST_LPD_TOP (CRL_APB_BASE + 0x23C) 66 #define CRL_APB_BOOT_PIN_CTRL (CRL_APB_BASE + U(0x250)) 67 #define CRL_APB_CLK_BASE U(0xFF5E0020) 68 69 #define CRL_APB_RPU_AMBA_RESET (U(1) << 2) 70 #define CRL_APB_RPLL_CTRL_BYPASS (U(1) << 3) 71 72 #define CRL_APB_RESET_CTRL_SOFT_RESET (U(1) << 4) 73 74 #define CRL_APB_BOOT_MODE_MASK (U(0xf) << 0) 75 #define CRL_APB_BOOT_PIN_MASK (U(0xf0f) << 0) 76 #define CRL_APB_BOOT_DRIVE_PIN_1_SHIFT U(9) 77 #define CRL_APB_BOOT_ENABLE_PIN_1_SHIFT U(1) 78 #define CRL_APB_BOOT_ENABLE_PIN_1 (U(0x1) << \ 79 CRL_APB_BOOT_ENABLE_PIN_1_SHIFT) 80 #define CRL_APB_BOOT_DRIVE_PIN_1 (U(0x1) << \ 81 CRL_APB_BOOT_DRIVE_PIN_1_SHIFT) 82 #define ZYNQMP_BOOTMODE_JTAG U(0) 83 #define ZYNQMP_ULPI_RESET_VAL_HIGH (CRL_APB_BOOT_ENABLE_PIN_1 | \ 84 CRL_APB_BOOT_DRIVE_PIN_1) 85 #define ZYNQMP_ULPI_RESET_VAL_LOW CRL_APB_BOOT_ENABLE_PIN_1 86 87 /* system counter registers and bitfields */ 88 #define IOU_SCNTRS_BASE U(0xFF260000) 89 #define IOU_SCNTRS_BASEFREQ (IOU_SCNTRS_BASE + 0x20) 90 91 /* APU registers and bitfields */ 92 #define APU_BASE U(0xFD5C0000) 93 #define APU_CONFIG_0 (APU_BASE + 0x20) 94 #define APU_RVBAR_L_0 (APU_BASE + 0x40) 95 #define APU_RVBAR_H_0 (APU_BASE + 0x44) 96 #define APU_PWRCTL (APU_BASE + 0x90) 97 98 #define APU_CONFIG_0_VINITHI_SHIFT 8 99 #define APU_0_PWRCTL_CPUPWRDWNREQ_MASK 1 100 #define APU_1_PWRCTL_CPUPWRDWNREQ_MASK 2 101 #define APU_2_PWRCTL_CPUPWRDWNREQ_MASK 4 102 #define APU_3_PWRCTL_CPUPWRDWNREQ_MASK 8 103 104 /* PMU registers and bitfields */ 105 #define PMU_GLOBAL_BASE U(0xFFD80000) 106 #define PMU_GLOBAL_CNTRL (PMU_GLOBAL_BASE + 0) 107 #define PMU_GLOBAL_GEN_STORAGE6 (PMU_GLOBAL_BASE + 0x48) 108 #define PMU_GLOBAL_REQ_PWRUP_STATUS (PMU_GLOBAL_BASE + 0x110) 109 #define PMU_GLOBAL_REQ_PWRUP_EN (PMU_GLOBAL_BASE + 0x118) 110 #define PMU_GLOBAL_REQ_PWRUP_DIS (PMU_GLOBAL_BASE + 0x11c) 111 #define PMU_GLOBAL_REQ_PWRUP_TRIG (PMU_GLOBAL_BASE + 0x120) 112 113 #define PMU_GLOBAL_CNTRL_FW_IS_PRESENT (1 << 4) 114 115 /******************************************************************************* 116 * CCI-400 related constants 117 ******************************************************************************/ 118 #define PLAT_ARM_CCI_BASE U(0xFD6E0000) 119 #define PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX 3 120 #define PLAT_ARM_CCI_CLUSTER1_SL_IFACE_IX 4 121 122 /******************************************************************************* 123 * GIC-400 & interrupt handling related constants 124 ******************************************************************************/ 125 #define BASE_GICD_BASE U(0xF9010000) 126 #define BASE_GICC_BASE U(0xF9020000) 127 #define BASE_GICH_BASE U(0xF9040000) 128 #define BASE_GICV_BASE U(0xF9060000) 129 130 #if ZYNQMP_WDT_RESTART 131 #define IRQ_SEC_IPI_APU 67 132 #define IRQ_TTC3_1 77 133 #define TTC3_BASE_ADDR U(0xFF140000) 134 #define TTC3_INTR_REGISTER_1 (TTC3_BASE_ADDR + 0x54) 135 #define TTC3_INTR_ENABLE_1 (TTC3_BASE_ADDR + 0x60) 136 #endif 137 138 #define ARM_IRQ_SEC_PHY_TIMER 29 139 140 #define ARM_IRQ_SEC_SGI_0 8 141 #define ARM_IRQ_SEC_SGI_1 9 142 #define ARM_IRQ_SEC_SGI_2 10 143 #define ARM_IRQ_SEC_SGI_3 11 144 #define ARM_IRQ_SEC_SGI_4 12 145 #define ARM_IRQ_SEC_SGI_5 13 146 #define ARM_IRQ_SEC_SGI_6 14 147 #define ARM_IRQ_SEC_SGI_7 15 148 149 /* number of interrupt handlers. increase as required */ 150 #define MAX_INTR_EL3 2 151 152 /******************************************************************************* 153 * UART related constants 154 ******************************************************************************/ 155 #define ZYNQMP_UART0_BASE U(0xFF000000) 156 #define ZYNQMP_UART1_BASE U(0xFF010000) 157 158 /* Boot console */ 159 #if CONSOLE_IS(cadence) || CONSOLE_IS(dtb) 160 # define UART_BASE ZYNQMP_UART0_BASE 161 # define UART_TYPE CONSOLE_CDNS 162 #elif CONSOLE_IS(cadence1) 163 # define UART_BASE ZYNQMP_UART1_BASE 164 # define UART_TYPE CONSOLE_CDNS 165 #elif CONSOLE_IS(dcc) 166 # define UART_BASE 0x0 167 # define UART_TYPE CONSOLE_DCC 168 #elif CONSOLE_IS(none) 169 # define UART_TYPE CONSOLE_NONE 170 #else 171 # error "invalid ZYNQMP_CONSOLE" 172 #endif 173 174 /* Runtime console */ 175 #if defined(CONSOLE_RUNTIME) 176 #if RT_CONSOLE_IS(cadence) || RT_CONSOLE_IS(dtb) 177 # define RT_UART_BASE ZYNQMP_UART0_BASE 178 # define RT_UART_TYPE CONSOLE_CDNS 179 #elif RT_CONSOLE_IS(cadence1) 180 # define RT_UART_BASE ZYNQMP_UART1_BASE 181 # define RT_UART_TYPE CONSOLE_CDNS 182 #elif RT_CONSOLE_IS(dcc) 183 # define RT_UART_BASE 0x0 184 # define RT_UART_TYPE CONSOLE_DCC 185 #else 186 # error "invalid CONSOLE_RUNTIME" 187 #endif 188 #endif 189 190 /* Must be non zero */ 191 #define UART_BAUDRATE 115200 192 193 /* Silicon version detection */ 194 #define ZYNQMP_SILICON_VER_MASK 0xF000 195 #define ZYNQMP_SILICON_VER_SHIFT 12 196 #define ZYNQMP_CSU_VERSION_SILICON 0 197 #define ZYNQMP_CSU_VERSION_QEMU 3 198 199 #define ZYNQMP_RTL_VER_MASK 0xFF0U 200 #define ZYNQMP_RTL_VER_SHIFT 4 201 202 #define ZYNQMP_PS_VER_MASK 0xFU 203 #define ZYNQMP_PS_VER_SHIFT 0 204 205 #define ZYNQMP_CSU_BASEADDR U(0xFFCA0000) 206 #define ZYNQMP_CSU_IDCODE_OFFSET 0x40U 207 208 #define ZYNQMP_CSU_IDCODE_XILINX_ID_SHIFT 0U 209 #define ZYNQMP_CSU_IDCODE_XILINX_ID_MASK (0xFFFU << \ 210 ZYNQMP_CSU_IDCODE_XILINX_ID_SHIFT) 211 #define ZYNQMP_CSU_IDCODE_XILINX_ID 0x093 212 213 #define ZYNQMP_CSU_IDCODE_SVD_SHIFT 12U 214 #define ZYNQMP_CSU_IDCODE_SVD_MASK (0x7U << \ 215 ZYNQMP_CSU_IDCODE_SVD_SHIFT) 216 #define ZYNQMP_CSU_IDCODE_DEVICE_CODE_SHIFT 15U 217 #define ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK (0xFU << \ 218 ZYNQMP_CSU_IDCODE_DEVICE_CODE_SHIFT) 219 #define ZYNQMP_CSU_IDCODE_SUB_FAMILY_SHIFT 19U 220 #define ZYNQMP_CSU_IDCODE_SUB_FAMILY_MASK (0x3U << \ 221 ZYNQMP_CSU_IDCODE_SUB_FAMILY_SHIFT) 222 #define ZYNQMP_CSU_IDCODE_FAMILY_SHIFT 21U 223 #define ZYNQMP_CSU_IDCODE_FAMILY_MASK (0x7FU << \ 224 ZYNQMP_CSU_IDCODE_FAMILY_SHIFT) 225 #define ZYNQMP_CSU_IDCODE_FAMILY 0x23 226 227 #define ZYNQMP_CSU_IDCODE_REVISION_SHIFT 28U 228 #define ZYNQMP_CSU_IDCODE_REVISION_MASK (0xFU << \ 229 ZYNQMP_CSU_IDCODE_REVISION_SHIFT) 230 #define ZYNQMP_CSU_IDCODE_REVISION 0U 231 232 #define ZYNQMP_CSU_VERSION_OFFSET 0x44U 233 234 /* Efuse */ 235 #define EFUSE_BASEADDR U(0xFFCC0000) 236 #define EFUSE_IPDISABLE_OFFSET 0x1018 237 #define EFUSE_IPDISABLE_VERSION 0x1FFU 238 #define ZYNQMP_EFUSE_IPDISABLE_SHIFT 20 239 240 /* Access control register defines */ 241 #define ACTLR_EL3_L2ACTLR_BIT (1 << 6) 242 #define ACTLR_EL3_CPUACTLR_BIT (1 << 0) 243 244 #define FPD_SLCR_BASEADDR U(0xFD610000) 245 #define IOU_SLCR_BASEADDR U(0xFF180000) 246 247 #define ZYNQMP_RPU_GLBL_CNTL U(0xFF9A0000) 248 #define ZYNQMP_RPU0_CFG U(0xFF9A0100) 249 #define ZYNQMP_RPU1_CFG U(0xFF9A0200) 250 #define ZYNQMP_SLSPLIT_MASK U(0x08) 251 #define ZYNQMP_TCM_COMB_MASK U(0x40) 252 #define ZYNQMP_SLCLAMP_MASK U(0x10) 253 #define ZYNQMP_VINITHI_MASK U(0x04) 254 255 /* Tap delay bypass */ 256 #define IOU_TAPDLY_BYPASS U(0XFF180390) 257 #define TAP_DELAY_MASK U(0x7) 258 259 /* SD DLL reset */ 260 #define ZYNQMP_SD_DLL_CTRL U(0xFF180358) 261 #define ZYNQMP_SD0_DLL_RST_MASK U(0x00000004) 262 #define ZYNQMP_SD0_DLL_RST U(0x00000004) 263 #define ZYNQMP_SD1_DLL_RST_MASK U(0x00040000) 264 #define ZYNQMP_SD1_DLL_RST U(0x00040000) 265 266 /* SD tap delay */ 267 #define ZYNQMP_SD_DLL_CTRL U(0xFF180358) 268 #define ZYNQMP_SD_ITAP_DLY U(0xFF180314) 269 #define ZYNQMP_SD_OTAP_DLY U(0xFF180318) 270 #define ZYNQMP_SD_TAP_OFFSET U(16) 271 #define ZYNQMP_SD_ITAPCHGWIN_MASK U(0x200) 272 #define ZYNQMP_SD_ITAPCHGWIN U(0x200) 273 #define ZYNQMP_SD_ITAPDLYENA_MASK U(0x100) 274 #define ZYNQMP_SD_ITAPDLYENA U(0x100) 275 #define ZYNQMP_SD_ITAPDLYSEL_MASK U(0xFF) 276 #define ZYNQMP_SD_OTAPDLYSEL_MASK U(0x3F) 277 #define ZYNQMP_SD_OTAPDLYENA_MASK U(0x40) 278 #define ZYNQMP_SD_OTAPDLYENA U(0x40) 279 280 /* Clock control registers */ 281 /* Full power domain clocks */ 282 #define CRF_APB_APLL_CTRL (CRF_APB_CLK_BASE + 0x00) 283 #define CRF_APB_DPLL_CTRL (CRF_APB_CLK_BASE + 0x0c) 284 #define CRF_APB_VPLL_CTRL (CRF_APB_CLK_BASE + 0x18) 285 #define CRF_APB_PLL_STATUS (CRF_APB_CLK_BASE + 0x24) 286 #define CRF_APB_APLL_TO_LPD_CTRL (CRF_APB_CLK_BASE + 0x28) 287 #define CRF_APB_DPLL_TO_LPD_CTRL (CRF_APB_CLK_BASE + 0x2c) 288 #define CRF_APB_VPLL_TO_LPD_CTRL (CRF_APB_CLK_BASE + 0x30) 289 /* Peripheral clocks */ 290 #define CRF_APB_ACPU_CTRL (CRF_APB_CLK_BASE + 0x40) 291 #define CRF_APB_DBG_TRACE_CTRL (CRF_APB_CLK_BASE + 0x44) 292 #define CRF_APB_DBG_FPD_CTRL (CRF_APB_CLK_BASE + 0x48) 293 #define CRF_APB_DP_VIDEO_REF_CTRL (CRF_APB_CLK_BASE + 0x50) 294 #define CRF_APB_DP_AUDIO_REF_CTRL (CRF_APB_CLK_BASE + 0x54) 295 #define CRF_APB_DP_STC_REF_CTRL (CRF_APB_CLK_BASE + 0x5c) 296 #define CRF_APB_DDR_CTRL (CRF_APB_CLK_BASE + 0x60) 297 #define CRF_APB_GPU_REF_CTRL (CRF_APB_CLK_BASE + 0x64) 298 #define CRF_APB_SATA_REF_CTRL (CRF_APB_CLK_BASE + 0x80) 299 #define CRF_APB_PCIE_REF_CTRL (CRF_APB_CLK_BASE + 0x94) 300 #define CRF_APB_GDMA_REF_CTRL (CRF_APB_CLK_BASE + 0x98) 301 #define CRF_APB_DPDMA_REF_CTRL (CRF_APB_CLK_BASE + 0x9c) 302 #define CRF_APB_TOPSW_MAIN_CTRL (CRF_APB_CLK_BASE + 0xa0) 303 #define CRF_APB_TOPSW_LSBUS_CTRL (CRF_APB_CLK_BASE + 0xa4) 304 #define CRF_APB_GTGREF0_REF_CTRL (CRF_APB_CLK_BASE + 0xa8) 305 #define CRF_APB_DBG_TSTMP_CTRL (CRF_APB_CLK_BASE + 0xd8) 306 307 /* Low power domain clocks */ 308 #define CRL_APB_IOPLL_CTRL (CRL_APB_CLK_BASE + 0x00) 309 #define CRL_APB_RPLL_CTRL (CRL_APB_CLK_BASE + 0x10) 310 #define CRL_APB_PLL_STATUS (CRL_APB_CLK_BASE + 0x20) 311 #define CRL_APB_IOPLL_TO_FPD_CTRL (CRL_APB_CLK_BASE + 0x24) 312 #define CRL_APB_RPLL_TO_FPD_CTRL (CRL_APB_CLK_BASE + 0x28) 313 /* Peripheral clocks */ 314 #define CRL_APB_USB3_DUAL_REF_CTRL (CRL_APB_CLK_BASE + 0x2c) 315 #define CRL_APB_GEM0_REF_CTRL (CRL_APB_CLK_BASE + 0x30) 316 #define CRL_APB_GEM1_REF_CTRL (CRL_APB_CLK_BASE + 0x34) 317 #define CRL_APB_GEM2_REF_CTRL (CRL_APB_CLK_BASE + 0x38) 318 #define CRL_APB_GEM3_REF_CTRL (CRL_APB_CLK_BASE + 0x3c) 319 #define CRL_APB_USB0_BUS_REF_CTRL (CRL_APB_CLK_BASE + 0x40) 320 #define CRL_APB_USB1_BUS_REF_CTRL (CRL_APB_CLK_BASE + 0x44) 321 #define CRL_APB_QSPI_REF_CTRL (CRL_APB_CLK_BASE + 0x48) 322 #define CRL_APB_SDIO0_REF_CTRL (CRL_APB_CLK_BASE + 0x4c) 323 #define CRL_APB_SDIO1_REF_CTRL (CRL_APB_CLK_BASE + 0x50) 324 #define CRL_APB_UART0_REF_CTRL (CRL_APB_CLK_BASE + 0x54) 325 #define CRL_APB_UART1_REF_CTRL (CRL_APB_CLK_BASE + 0x58) 326 #define CRL_APB_SPI0_REF_CTRL (CRL_APB_CLK_BASE + 0x5c) 327 #define CRL_APB_SPI1_REF_CTRL (CRL_APB_CLK_BASE + 0x60) 328 #define CRL_APB_CAN0_REF_CTRL (CRL_APB_CLK_BASE + 0x64) 329 #define CRL_APB_CAN1_REF_CTRL (CRL_APB_CLK_BASE + 0x68) 330 #define CRL_APB_CPU_R5_CTRL (CRL_APB_CLK_BASE + 0x70) 331 #define CRL_APB_IOU_SWITCH_CTRL (CRL_APB_CLK_BASE + 0x7c) 332 #define CRL_APB_CSU_PLL_CTRL (CRL_APB_CLK_BASE + 0x80) 333 #define CRL_APB_PCAP_CTRL (CRL_APB_CLK_BASE + 0x84) 334 #define CRL_APB_LPD_SWITCH_CTRL (CRL_APB_CLK_BASE + 0x88) 335 #define CRL_APB_LPD_LSBUS_CTRL (CRL_APB_CLK_BASE + 0x8c) 336 #define CRL_APB_DBG_LPD_CTRL (CRL_APB_CLK_BASE + 0x90) 337 #define CRL_APB_NAND_REF_CTRL (CRL_APB_CLK_BASE + 0x94) 338 #define CRL_APB_ADMA_REF_CTRL (CRL_APB_CLK_BASE + 0x98) 339 #define CRL_APB_PL0_REF_CTRL (CRL_APB_CLK_BASE + 0xa0) 340 #define CRL_APB_PL1_REF_CTRL (CRL_APB_CLK_BASE + 0xa4) 341 #define CRL_APB_PL2_REF_CTRL (CRL_APB_CLK_BASE + 0xa8) 342 #define CRL_APB_PL3_REF_CTRL (CRL_APB_CLK_BASE + 0xac) 343 #define CRL_APB_PL0_THR_CNT (CRL_APB_CLK_BASE + 0xb4) 344 #define CRL_APB_PL1_THR_CNT (CRL_APB_CLK_BASE + 0xbc) 345 #define CRL_APB_PL2_THR_CNT (CRL_APB_CLK_BASE + 0xc4) 346 #define CRL_APB_PL3_THR_CNT (CRL_APB_CLK_BASE + 0xdc) 347 #define CRL_APB_GEM_TSU_REF_CTRL (CRL_APB_CLK_BASE + 0xe0) 348 #define CRL_APB_DLL_REF_CTRL (CRL_APB_CLK_BASE + 0xe4) 349 #define CRL_APB_AMS_REF_CTRL (CRL_APB_CLK_BASE + 0xe8) 350 #define CRL_APB_I2C0_REF_CTRL (CRL_APB_CLK_BASE + 0x100) 351 #define CRL_APB_I2C1_REF_CTRL (CRL_APB_CLK_BASE + 0x104) 352 #define CRL_APB_TIMESTAMP_REF_CTRL (CRL_APB_CLK_BASE + 0x108) 353 #define IOU_SLCR_GEM_CLK_CTRL (IOU_SLCR_BASEADDR + 0x308) 354 #define IOU_SLCR_CAN_MIO_CTRL (IOU_SLCR_BASEADDR + 0x304) 355 #define FPD_SLCR_WDT_CLK_SEL (FPD_SLCR_BASEADDR + 0x100) 356 #define IOU_SLCR_WDT_CLK_SEL (IOU_SLCR_BASEADDR + 0x300) 357 358 /* Global general storage register base address */ 359 #define GGS_BASEADDR (0xFFD80030U) 360 #define GGS_NUM_REGS U(4) 361 362 /* Persistent global general storage register base address */ 363 #define PGGS_BASEADDR (0xFFD80050U) 364 #define PGGS_NUM_REGS U(4) 365 366 /* PMU GGS4 register 4 is used for warm restart boot health status */ 367 #define PMU_GLOBAL_GEN_STORAGE4 (GGS_BASEADDR + 0x10) 368 /* Warm restart boot health status mask */ 369 #define PM_BOOT_HEALTH_STATUS_MASK U(0x01) 370 /* WDT restart scope shift and mask */ 371 #define RESTART_SCOPE_SHIFT (3) 372 #define RESTART_SCOPE_MASK (0x3U << RESTART_SCOPE_SHIFT) 373 374 /* AFI registers */ 375 #define AFIFM6_WRCTRL U(13) 376 #define FABRIC_WIDTH U(3) 377 378 /* CSUDMA Module Base Address*/ 379 #define CSUDMA_BASE U(0xFFC80000) 380 381 /* RSA-CORE Module Base Address*/ 382 #define RSA_CORE_BASE U(0xFFCE0000) 383 384 #endif /* ZYNQMP_DEF_H */ 385