xref: /rk3399_ARM-atf/plat/st/stm32mp2/bl2_plat_setup.c (revision 7623e085cb5396054b72f1ea3f02e8c7a34568b5) 
1 /*
2  * Copyright (c) 2023-2024, STMicroelectronics - All Rights Reserved
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #include <assert.h>
8 #include <cdefs.h>
9 #include <errno.h>
10 #include <stdint.h>
11 
12 #include <common/debug.h>
13 #include <common/desc_image_load.h>
14 #include <drivers/clk.h>
15 #include <drivers/mmc.h>
16 #include <drivers/st/regulator_fixed.h>
17 #include <drivers/st/stm32mp2_ddr_helpers.h>
18 #include <drivers/st/stm32mp2_ram.h>
19 #include <drivers/st/stm32mp_pmic2.h>
20 #include <drivers/st/stm32mp_risab_regs.h>
21 #include <lib/fconf/fconf.h>
22 #include <lib/fconf/fconf_dyn_cfg_getter.h>
23 #include <lib/mmio.h>
24 #include <lib/optee_utils.h>
25 #include <lib/xlat_tables/xlat_tables_v2.h>
26 #include <plat/common/platform.h>
27 
28 #include <platform_def.h>
29 #include <stm32mp_common.h>
30 #include <stm32mp_dt.h>
31 
32 #define BOOT_CTX_ADDR	0x0e000020UL
33 
34 static void print_reset_reason(void)
35 {
36 	uint32_t rstsr = mmio_read_32(stm32mp_rcc_base() + RCC_C1BOOTRSTSCLRR);
37 
38 	if (rstsr == 0U) {
39 		WARN("Reset reason unknown\n");
40 		return;
41 	}
42 
43 	INFO("Reset reason (0x%x):\n", rstsr);
44 
45 	if ((rstsr & RCC_C1BOOTRSTSCLRR_PADRSTF) == 0U) {
46 		if ((rstsr & RCC_C1BOOTRSTSCLRR_STBYC1RSTF) != 0U) {
47 			INFO("System exits from Standby for CA35\n");
48 			return;
49 		}
50 
51 		if ((rstsr & RCC_C1BOOTRSTSCLRR_D1STBYRSTF) != 0U) {
52 			INFO("D1 domain exits from DStandby\n");
53 			return;
54 		}
55 	}
56 
57 	if ((rstsr & RCC_C1BOOTRSTSCLRR_PORRSTF) != 0U) {
58 		INFO("  Power-on Reset (rst_por)\n");
59 		return;
60 	}
61 
62 	if ((rstsr & RCC_C1BOOTRSTSCLRR_BORRSTF) != 0U) {
63 		INFO("  Brownout Reset (rst_bor)\n");
64 		return;
65 	}
66 
67 	if ((rstsr & RCC_C1BOOTRSTSSETR_SYSC2RSTF) != 0U) {
68 		INFO("  System reset (SYSRST) by M33\n");
69 		return;
70 	}
71 
72 	if ((rstsr & RCC_C1BOOTRSTSSETR_SYSC1RSTF) != 0U) {
73 		INFO("  System reset (SYSRST) by A35\n");
74 		return;
75 	}
76 
77 	if ((rstsr & RCC_C1BOOTRSTSCLRR_HCSSRSTF) != 0U) {
78 		INFO("  Clock failure on HSE\n");
79 		return;
80 	}
81 
82 	if ((rstsr & RCC_C1BOOTRSTSCLRR_IWDG1SYSRSTF) != 0U) {
83 		INFO("  IWDG1 system reset (rst_iwdg1)\n");
84 		return;
85 	}
86 
87 	if ((rstsr & RCC_C1BOOTRSTSCLRR_IWDG2SYSRSTF) != 0U) {
88 		INFO("  IWDG2 system reset (rst_iwdg2)\n");
89 		return;
90 	}
91 
92 	if ((rstsr & RCC_C1BOOTRSTSCLRR_IWDG3SYSRSTF) != 0U) {
93 		INFO("  IWDG3 system reset (rst_iwdg3)\n");
94 		return;
95 	}
96 
97 	if ((rstsr & RCC_C1BOOTRSTSCLRR_IWDG4SYSRSTF) != 0U) {
98 		INFO("  IWDG4 system reset (rst_iwdg4)\n");
99 		return;
100 	}
101 
102 	if ((rstsr & RCC_C1BOOTRSTSCLRR_IWDG5SYSRSTF) != 0U) {
103 		INFO("  IWDG5 system reset (rst_iwdg5)\n");
104 		return;
105 	}
106 
107 	if ((rstsr & RCC_C1BOOTRSTSCLRR_C1P1RSTF) != 0U) {
108 		INFO("  A35 processor core 1 reset\n");
109 		return;
110 	}
111 
112 	if ((rstsr & RCC_C1BOOTRSTSCLRR_PADRSTF) != 0U) {
113 		INFO("  Pad Reset from NRST\n");
114 		return;
115 	}
116 
117 	if ((rstsr & RCC_C1BOOTRSTSCLRR_VCORERSTF) != 0U) {
118 		INFO("  Reset due to a failure of VDD_CORE\n");
119 		return;
120 	}
121 
122 	if ((rstsr & RCC_C1BOOTRSTSCLRR_C1RSTF) != 0U) {
123 		INFO("  A35 processor reset\n");
124 		return;
125 	}
126 
127 	ERROR("  Unidentified reset reason\n");
128 }
129 
130 void bl2_el3_early_platform_setup(u_register_t arg0 __unused,
131 				  u_register_t arg1 __unused,
132 				  u_register_t arg2 __unused,
133 				  u_register_t arg3 __unused)
134 {
135 	stm32mp_save_boot_ctx_address(BOOT_CTX_ADDR);
136 }
137 
138 void bl2_platform_setup(void)
139 {
140 	int ret;
141 
142 	ret = stm32mp2_ddr_probe();
143 	if (ret != 0) {
144 		ERROR("DDR probe: error %d\n", ret);
145 		panic();
146 	}
147 
148 	/* Map DDR for binary load, now with cacheable attribute */
149 	ret = mmap_add_dynamic_region(STM32MP_DDR_BASE, STM32MP_DDR_BASE,
150 				      STM32MP_DDR_MAX_SIZE, MT_MEMORY | MT_RW | MT_SECURE);
151 	if (ret < 0) {
152 		ERROR("DDR mapping: error %d\n", ret);
153 		panic();
154 	}
155 }
156 
157 static void reset_backup_domain(void)
158 {
159 	uintptr_t pwr_base = stm32mp_pwr_base();
160 	uintptr_t rcc_base = stm32mp_rcc_base();
161 
162 	/*
163 	 * Disable the backup domain write protection.
164 	 * The protection is enable at each reset by hardware
165 	 * and must be disabled by software.
166 	 */
167 	mmio_setbits_32(pwr_base + PWR_BDCR1, PWR_BDCR1_DBD3P);
168 
169 	while ((mmio_read_32(pwr_base + PWR_BDCR1) & PWR_BDCR1_DBD3P) == 0U) {
170 		;
171 	}
172 
173 	/* Reset backup domain on cold boot cases */
174 	if ((mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_RTCCKEN) == 0U) {
175 		mmio_setbits_32(rcc_base + RCC_BDCR, RCC_BDCR_VSWRST);
176 
177 		while ((mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_VSWRST) == 0U) {
178 			;
179 		}
180 
181 		mmio_clrbits_32(rcc_base + RCC_BDCR, RCC_BDCR_VSWRST);
182 	}
183 }
184 
185 void bl2_el3_plat_arch_setup(void)
186 {
187 	const char *board_model;
188 	boot_api_context_t *boot_context =
189 		(boot_api_context_t *)stm32mp_get_boot_ctx_address();
190 
191 	if (stm32_otp_probe() != 0U) {
192 		EARLY_ERROR("OTP probe failed\n");
193 		panic();
194 	}
195 
196 	mmap_add_region(BL_CODE_BASE, BL_CODE_BASE,
197 			BL_CODE_END - BL_CODE_BASE,
198 			MT_CODE | MT_SECURE);
199 
200 	configure_mmu();
201 
202 	if (dt_open_and_check(STM32MP_DTB_BASE) < 0) {
203 		panic();
204 	}
205 
206 	reset_backup_domain();
207 
208 	/*
209 	 * Initialize DDR sub-system clock. This needs to be done before enabling DDR PLL (PLL2),
210 	 * and so before stm32mp2_clk_init().
211 	 */
212 	ddr_sub_system_clk_init();
213 
214 	if (stm32mp2_clk_init() < 0) {
215 		panic();
216 	}
217 
218 #if STM32MP_DDR_FIP_IO_STORAGE
219 	/*
220 	 * RISAB3 setup (dedicated for SRAM1)
221 	 *
222 	 * Allow secure read/writes data accesses to non-secure
223 	 * blocks or pages, all RISAB registers are writable.
224 	 * DDR firmwares are saved there before being loaded in DDRPHY memory.
225 	 */
226 	mmio_write_32(RISAB3_BASE + RISAB_CR, RISAB_CR_SRWIAD);
227 #endif
228 
229 	stm32_save_boot_info(boot_context);
230 
231 	if (stm32mp_uart_console_setup() != 0) {
232 		goto skip_console_init;
233 	}
234 
235 	stm32mp_print_cpuinfo();
236 
237 	board_model = dt_get_board_model();
238 	if (board_model != NULL) {
239 		NOTICE("Model: %s\n", board_model);
240 	}
241 
242 	stm32mp_print_boardinfo();
243 
244 	print_reset_reason();
245 
246 skip_console_init:
247 	if (fixed_regulator_register() != 0) {
248 		panic();
249 	}
250 
251 	if (dt_pmic_status() > 0) {
252 		initialize_pmic();
253 	}
254 
255 	fconf_populate("TB_FW", STM32MP_DTB_BASE);
256 
257 	/*
258 	 * RISAB5 setup (dedicated for RETRAM)
259 	 *
260 	 * Allow secure read/writes data accesses to non-secure
261 	 * blocks or pages, all RISAB registers are writable.
262 	 * DDR retention registers are saved there and restored
263 	 * when exiting standby low power state.
264 	 */
265 	mmio_write_32(RISAB5_BASE + RISAB_CR, RISAB_CR_SRWIAD);
266 
267 	stm32mp_io_setup();
268 }
269 
270 /*******************************************************************************
271  * This function can be used by the platforms to update/use image
272  * information for given `image_id`.
273  ******************************************************************************/
274 int bl2_plat_handle_post_image_load(unsigned int image_id)
275 {
276 	int err = 0;
277 	bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id);
278 	bl_mem_params_node_t *pager_mem_params;
279 	const struct dyn_cfg_dtb_info_t *config_info;
280 	unsigned int i;
281 	const unsigned int image_ids[] = {
282 		BL31_IMAGE_ID,
283 		SOC_FW_CONFIG_ID,
284 		BL32_IMAGE_ID,
285 		BL33_IMAGE_ID,
286 		HW_CONFIG_ID,
287 	};
288 
289 	assert(bl_mem_params != NULL);
290 
291 #if STM32MP_SDMMC || STM32MP_EMMC
292 	/*
293 	 * Invalidate remaining data read from MMC but not flushed by load_image_flush().
294 	 * We take the worst case which is 2 MMC blocks.
295 	 */
296 	if ((image_id != FW_CONFIG_ID) &&
297 	    ((bl_mem_params->image_info.h.attr & IMAGE_ATTRIB_SKIP_LOADING) == 0U)) {
298 		inv_dcache_range(bl_mem_params->image_info.image_base +
299 				 bl_mem_params->image_info.image_size,
300 				 2U * MMC_BLOCK_SIZE);
301 	}
302 #endif /* STM32MP_SDMMC || STM32MP_EMMC */
303 
304 	switch (image_id) {
305 	case FW_CONFIG_ID:
306 		/* Set global DTB info for fixed fw_config information */
307 		set_config_info(STM32MP_FW_CONFIG_BASE, ~0UL, STM32MP_FW_CONFIG_MAX_SIZE,
308 				FW_CONFIG_ID);
309 		fconf_populate("FW_CONFIG", STM32MP_FW_CONFIG_BASE);
310 
311 		/* Iterate through all the fw config IDs */
312 		for (i = 0U; i < ARRAY_SIZE(image_ids); i++) {
313 			bl_mem_params = get_bl_mem_params_node(image_ids[i]);
314 			assert(bl_mem_params != NULL);
315 
316 			config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, image_ids[i]);
317 			if (config_info == NULL) {
318 				continue;
319 			}
320 
321 			bl_mem_params->image_info.image_base = config_info->config_addr;
322 			bl_mem_params->image_info.image_max_size = config_info->config_max_size;
323 
324 			bl_mem_params->image_info.h.attr &= ~IMAGE_ATTRIB_SKIP_LOADING;
325 
326 			switch (image_ids[i]) {
327 			case BL31_IMAGE_ID:
328 				bl_mem_params->ep_info.pc = config_info->config_addr;
329 				break;
330 
331 			case BL32_IMAGE_ID:
332 				bl_mem_params->ep_info.pc = config_info->config_addr;
333 
334 				/* In case of OPTEE, initialize address space with tos_fw addr */
335 				pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID);
336 				if (pager_mem_params != NULL) {
337 					pager_mem_params->image_info.image_base =
338 						config_info->config_addr;
339 					pager_mem_params->image_info.image_max_size =
340 						config_info->config_max_size;
341 				}
342 				break;
343 
344 			case BL33_IMAGE_ID:
345 				bl_mem_params->ep_info.pc = config_info->config_addr;
346 				break;
347 
348 			case HW_CONFIG_ID:
349 			case SOC_FW_CONFIG_ID:
350 				break;
351 
352 			default:
353 				return -EINVAL;
354 			}
355 		}
356 
357 		/*
358 		 * After this step, the BL2 device tree area will be overwritten
359 		 * with BL31 binary, no other data should be read from BL2 DT.
360 		 */
361 
362 		break;
363 
364 	case BL32_IMAGE_ID:
365 		if ((bl_mem_params->image_info.image_base != 0UL) &&
366 		    (optee_header_is_valid(bl_mem_params->image_info.image_base))) {
367 			/* BL32 is OP-TEE header */
368 			bl_mem_params->ep_info.pc = bl_mem_params->image_info.image_base;
369 			pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID);
370 			assert(pager_mem_params != NULL);
371 
372 			err = parse_optee_header(&bl_mem_params->ep_info,
373 						 &pager_mem_params->image_info,
374 						 NULL);
375 			if (err != 0) {
376 				ERROR("OPTEE header parse error.\n");
377 				panic();
378 			}
379 
380 			/* Set optee boot info from parsed header data */
381 			bl_mem_params->ep_info.args.arg0 = 0U; /* Unused */
382 			bl_mem_params->ep_info.args.arg1 = 0U; /* Unused */
383 			bl_mem_params->ep_info.args.arg2 = 0U; /* No DT supported */
384 		}
385 		break;
386 
387 	case BL33_IMAGE_ID:
388 	default:
389 		/* Do nothing in default case */
390 		break;
391 	}
392 
393 	return err;
394 }
395