1 /* 2 * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <arch.h> 10 #include <common/debug.h> 11 #include <common/interrupt_props.h> 12 #include <drivers/arm/gic_common.h> 13 #include <drivers/arm/gicv2.h> 14 15 #include "../common/gic_common_private.h" 16 #include "gicv2_private.h" 17 18 /* 19 * Accessor to read the GIC Distributor ITARGETSR corresponding to the 20 * interrupt `id`, 4 interrupt IDs at a time. 21 */ 22 unsigned int gicd_read_itargetsr(uintptr_t base, unsigned int id) 23 { 24 unsigned n = id >> ITARGETSR_SHIFT; 25 return mmio_read_32(base + GICD_ITARGETSR + (n << 2)); 26 } 27 28 /* 29 * Accessor to read the GIC Distributor CPENDSGIR corresponding to the 30 * interrupt `id`, 4 interrupt IDs at a time. 31 */ 32 unsigned int gicd_read_cpendsgir(uintptr_t base, unsigned int id) 33 { 34 unsigned n = id >> CPENDSGIR_SHIFT; 35 return mmio_read_32(base + GICD_CPENDSGIR + (n << 2)); 36 } 37 38 /* 39 * Accessor to read the GIC Distributor SPENDSGIR corresponding to the 40 * interrupt `id`, 4 interrupt IDs at a time. 41 */ 42 unsigned int gicd_read_spendsgir(uintptr_t base, unsigned int id) 43 { 44 unsigned n = id >> SPENDSGIR_SHIFT; 45 return mmio_read_32(base + GICD_SPENDSGIR + (n << 2)); 46 } 47 48 /* 49 * Accessor to write the GIC Distributor ITARGETSR corresponding to the 50 * interrupt `id`, 4 interrupt IDs at a time. 51 */ 52 void gicd_write_itargetsr(uintptr_t base, unsigned int id, unsigned int val) 53 { 54 unsigned n = id >> ITARGETSR_SHIFT; 55 mmio_write_32(base + GICD_ITARGETSR + (n << 2), val); 56 } 57 58 /* 59 * Accessor to write the GIC Distributor CPENDSGIR corresponding to the 60 * interrupt `id`, 4 interrupt IDs at a time. 61 */ 62 void gicd_write_cpendsgir(uintptr_t base, unsigned int id, unsigned int val) 63 { 64 unsigned n = id >> CPENDSGIR_SHIFT; 65 mmio_write_32(base + GICD_CPENDSGIR + (n << 2), val); 66 } 67 68 /* 69 * Accessor to write the GIC Distributor SPENDSGIR corresponding to the 70 * interrupt `id`, 4 interrupt IDs at a time. 71 */ 72 void gicd_write_spendsgir(uintptr_t base, unsigned int id, unsigned int val) 73 { 74 unsigned n = id >> SPENDSGIR_SHIFT; 75 mmio_write_32(base + GICD_SPENDSGIR + (n << 2), val); 76 } 77 78 /******************************************************************************* 79 * Get the current CPU bit mask from GICD_ITARGETSR0 80 ******************************************************************************/ 81 unsigned int gicv2_get_cpuif_id(uintptr_t base) 82 { 83 unsigned int val; 84 85 val = gicd_read_itargetsr(base, 0); 86 return val & GIC_TARGET_CPU_MASK; 87 } 88 89 /******************************************************************************* 90 * Helper function to configure the default attributes of SPIs. 91 ******************************************************************************/ 92 void gicv2_spis_configure_defaults(uintptr_t gicd_base) 93 { 94 unsigned int index, num_ints; 95 96 num_ints = gicd_read_typer(gicd_base); 97 num_ints &= TYPER_IT_LINES_NO_MASK; 98 num_ints = (num_ints + 1U) << 5; 99 100 /* 101 * Treat all SPIs as G1NS by default. The number of interrupts is 102 * calculated as 32 * (IT_LINES + 1). We do 32 at a time. 103 */ 104 for (index = MIN_SPI_ID; index < num_ints; index += 32U) { 105 gicd_write_igroupr(gicd_base, index, ~0U); 106 } 107 /* Setup the default SPI priorities doing four at a time */ 108 for (index = MIN_SPI_ID; index < num_ints; index += 4U) { 109 gicd_write_ipriorityr(gicd_base, 110 index, 111 GICD_IPRIORITYR_DEF_VAL); 112 } 113 /* Treat all SPIs as level triggered by default, 16 at a time */ 114 for (index = MIN_SPI_ID; index < num_ints; index += 16U) { 115 gicd_write_icfgr(gicd_base, index, 0U); 116 } 117 } 118 119 /******************************************************************************* 120 * Helper function to configure properties of secure G0 SPIs. 121 ******************************************************************************/ 122 void gicv2_secure_spis_configure_props(uintptr_t gicd_base, 123 const interrupt_prop_t *interrupt_props, 124 unsigned int interrupt_props_num) 125 { 126 unsigned int i; 127 const interrupt_prop_t *prop_desc; 128 129 /* Make sure there's a valid property array */ 130 if (interrupt_props_num != 0U) { 131 assert(interrupt_props != NULL); 132 } 133 for (i = 0; i < interrupt_props_num; i++) { 134 prop_desc = &interrupt_props[i]; 135 136 if (prop_desc->intr_num < MIN_SPI_ID) { 137 continue; 138 } 139 /* Configure this interrupt as a secure interrupt */ 140 assert(prop_desc->intr_grp == GICV2_INTR_GROUP0); 141 gicd_clr_igroupr(gicd_base, prop_desc->intr_num); 142 143 /* Set the priority of this interrupt */ 144 gicd_set_ipriorityr(gicd_base, prop_desc->intr_num, 145 prop_desc->intr_pri); 146 147 /* Target the secure interrupts to primary CPU */ 148 gicd_set_itargetsr(gicd_base, prop_desc->intr_num, 149 gicv2_get_cpuif_id(gicd_base)); 150 151 /* Set interrupt configuration */ 152 gicd_set_icfgr(gicd_base, prop_desc->intr_num, 153 prop_desc->intr_cfg); 154 155 /* Enable this interrupt */ 156 gicd_set_isenabler(gicd_base, prop_desc->intr_num); 157 } 158 } 159 160 /******************************************************************************* 161 * Helper function to configure properties of secure G0 SGIs and PPIs. 162 ******************************************************************************/ 163 void gicv2_secure_ppi_sgi_setup_props(uintptr_t gicd_base, 164 const interrupt_prop_t *interrupt_props, 165 unsigned int interrupt_props_num) 166 { 167 unsigned int i; 168 uint32_t sec_ppi_sgi_mask = 0; 169 const interrupt_prop_t *prop_desc; 170 171 /* Make sure there's a valid property array */ 172 if (interrupt_props_num != 0U) { 173 assert(interrupt_props != NULL); 174 } 175 /* 176 * Disable all SGIs (imp. def.)/PPIs before configuring them. This is a 177 * more scalable approach as it avoids clearing the enable bits in the 178 * GICD_CTLR. 179 */ 180 gicd_write_icenabler(gicd_base, 0U, ~0U); 181 182 /* Setup the default PPI/SGI priorities doing four at a time */ 183 for (i = 0U; i < MIN_SPI_ID; i += 4U) { 184 gicd_write_ipriorityr(gicd_base, i, GICD_IPRIORITYR_DEF_VAL); 185 } 186 for (i = 0U; i < interrupt_props_num; i++) { 187 prop_desc = &interrupt_props[i]; 188 189 if (prop_desc->intr_num >= MIN_SPI_ID) { 190 continue; 191 } 192 /* Configure this interrupt as a secure interrupt */ 193 assert(prop_desc->intr_grp == GICV2_INTR_GROUP0); 194 195 /* 196 * Set interrupt configuration for PPIs. Configuration for SGIs 197 * are ignored. 198 */ 199 if ((prop_desc->intr_num >= MIN_PPI_ID) && 200 (prop_desc->intr_num < MIN_SPI_ID)) { 201 gicd_set_icfgr(gicd_base, prop_desc->intr_num, 202 prop_desc->intr_cfg); 203 } 204 205 /* We have an SGI or a PPI. They are Group0 at reset */ 206 sec_ppi_sgi_mask |= (1u << prop_desc->intr_num); 207 208 /* Set the priority of this interrupt */ 209 gicd_set_ipriorityr(gicd_base, prop_desc->intr_num, 210 prop_desc->intr_pri); 211 } 212 213 /* 214 * Invert the bitmask to create a mask for non-secure PPIs and SGIs. 215 * Program the GICD_IGROUPR0 with this bit mask. 216 */ 217 gicd_write_igroupr(gicd_base, 0, ~sec_ppi_sgi_mask); 218 219 /* Enable the Group 0 SGIs and PPIs */ 220 gicd_write_isenabler(gicd_base, 0, sec_ppi_sgi_mask); 221 } 222