1/* 2 * Copyright (c) 2019-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_a78.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13#include "wa_cve_2022_23960_bhb_vector.S" 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "cortex_a78 must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20.globl cortex_a78_reset_func 21.globl cortex_a78_core_pwr_dwn 22 23#if WORKAROUND_CVE_2022_23960 24 wa_cve_2022_23960_bhb_vector_table CORTEX_A78_BHB_LOOP_COUNT, cortex_a78 25#endif /* WORKAROUND_CVE_2022_23960 */ 26 27cpu_reset_prologue cortex_a78 28 29/* Disable hardware page aggregation.Enables mitigation for `CVE-2024-5660` */ 30workaround_reset_start cortex_a78, CVE(2024, 5660), WORKAROUND_CVE_2024_5660 31 sysreg_bit_set CORTEX_A78_CPUECTLR_EL1, BIT(46) 32workaround_reset_end cortex_a78, CVE(2024, 5660) 33 34check_erratum_ls cortex_a78, CVE(2024, 5660), CPU_REV(1, 2) 35 36workaround_reset_start cortex_a78, ERRATUM(1688305), ERRATA_A78_1688305 37 sysreg_bit_set CORTEX_A78_ACTLR2_EL1, CORTEX_A78_ACTLR2_EL1_BIT_1 38workaround_reset_end cortex_a78, ERRATUM(1688305) 39 40check_erratum_ls cortex_a78, ERRATUM(1688305), CPU_REV(1, 0) 41 42workaround_reset_start cortex_a78, ERRATUM(1821534), ERRATA_A78_1821534 43 sysreg_bit_set CORTEX_A78_ACTLR2_EL1, CORTEX_A78_ACTLR2_EL1_BIT_2 44workaround_reset_end cortex_a78, ERRATUM(1821534) 45 46check_erratum_ls cortex_a78, ERRATUM(1821534), CPU_REV(1, 0) 47 48workaround_reset_start cortex_a78, ERRATUM(1941498), ERRATA_A78_1941498 49 sysreg_bit_set CORTEX_A78_CPUECTLR_EL1, CORTEX_A78_CPUECTLR_EL1_BIT_8 50workaround_reset_end cortex_a78, ERRATUM(1941498) 51 52check_erratum_ls cortex_a78, ERRATUM(1941498), CPU_REV(1, 1) 53 54workaround_reset_start cortex_a78, ERRATUM(1951500), ERRATA_A78_1951500 55 msr S3_6_c15_c8_0, xzr 56 ldr x0, =0x10E3900002 57 msr S3_6_c15_c8_2, x0 58 ldr x0, =0x10FFF00083 59 msr S3_6_c15_c8_3, x0 60 ldr x0, =0x2001003FF 61 msr S3_6_c15_c8_1, x0 62 63 mov x0, #1 64 msr S3_6_c15_c8_0, x0 65 ldr x0, =0x10E3800082 66 msr S3_6_c15_c8_2, x0 67 ldr x0, =0x10FFF00083 68 msr S3_6_c15_c8_3, x0 69 ldr x0, =0x2001003FF 70 msr S3_6_c15_c8_1, x0 71 72 mov x0, #2 73 msr S3_6_c15_c8_0, x0 74 ldr x0, =0x10E3800200 75 msr S3_6_c15_c8_2, x0 76 ldr x0, =0x10FFF003E0 77 msr S3_6_c15_c8_3, x0 78 ldr x0, =0x2001003FF 79 msr S3_6_c15_c8_1, x0 80workaround_reset_end cortex_a78, ERRATUM(1951500) 81 82check_erratum_range cortex_a78, ERRATUM(1951500), CPU_REV(1, 0), CPU_REV(1, 1) 83 84workaround_reset_start cortex_a78, ERRATUM(1952683), ERRATA_A78_1952683 85 ldr x0,=0x5 86 msr S3_6_c15_c8_0,x0 87 ldr x0,=0xEEE10A10 88 msr S3_6_c15_c8_2,x0 89 ldr x0,=0xFFEF0FFF 90 msr S3_6_c15_c8_3,x0 91 ldr x0,=0x0010F000 92 msr S3_6_c15_c8_4,x0 93 ldr x0,=0x0010F000 94 msr S3_6_c15_c8_5,x0 95 ldr x0,=0x40000080023ff 96 msr S3_6_c15_c8_1,x0 97 ldr x0,=0x6 98 msr S3_6_c15_c8_0,x0 99 ldr x0,=0xEE640F34 100 msr S3_6_c15_c8_2,x0 101 ldr x0,=0xFFEF0FFF 102 msr S3_6_c15_c8_3,x0 103 ldr x0,=0x40000080023ff 104 msr S3_6_c15_c8_1,x0 105workaround_reset_end cortex_a78, ERRATUM(1952683) 106 107check_erratum_ls cortex_a78, ERRATUM(1952683), CPU_REV(0, 0) 108 109workaround_reset_start cortex_a78, ERRATUM(2132060), ERRATA_A78_2132060 110 /* Apply the workaround. */ 111 mrs x1, CORTEX_A78_CPUECTLR_EL1 112 mov x0, #CORTEX_A78_CPUECTLR_EL1_PF_MODE_CNSRV 113 bfi x1, x0, #CPUECTLR_EL1_PF_MODE_LSB, #CPUECTLR_EL1_PF_MODE_WIDTH 114 msr CORTEX_A78_CPUECTLR_EL1, x1 115workaround_reset_end cortex_a78, ERRATUM(2132060) 116 117check_erratum_ls cortex_a78, ERRATUM(2132060), CPU_REV(1, 2) 118 119workaround_reset_start cortex_a78, ERRATUM(2242635), ERRATA_A78_2242635 120 ldr x0, =0x5 121 msr S3_6_c15_c8_0, x0 /* CPUPSELR_EL3 */ 122 ldr x0, =0x10F600E000 123 msr S3_6_c15_c8_2, x0 /* CPUPOR_EL3 */ 124 ldr x0, =0x10FF80E000 125 msr S3_6_c15_c8_3, x0 /* CPUPMR_EL3 */ 126 ldr x0, =0x80000000003FF 127 msr S3_6_c15_c8_1, x0 /* CPUPCR_EL3 */ 128workaround_reset_end cortex_a78, ERRATUM(2242635) 129 130check_erratum_range cortex_a78, ERRATUM(2242635), CPU_REV(1, 0), CPU_REV(1, 2) 131 132workaround_reset_start cortex_a78, ERRATUM(2376745), ERRATA_A78_2376745 133 sysreg_bit_set CORTEX_A78_ACTLR2_EL1, BIT(0) 134workaround_reset_end cortex_a78, ERRATUM(2376745) 135 136check_erratum_ls cortex_a78, ERRATUM(2376745), CPU_REV(1, 2) 137 138workaround_reset_start cortex_a78, ERRATUM(2395406), ERRATA_A78_2395406 139 sysreg_bit_set CORTEX_A78_ACTLR2_EL1, BIT(40) 140workaround_reset_end cortex_a78, ERRATUM(2395406) 141 142check_erratum_ls cortex_a78, ERRATUM(2395406), CPU_REV(1, 2) 143 144workaround_reset_start cortex_a78, ERRATUM(2742426), ERRATA_A78_2742426 145 /* Apply the workaround */ 146 mrs x1, CORTEX_A78_ACTLR5_EL1 147 bic x1, x1, #BIT(56) 148 orr x1, x1, #BIT(55) 149 msr CORTEX_A78_ACTLR5_EL1, x1 150workaround_reset_end cortex_a78, ERRATUM(2742426) 151 152check_erratum_ls cortex_a78, ERRATUM(2742426), CPU_REV(1, 2) 153 154workaround_runtime_start cortex_a78, ERRATUM(2772019), ERRATA_A78_2772019 155 /* dsb before isb of power down sequence */ 156 dsb sy 157workaround_runtime_end cortex_a78, ERRATUM(2772019) 158 159check_erratum_ls cortex_a78, ERRATUM(2772019), CPU_REV(1, 2) 160 161workaround_reset_start cortex_a78, ERRATUM(2779479), ERRATA_A78_2779479 162 sysreg_bit_set CORTEX_A78_ACTLR3_EL1, BIT(47) 163workaround_reset_end cortex_a78, ERRATUM(2779479) 164 165check_erratum_ls cortex_a78, ERRATUM(2779479), CPU_REV(1, 2) 166 167workaround_reset_start cortex_a78, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 168#if IMAGE_BL31 169 /* 170 * The Cortex-X1 generic vectors are overridden to apply errata 171 * mitigation on exception entry from lower ELs. 172 */ 173 override_vector_table wa_cve_vbar_cortex_a78 174#endif /* IMAGE_BL31 */ 175workaround_reset_end cortex_a78, CVE(2022, 23960) 176 177check_erratum_chosen cortex_a78, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 178 179cpu_reset_func_start cortex_a78 180#if ENABLE_FEAT_AMU 181 /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ 182 sysreg_bit_clear actlr_el3, CORTEX_A78_ACTLR_TAM_BIT 183 184 /* Make sure accesses from non-secure EL0/EL1 are not trapped to EL2 */ 185 sysreg_bit_clear actlr_el2, CORTEX_A78_ACTLR_TAM_BIT 186 187 /* Enable group0 counters */ 188 mov x0, #CORTEX_A78_AMU_GROUP0_MASK 189 msr CPUAMCNTENSET0_EL0, x0 190 191 /* Enable group1 counters */ 192 mov x0, #CORTEX_A78_AMU_GROUP1_MASK 193 msr CPUAMCNTENSET1_EL0, x0 194#endif 195cpu_reset_func_end cortex_a78 196 197 /* --------------------------------------------- 198 * HW will do the cache maintenance while powering down 199 * --------------------------------------------- 200 */ 201func cortex_a78_core_pwr_dwn 202 sysreg_bit_set CORTEX_A78_CPUPWRCTLR_EL1, CORTEX_A78_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT 203 204 apply_erratum cortex_a78, ERRATUM(2772019), ERRATA_A78_2772019, NO_GET_CPU_REV 205 206 isb 207 ret 208endfunc cortex_a78_core_pwr_dwn 209 210 /* --------------------------------------------- 211 * This function provides cortex_a78 specific 212 * register information for crash reporting. 213 * It needs to return with x6 pointing to 214 * a list of register names in ascii and 215 * x8 - x15 having values of registers to be 216 * reported. 217 * --------------------------------------------- 218 */ 219.section .rodata.cortex_a78_regs, "aS" 220cortex_a78_regs: /* The ascii list of register names to be reported */ 221 .asciz "cpuectlr_el1", "" 222 223func cortex_a78_cpu_reg_dump 224 adr x6, cortex_a78_regs 225 mrs x8, CORTEX_A78_CPUECTLR_EL1 226 ret 227endfunc cortex_a78_cpu_reg_dump 228 229declare_cpu_ops cortex_a78, CORTEX_A78_MIDR, \ 230 cortex_a78_reset_func, \ 231 cortex_a78_core_pwr_dwn 232