Merge "feat(s32g274ardb): use DDR reset deassertion" into integration

feat(s32g274ardb): add DDR post training setup

Add the final configuration step after PHY
training, including CSR storage, memory
initialization and DDRC adjustments.

The post training setup is now

feat(s32g274ardb): add DDR post training setup

Add the final configuration step after PHY
training, including CSR storage, memory
initialization and DDRC adjustments.

The post training setup is now integrated into
the DDR initialization flow.

Change-Id: I457d1f58479b282607c9d42773d6f922f563b2fb
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
Signed-off-by: Andrei Cherechesu <andrei.cherechesu@nxp.com>
Signed-off-by: Khristine Andreea Barbulescu <khristineandreea.barbulescu@nxp.com>

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feat(s32g274ardb): add training for 1D and 2D

Extend the logic for executing the training stage
to include 1D and 2D PHY training.

Change-Id: If3445125d868e67cfcd81eaeeb20b2283731a4ea
Signed-off-by

feat(s32g274ardb): add training for 1D and 2D

Extend the logic for executing the training stage
to include 1D and 2D PHY training.

Change-Id: If3445125d868e67cfcd81eaeeb20b2283731a4ea
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
Signed-off-by: Andrei Cherechesu <andrei.cherechesu@nxp.com>
Signed-off-by: Khristine Andreea Barbulescu <khristineandreea.barbulescu@nxp.com>

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feat(s32g274ardb): add DDR training stubs

Introduce logic to load DDR firmware configuration
data from memory into internal structures.

Introduce the components required to initialize
the DDR contr

feat(s32g274ardb): add DDR training stubs

Introduce logic to load DDR firmware configuration
data from memory into internal structures.

Introduce the components required to initialize
the DDR controller and prepare for PHY training.
It includes controller setup and the training
orchestration function.

Change-Id: Icd8649516d9bad1a6d72616a774b8b60c6bae067
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
Signed-off-by: Andrei Cherechesu <andrei.cherechesu@nxp.com>
Signed-off-by: Khristine Andreea Barbulescu <khristineandreea.barbulescu@nxp.com>

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feat(s32g274ardb): use DDR reset deassertion

The DDR reset must be deasserted after
configuring AXI parity to guarantee the DDRC
registers are accessible for configuration
and PHY training.

Change-

feat(s32g274ardb): use DDR reset deassertion

The DDR reset must be deasserted after
configuring AXI parity to guarantee the DDRC
registers are accessible for configuration
and PHY training.

Change-Id: I80b8df9a7f0058941083893d4e7bb728768ae236
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
Signed-off-by: Andrei Cherechesu <andrei.cherechesu@nxp.com>
Signed-off-by: Khristine Andreea Barbulescu <khristineandreea.barbulescu@nxp.com>

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Merge changes from topic "upstream_ddr_reg_accesories" into integration

* changes:
feat(s32g274ardb): add DDR register accessories
feat(s32g274ardb): add DDR PHY mailbox support

fix(nxp-ddr): fix improper disable of first DDRC

Fixes an issue where the first DDRC is disabled improperly
when two DDRCs are present and only the second DDRC slot is
populated with a DIMM.

Change

fix(nxp-ddr): fix improper disable of first DDRC

Fixes an issue where the first DDRC is disabled improperly
when two DDRCs are present and only the second DDRC slot is
populated with a DIMM.

Change-Id: Ia4f71c5e79fa318a81a291080494f25e76fd987f
Signed-off-by: Roman Meier <romameie@outlook.com>

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feat(s32g274ardb): add DDR register accessories

Introduce a set of helper functions that
simplify register reads, bitfield updates,
AXI parity configuration and extraction
of training values.

These

feat(s32g274ardb): add DDR register accessories

Introduce a set of helper functions that
simplify register reads, bitfield updates,
AXI parity configuration and extraction
of training values.

These utilities encapsulate register access
patterns and are used for delay calibration,
Vref averaging, memory type detection and PLL
source selection.

Change-Id: I5415a650f6430578a8cca13ff7e144b471c61466
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
Signed-off-by: Andrei Cherechesu <andrei.cherechesu@nxp.com>
Signed-off-by: Khristine Andreea Barbulescu <khristineandreea.barbulescu@nxp.com>

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feat(s32g274ardb): add DDR PHY mailbox support

Introduce mailbox handling between the DDR
controller and the PHY firmware, providing
mechanisms for message exchange, acknowledgments,
and execution s

feat(s32g274ardb): add DDR PHY mailbox support

Introduce mailbox handling between the DDR
controller and the PHY firmware, providing
mechanisms for message exchange, acknowledgments,
and execution status monitoring.

This enables reliable tracking of firmware
progress during DDR initialization and training,

Change-Id: I4fdd582fcc9a88c09c820ce9e59fe14ec3c043a8
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
Signed-off-by: Andrei Cherechesu <andrei.cherechesu@nxp.com>
Signed-off-by: Khristine Andreea Barbulescu <khristineandreea.barbulescu@nxp.com>

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fix(nxp-ddr): add missing macro define for Errata A009663

Even though platform support was added in commit 3b0de9182
("feat(plat/nxp/ls1043a): add ls1043a soc support"), the workaround
for errata A0

fix(nxp-ddr): add missing macro define for Errata A009663

Even though platform support was added in commit 3b0de9182
("feat(plat/nxp/ls1043a): add ls1043a soc support"), the workaround
for errata A009663 was not applied due to missing define.

Change-Id: I4f3669adf02dea487f89f81d2fc7344bb65f830d
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>

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