| 2d541cbc | 02-Sep-2022 |
Jiafei Pan <Jiafei.Pan@nxp.com> |
fix(nxp-ddr): fix coverity issue
Fixed coverity issue for "shifting by a negtive value", returned before go to the next shifting code.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com> Change-Id: I001
fix(nxp-ddr): fix coverity issue
Fixed coverity issue for "shifting by a negtive value", returned before go to the next shifting code.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com> Change-Id: I00171b057b8948cb9e9ec5d9405b2e32aba568fb
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| 00bb8c37 | 31-Jan-2022 |
Maninder Singh <maninder.singh_1@nxp.com> |
fix(nxp-ddr): apply Max CDD values for warm boot
Timing CFG 0 and Timing CFG 4 are ddr controller registers that have been affected by 1d phy training during cold boot. They are needed to be stored
fix(nxp-ddr): apply Max CDD values for warm boot
Timing CFG 0 and Timing CFG 4 are ddr controller registers that have been affected by 1d phy training during cold boot. They are needed to be stored and restored along with phy training values.
Signed-off-by: Maninder Singh <maninder.singh_1@nxp.com> Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com> Change-Id: I29c55256e74456515aaeb098e2e0e3475697a466
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