1/* 2 * Copyright (c) 2021-2022, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_a78c.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13#include "wa_cve_2022_23960_bhb_vector.S" 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "cortex_a78c must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20#if WORKAROUND_CVE_2022_23960 21 wa_cve_2022_23960_bhb_vector_table CORTEX_A78C_BHB_LOOP_COUNT, cortex_a78c 22#endif /* WORKAROUND_CVE_2022_23960 */ 23 24func check_errata_cve_2022_23960 25#if WORKAROUND_CVE_2022_23960 26 mov x0, #ERRATA_APPLIES 27#else 28 mov x0, #ERRATA_MISSING 29#endif 30 ret 31endfunc check_errata_cve_2022_23960 32 33 /* ------------------------------------------------- 34 * The CPU Ops reset function for Cortex-A78C 35 * ------------------------------------------------- 36 */ 37func cortex_a78c_reset_func 38#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960 39 /* 40 * The Cortex-A78c generic vectors are overridden to apply errata 41 * mitigation on exception entry from lower ELs. 42 */ 43 adr x0, wa_cve_vbar_cortex_a78c 44 msr vbar_el3, x0 45#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */ 46 isb 47 ret 48endfunc cortex_a78c_reset_func 49 50 /* ---------------------------------------------------- 51 * HW will do the cache maintenance while powering down 52 * ---------------------------------------------------- 53 */ 54func cortex_a78c_core_pwr_dwn 55 /* --------------------------------------------------- 56 * Enable CPU power down bit in power control register 57 * --------------------------------------------------- 58 */ 59 mrs x0, CORTEX_A78C_CPUPWRCTLR_EL1 60 orr x0, x0, #CORTEX_A78C_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT 61 msr CORTEX_A78C_CPUPWRCTLR_EL1, x0 62 isb 63 ret 64endfunc cortex_a78c_core_pwr_dwn 65 66#if REPORT_ERRATA 67/* 68 * Errata printing function for Cortex A78C. Must follow AAPCS. 69 */ 70func cortex_a78c_errata_report 71 stp x8, x30, [sp, #-16]! 72 73 bl cpu_get_rev_var 74 mov x8, x0 75 76 /* 77 * Report all errata. The revision-variant information is passed to 78 * checking functions of each errata. 79 */ 80 report_errata WORKAROUND_CVE_2022_23960, cortex_a78c, cve_2022_23960 81 82 ldp x8, x30, [sp], #16 83 ret 84endfunc cortex_a78c_errata_report 85#endif 86 87 /* --------------------------------------------- 88 * This function provides cortex_a78c specific 89 * register information for crash reporting. 90 * It needs to return with x6 pointing to 91 * a list of register names in ascii and 92 * x8 - x15 having values of registers to be 93 * reported. 94 * --------------------------------------------- 95 */ 96.section .rodata.cortex_a78c_regs, "aS" 97cortex_a78c_regs: /* The ascii list of register names to be reported */ 98 .asciz "cpuectlr_el1", "" 99 100func cortex_a78c_cpu_reg_dump 101 adr x6, cortex_a78c_regs 102 mrs x8, CORTEX_A78C_CPUECTLR_EL1 103 ret 104endfunc cortex_a78c_cpu_reg_dump 105 106declare_cpu_ops cortex_a78c, CORTEX_A78C_MIDR, \ 107 cortex_a78c_reset_func, \ 108 cortex_a78c_core_pwr_dwn 109