1 /* 2 * Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <common/debug.h> 10 #include <drivers/arm/cci.h> 11 #include <drivers/arm/ccn.h> 12 #include <drivers/arm/gicv2.h> 13 #include <drivers/arm/sp804_delay_timer.h> 14 #include <drivers/generic_delay_timer.h> 15 #include <lib/mmio.h> 16 #include <lib/smccc.h> 17 #include <lib/xlat_tables/xlat_tables_compat.h> 18 #include <platform_def.h> 19 #include <services/arm_arch_svc.h> 20 #if SPM_MM 21 #include <services/spm_mm_partition.h> 22 #endif 23 24 #include <plat/arm/common/arm_config.h> 25 #include <plat/arm/common/plat_arm.h> 26 #include <plat/common/platform.h> 27 28 #include "fvp_private.h" 29 30 /* Defines for GIC Driver build time selection */ 31 #define FVP_GICV2 1 32 #define FVP_GICV3 2 33 34 /******************************************************************************* 35 * arm_config holds the characteristics of the differences between the three FVP 36 * platforms (Base, A53_A57 & Foundation). It will be populated during cold boot 37 * at each boot stage by the primary before enabling the MMU (to allow 38 * interconnect configuration) & used thereafter. Each BL will have its own copy 39 * to allow independent operation. 40 ******************************************************************************/ 41 arm_config_t arm_config; 42 43 #define MAP_DEVICE0 MAP_REGION_FLAT(DEVICE0_BASE, \ 44 DEVICE0_SIZE, \ 45 MT_DEVICE | MT_RW | MT_SECURE) 46 47 #define MAP_DEVICE1 MAP_REGION_FLAT(DEVICE1_BASE, \ 48 DEVICE1_SIZE, \ 49 MT_DEVICE | MT_RW | MT_SECURE) 50 51 #if FVP_GICR_REGION_PROTECTION 52 #define MAP_GICD_MEM MAP_REGION_FLAT(BASE_GICD_BASE, \ 53 BASE_GICD_SIZE, \ 54 MT_DEVICE | MT_RW | MT_SECURE) 55 56 /* Map all core's redistributor memory as read-only. After boots up, 57 * per-core map its redistributor memory as read-write */ 58 #define MAP_GICR_MEM MAP_REGION_FLAT(BASE_GICR_BASE, \ 59 (BASE_GICR_SIZE * PLATFORM_CORE_COUNT),\ 60 MT_DEVICE | MT_RO | MT_SECURE) 61 #endif /* FVP_GICR_REGION_PROTECTION */ 62 63 /* 64 * Need to be mapped with write permissions in order to set a new non-volatile 65 * counter value. 66 */ 67 #define MAP_DEVICE2 MAP_REGION_FLAT(DEVICE2_BASE, \ 68 DEVICE2_SIZE, \ 69 MT_DEVICE | MT_RW | MT_SECURE) 70 71 /* 72 * Table of memory regions for various BL stages to map using the MMU. 73 * This doesn't include Trusted SRAM as setup_page_tables() already takes care 74 * of mapping it. 75 */ 76 #ifdef IMAGE_BL1 77 const mmap_region_t plat_arm_mmap[] = { 78 ARM_MAP_SHARED_RAM, 79 V2M_MAP_FLASH0_RO, 80 V2M_MAP_IOFPGA, 81 MAP_DEVICE0, 82 #if FVP_INTERCONNECT_DRIVER == FVP_CCN 83 MAP_DEVICE1, 84 #endif 85 #if TRUSTED_BOARD_BOOT 86 /* To access the Root of Trust Public Key registers. */ 87 MAP_DEVICE2, 88 /* Map DRAM to authenticate NS_BL2U image. */ 89 ARM_MAP_NS_DRAM1, 90 #endif 91 {0} 92 }; 93 #endif 94 #ifdef IMAGE_BL2 95 const mmap_region_t plat_arm_mmap[] = { 96 ARM_MAP_SHARED_RAM, 97 V2M_MAP_FLASH0_RW, 98 V2M_MAP_IOFPGA, 99 MAP_DEVICE0, 100 #if FVP_INTERCONNECT_DRIVER == FVP_CCN 101 MAP_DEVICE1, 102 #endif 103 ARM_MAP_NS_DRAM1, 104 #ifdef __aarch64__ 105 ARM_MAP_DRAM2, 106 #endif 107 /* 108 * Required to load HW_CONFIG, SPMC and SPs to trusted DRAM. 109 */ 110 ARM_MAP_TRUSTED_DRAM, 111 #if ENABLE_RME 112 ARM_MAP_RMM_DRAM, 113 ARM_MAP_GPT_L1_DRAM, 114 #endif /* ENABLE_RME */ 115 #ifdef SPD_tspd 116 ARM_MAP_TSP_SEC_MEM, 117 #endif 118 #if TRUSTED_BOARD_BOOT 119 /* To access the Root of Trust Public Key registers. */ 120 MAP_DEVICE2, 121 #endif /* TRUSTED_BOARD_BOOT */ 122 123 #if CRYPTO_SUPPORT && !BL2_AT_EL3 124 /* 125 * To access shared the Mbed TLS heap while booting the 126 * system with Crypto support 127 */ 128 ARM_MAP_BL1_RW, 129 #endif /* CRYPTO_SUPPORT && !BL2_AT_EL3 */ 130 #if SPM_MM || SPMC_AT_EL3 131 ARM_SP_IMAGE_MMAP, 132 #endif 133 #if ARM_BL31_IN_DRAM 134 ARM_MAP_BL31_SEC_DRAM, 135 #endif 136 #ifdef SPD_opteed 137 ARM_MAP_OPTEE_CORE_MEM, 138 ARM_OPTEE_PAGEABLE_LOAD_MEM, 139 #endif 140 {0} 141 }; 142 #endif 143 #ifdef IMAGE_BL2U 144 const mmap_region_t plat_arm_mmap[] = { 145 MAP_DEVICE0, 146 V2M_MAP_IOFPGA, 147 {0} 148 }; 149 #endif 150 #ifdef IMAGE_BL31 151 const mmap_region_t plat_arm_mmap[] = { 152 ARM_MAP_SHARED_RAM, 153 #if USE_DEBUGFS 154 /* Required by devfip, can be removed if devfip is not used */ 155 V2M_MAP_FLASH0_RW, 156 #endif /* USE_DEBUGFS */ 157 ARM_MAP_EL3_TZC_DRAM, 158 V2M_MAP_IOFPGA, 159 MAP_DEVICE0, 160 #if FVP_GICR_REGION_PROTECTION 161 MAP_GICD_MEM, 162 MAP_GICR_MEM, 163 #else 164 MAP_DEVICE1, 165 #endif /* FVP_GICR_REGION_PROTECTION */ 166 ARM_V2M_MAP_MEM_PROTECT, 167 #if SPM_MM 168 ARM_SPM_BUF_EL3_MMAP, 169 #endif 170 #if ENABLE_RME 171 ARM_MAP_GPT_L1_DRAM, 172 #endif 173 {0} 174 }; 175 176 #if defined(IMAGE_BL31) && SPM_MM 177 const mmap_region_t plat_arm_secure_partition_mmap[] = { 178 V2M_MAP_IOFPGA_EL0, /* for the UART */ 179 MAP_REGION_FLAT(DEVICE0_BASE, \ 180 DEVICE0_SIZE, \ 181 MT_DEVICE | MT_RO | MT_SECURE | MT_USER), 182 ARM_SP_IMAGE_MMAP, 183 ARM_SP_IMAGE_NS_BUF_MMAP, 184 ARM_SP_IMAGE_RW_MMAP, 185 ARM_SPM_BUF_EL0_MMAP, 186 {0} 187 }; 188 #endif 189 #endif 190 #ifdef IMAGE_BL32 191 const mmap_region_t plat_arm_mmap[] = { 192 #ifndef __aarch64__ 193 ARM_MAP_SHARED_RAM, 194 ARM_V2M_MAP_MEM_PROTECT, 195 #endif 196 V2M_MAP_IOFPGA, 197 MAP_DEVICE0, 198 MAP_DEVICE1, 199 {0} 200 }; 201 #endif 202 203 #ifdef IMAGE_RMM 204 const mmap_region_t plat_arm_mmap[] = { 205 V2M_MAP_IOFPGA, 206 MAP_DEVICE0, 207 MAP_DEVICE1, 208 {0} 209 }; 210 #endif 211 212 ARM_CASSERT_MMAP 213 214 #if FVP_INTERCONNECT_DRIVER != FVP_CCN 215 static const int fvp_cci400_map[] = { 216 PLAT_FVP_CCI400_CLUS0_SL_PORT, 217 PLAT_FVP_CCI400_CLUS1_SL_PORT, 218 }; 219 220 static const int fvp_cci5xx_map[] = { 221 PLAT_FVP_CCI5XX_CLUS0_SL_PORT, 222 PLAT_FVP_CCI5XX_CLUS1_SL_PORT, 223 }; 224 225 static unsigned int get_interconnect_master(void) 226 { 227 unsigned int master; 228 u_register_t mpidr; 229 230 mpidr = read_mpidr_el1(); 231 master = ((arm_config.flags & ARM_CONFIG_FVP_SHIFTED_AFF) != 0U) ? 232 MPIDR_AFFLVL2_VAL(mpidr) : MPIDR_AFFLVL1_VAL(mpidr); 233 234 assert(master < FVP_CLUSTER_COUNT); 235 return master; 236 } 237 #endif 238 239 #if defined(IMAGE_BL31) && SPM_MM 240 /* 241 * Boot information passed to a secure partition during initialisation. Linear 242 * indices in MP information will be filled at runtime. 243 */ 244 static spm_mm_mp_info_t sp_mp_info[] = { 245 [0] = {0x80000000, 0}, 246 [1] = {0x80000001, 0}, 247 [2] = {0x80000002, 0}, 248 [3] = {0x80000003, 0}, 249 [4] = {0x80000100, 0}, 250 [5] = {0x80000101, 0}, 251 [6] = {0x80000102, 0}, 252 [7] = {0x80000103, 0}, 253 }; 254 255 const spm_mm_boot_info_t plat_arm_secure_partition_boot_info = { 256 .h.type = PARAM_SP_IMAGE_BOOT_INFO, 257 .h.version = VERSION_1, 258 .h.size = sizeof(spm_mm_boot_info_t), 259 .h.attr = 0, 260 .sp_mem_base = ARM_SP_IMAGE_BASE, 261 .sp_mem_limit = ARM_SP_IMAGE_LIMIT, 262 .sp_image_base = ARM_SP_IMAGE_BASE, 263 .sp_stack_base = PLAT_SP_IMAGE_STACK_BASE, 264 .sp_heap_base = ARM_SP_IMAGE_HEAP_BASE, 265 .sp_ns_comm_buf_base = PLAT_SP_IMAGE_NS_BUF_BASE, 266 .sp_shared_buf_base = PLAT_SPM_BUF_BASE, 267 .sp_image_size = ARM_SP_IMAGE_SIZE, 268 .sp_pcpu_stack_size = PLAT_SP_IMAGE_STACK_PCPU_SIZE, 269 .sp_heap_size = ARM_SP_IMAGE_HEAP_SIZE, 270 .sp_ns_comm_buf_size = PLAT_SP_IMAGE_NS_BUF_SIZE, 271 .sp_shared_buf_size = PLAT_SPM_BUF_SIZE, 272 .num_sp_mem_regions = ARM_SP_IMAGE_NUM_MEM_REGIONS, 273 .num_cpus = PLATFORM_CORE_COUNT, 274 .mp_info = &sp_mp_info[0], 275 }; 276 277 const struct mmap_region *plat_get_secure_partition_mmap(void *cookie) 278 { 279 return plat_arm_secure_partition_mmap; 280 } 281 282 const struct spm_mm_boot_info *plat_get_secure_partition_boot_info( 283 void *cookie) 284 { 285 return &plat_arm_secure_partition_boot_info; 286 } 287 #endif 288 289 /******************************************************************************* 290 * A single boot loader stack is expected to work on both the Foundation FVP 291 * models and the two flavours of the Base FVP models (AEMv8 & Cortex). The 292 * SYS_ID register provides a mechanism for detecting the differences between 293 * these platforms. This information is stored in a per-BL array to allow the 294 * code to take the correct path.Per BL platform configuration. 295 ******************************************************************************/ 296 void __init fvp_config_setup(void) 297 { 298 unsigned int rev, hbi, bld, arch, sys_id; 299 300 sys_id = mmio_read_32(V2M_SYSREGS_BASE + V2M_SYS_ID); 301 rev = (sys_id >> V2M_SYS_ID_REV_SHIFT) & V2M_SYS_ID_REV_MASK; 302 hbi = (sys_id >> V2M_SYS_ID_HBI_SHIFT) & V2M_SYS_ID_HBI_MASK; 303 bld = (sys_id >> V2M_SYS_ID_BLD_SHIFT) & V2M_SYS_ID_BLD_MASK; 304 arch = (sys_id >> V2M_SYS_ID_ARCH_SHIFT) & V2M_SYS_ID_ARCH_MASK; 305 306 if (arch != ARCH_MODEL) { 307 ERROR("This firmware is for FVP models\n"); 308 panic(); 309 } 310 311 /* 312 * The build field in the SYS_ID tells which variant of the GIC 313 * memory is implemented by the model. 314 */ 315 switch (bld) { 316 case BLD_GIC_VE_MMAP: 317 ERROR("Legacy Versatile Express memory map for GIC peripheral" 318 " is not supported\n"); 319 panic(); 320 break; 321 case BLD_GIC_A53A57_MMAP: 322 break; 323 default: 324 ERROR("Unsupported board build %x\n", bld); 325 panic(); 326 } 327 328 /* 329 * The hbi field in the SYS_ID is 0x020 for the Base FVP & 0x010 330 * for the Foundation FVP. 331 */ 332 switch (hbi) { 333 case HBI_FOUNDATION_FVP: 334 arm_config.flags = 0; 335 336 /* 337 * Check for supported revisions of Foundation FVP 338 * Allow future revisions to run but emit warning diagnostic 339 */ 340 switch (rev) { 341 case REV_FOUNDATION_FVP_V2_0: 342 case REV_FOUNDATION_FVP_V2_1: 343 case REV_FOUNDATION_FVP_v9_1: 344 case REV_FOUNDATION_FVP_v9_6: 345 break; 346 default: 347 WARN("Unrecognized Foundation FVP revision %x\n", rev); 348 break; 349 } 350 break; 351 case HBI_BASE_FVP: 352 arm_config.flags |= (ARM_CONFIG_BASE_MMAP | ARM_CONFIG_HAS_TZC); 353 354 /* 355 * Check for supported revisions 356 * Allow future revisions to run but emit warning diagnostic 357 */ 358 switch (rev) { 359 case REV_BASE_FVP_V0: 360 arm_config.flags |= ARM_CONFIG_FVP_HAS_CCI400; 361 break; 362 case REV_BASE_FVP_REVC: 363 arm_config.flags |= (ARM_CONFIG_FVP_HAS_SMMUV3 | 364 ARM_CONFIG_FVP_HAS_CCI5XX); 365 break; 366 default: 367 WARN("Unrecognized Base FVP revision %x\n", rev); 368 break; 369 } 370 break; 371 default: 372 ERROR("Unsupported board HBI number 0x%x\n", hbi); 373 panic(); 374 } 375 376 /* 377 * We assume that the presence of MT bit, and therefore shifted 378 * affinities, is uniform across the platform: either all CPUs, or no 379 * CPUs implement it. 380 */ 381 if ((read_mpidr_el1() & MPIDR_MT_MASK) != 0U) 382 arm_config.flags |= ARM_CONFIG_FVP_SHIFTED_AFF; 383 } 384 385 386 void __init fvp_interconnect_init(void) 387 { 388 #if FVP_INTERCONNECT_DRIVER == FVP_CCN 389 if (ccn_get_part0_id(PLAT_ARM_CCN_BASE) != CCN_502_PART0_ID) { 390 ERROR("Unrecognized CCN variant detected. Only CCN-502 is supported"); 391 panic(); 392 } 393 394 plat_arm_interconnect_init(); 395 #else 396 uintptr_t cci_base = 0U; 397 const int *cci_map = NULL; 398 unsigned int map_size = 0U; 399 400 /* Initialize the right interconnect */ 401 if ((arm_config.flags & ARM_CONFIG_FVP_HAS_CCI5XX) != 0U) { 402 cci_base = PLAT_FVP_CCI5XX_BASE; 403 cci_map = fvp_cci5xx_map; 404 map_size = ARRAY_SIZE(fvp_cci5xx_map); 405 } else if ((arm_config.flags & ARM_CONFIG_FVP_HAS_CCI400) != 0U) { 406 cci_base = PLAT_FVP_CCI400_BASE; 407 cci_map = fvp_cci400_map; 408 map_size = ARRAY_SIZE(fvp_cci400_map); 409 } else { 410 return; 411 } 412 413 assert(cci_base != 0U); 414 assert(cci_map != NULL); 415 cci_init(cci_base, cci_map, map_size); 416 #endif 417 } 418 419 void fvp_interconnect_enable(void) 420 { 421 #if FVP_INTERCONNECT_DRIVER == FVP_CCN 422 plat_arm_interconnect_enter_coherency(); 423 #else 424 unsigned int master; 425 426 if ((arm_config.flags & (ARM_CONFIG_FVP_HAS_CCI400 | 427 ARM_CONFIG_FVP_HAS_CCI5XX)) != 0U) { 428 master = get_interconnect_master(); 429 cci_enable_snoop_dvm_reqs(master); 430 } 431 #endif 432 } 433 434 void fvp_interconnect_disable(void) 435 { 436 #if FVP_INTERCONNECT_DRIVER == FVP_CCN 437 plat_arm_interconnect_exit_coherency(); 438 #else 439 unsigned int master; 440 441 if ((arm_config.flags & (ARM_CONFIG_FVP_HAS_CCI400 | 442 ARM_CONFIG_FVP_HAS_CCI5XX)) != 0U) { 443 master = get_interconnect_master(); 444 cci_disable_snoop_dvm_reqs(master); 445 } 446 #endif 447 } 448 449 #if CRYPTO_SUPPORT 450 int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size) 451 { 452 assert(heap_addr != NULL); 453 assert(heap_size != NULL); 454 455 return arm_get_mbedtls_heap(heap_addr, heap_size); 456 } 457 #endif /* CRYPTO_SUPPORT */ 458 459 void fvp_timer_init(void) 460 { 461 #if USE_SP804_TIMER 462 /* Enable the clock override for SP804 timer 0, which means that no 463 * clock dividers are applied and the raw (35MHz) clock will be used. 464 */ 465 mmio_write_32(V2M_SP810_BASE, FVP_SP810_CTRL_TIM0_OV); 466 467 /* Initialize delay timer driver using SP804 dual timer 0 */ 468 sp804_timer_init(V2M_SP804_TIMER0_BASE, 469 SP804_TIMER_CLKMULT, SP804_TIMER_CLKDIV); 470 #else 471 generic_delay_timer_init(); 472 473 /* Enable System level generic timer */ 474 mmio_write_32(ARM_SYS_CNTCTL_BASE + CNTCR_OFF, 475 CNTCR_FCREQ(0U) | CNTCR_EN); 476 #endif /* USE_SP804_TIMER */ 477 } 478 479 /***************************************************************************** 480 * plat_is_smccc_feature_available() - This function checks whether SMCCC 481 * feature is availabile for platform. 482 * @fid: SMCCC function id 483 * 484 * Return SMC_ARCH_CALL_SUCCESS if SMCCC feature is available and 485 * SMC_ARCH_CALL_NOT_SUPPORTED otherwise. 486 *****************************************************************************/ 487 int32_t plat_is_smccc_feature_available(u_register_t fid) 488 { 489 switch (fid) { 490 case SMCCC_ARCH_SOC_ID: 491 return SMC_ARCH_CALL_SUCCESS; 492 default: 493 return SMC_ARCH_CALL_NOT_SUPPORTED; 494 } 495 } 496 497 /* Get SOC version */ 498 int32_t plat_get_soc_version(void) 499 { 500 return (int32_t) 501 (SOC_ID_SET_JEP_106(ARM_SOC_CONTINUATION_CODE, 502 ARM_SOC_IDENTIFICATION_CODE) | 503 (FVP_SOC_ID & SOC_ID_IMPL_DEF_MASK)); 504 } 505 506 /* Get SOC revision */ 507 int32_t plat_get_soc_revision(void) 508 { 509 unsigned int sys_id; 510 511 sys_id = mmio_read_32(V2M_SYSREGS_BASE + V2M_SYS_ID); 512 return (int32_t)(((sys_id >> V2M_SYS_ID_REV_SHIFT) & 513 V2M_SYS_ID_REV_MASK) & SOC_ID_REV_MASK); 514 } 515