1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * Copyright (c) 2017-2022, STMicroelectronics - All Rights Reserved 4 * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics. 5 */ 6/dts-v1/; 7 8#include "stm32mp157.dtsi" 9#include "stm32mp15xc.dtsi" 10#include "stm32mp15-pinctrl.dtsi" 11#include "stm32mp15xxaa-pinctrl.dtsi" 12#include <dt-bindings/clock/stm32mp1-clksrc.h> 13#include "stm32mp15-ddr3-2x4Gb-1066-binG.dtsi" 14 15/ { 16 model = "STMicroelectronics STM32MP157C eval daughter"; 17 compatible = "st,stm32mp157c-ed1", "st,stm32mp157"; 18 19 chosen { 20 stdout-path = "serial0:115200n8"; 21 }; 22 23 memory@c0000000 { 24 device_type = "memory"; 25 reg = <0xC0000000 0x40000000>; 26 }; 27 28 aliases { 29 serial0 = &uart4; 30 }; 31}; 32 33&bsec { 34 board_id: board_id@ec { 35 reg = <0xec 0x4>; 36 st,non-secure-otp; 37 }; 38}; 39 40&clk_hse { 41 st,digbypass; 42}; 43 44&cpu0 { 45 cpu-supply = <&vddcore>; 46}; 47 48&cpu1 { 49 cpu-supply = <&vddcore>; 50}; 51 52&cryp1 { 53 status = "okay"; 54}; 55 56&hash1 { 57 status = "okay"; 58}; 59 60&i2c4 { 61 pinctrl-names = "default"; 62 pinctrl-0 = <&i2c4_pins_a>; 63 i2c-scl-rising-time-ns = <185>; 64 i2c-scl-falling-time-ns = <20>; 65 clock-frequency = <400000>; 66 status = "okay"; 67 68 pmic: stpmic@33 { 69 compatible = "st,stpmic1"; 70 reg = <0x33>; 71 interrupts-extended = <&exti_pwr 55 IRQ_TYPE_EDGE_FALLING>; 72 interrupt-controller; 73 #interrupt-cells = <2>; 74 status = "okay"; 75 76 regulators { 77 compatible = "st,stpmic1-regulators"; 78 ldo1-supply = <&v3v3>; 79 ldo2-supply = <&v3v3>; 80 ldo3-supply = <&vdd_ddr>; 81 ldo5-supply = <&v3v3>; 82 ldo6-supply = <&v3v3>; 83 pwr_sw1-supply = <&bst_out>; 84 pwr_sw2-supply = <&bst_out>; 85 86 vddcore: buck1 { 87 regulator-name = "vddcore"; 88 regulator-min-microvolt = <1200000>; 89 regulator-max-microvolt = <1350000>; 90 regulator-always-on; 91 regulator-initial-mode = <0>; 92 regulator-over-current-protection; 93 }; 94 95 vdd_ddr: buck2 { 96 regulator-name = "vdd_ddr"; 97 regulator-min-microvolt = <1350000>; 98 regulator-max-microvolt = <1350000>; 99 regulator-always-on; 100 regulator-initial-mode = <0>; 101 regulator-over-current-protection; 102 }; 103 104 vdd: buck3 { 105 regulator-name = "vdd"; 106 regulator-min-microvolt = <3300000>; 107 regulator-max-microvolt = <3300000>; 108 regulator-always-on; 109 st,mask-reset; 110 regulator-initial-mode = <0>; 111 regulator-over-current-protection; 112 }; 113 114 v3v3: buck4 { 115 regulator-name = "v3v3"; 116 regulator-min-microvolt = <3300000>; 117 regulator-max-microvolt = <3300000>; 118 regulator-always-on; 119 regulator-over-current-protection; 120 regulator-initial-mode = <0>; 121 }; 122 123 vdda: ldo1 { 124 regulator-name = "vdda"; 125 regulator-min-microvolt = <2900000>; 126 regulator-max-microvolt = <2900000>; 127 }; 128 129 v2v8: ldo2 { 130 regulator-name = "v2v8"; 131 regulator-min-microvolt = <2800000>; 132 regulator-max-microvolt = <2800000>; 133 }; 134 135 vtt_ddr: ldo3 { 136 regulator-name = "vtt_ddr"; 137 regulator-always-on; 138 regulator-over-current-protection; 139 st,regulator-sink-source; 140 }; 141 142 vdd_usb: ldo4 { 143 regulator-name = "vdd_usb"; 144 regulator-min-microvolt = <3300000>; 145 regulator-max-microvolt = <3300000>; 146 }; 147 148 vdd_sd: ldo5 { 149 regulator-name = "vdd_sd"; 150 regulator-min-microvolt = <2900000>; 151 regulator-max-microvolt = <2900000>; 152 regulator-boot-on; 153 }; 154 155 v1v8: ldo6 { 156 regulator-name = "v1v8"; 157 regulator-min-microvolt = <1800000>; 158 regulator-max-microvolt = <1800000>; 159 }; 160 161 vref_ddr: vref_ddr { 162 regulator-name = "vref_ddr"; 163 regulator-always-on; 164 }; 165 166 bst_out: boost { 167 regulator-name = "bst_out"; 168 }; 169 170 vbus_otg: pwr_sw1 { 171 regulator-name = "vbus_otg"; 172 }; 173 174 vbus_sw: pwr_sw2 { 175 regulator-name = "vbus_sw"; 176 regulator-active-discharge = <1>; 177 }; 178 }; 179 180 onkey { 181 compatible = "st,stpmic1-onkey"; 182 power-off-time-sec = <10>; 183 status = "okay"; 184 }; 185 186 watchdog { 187 compatible = "st,stpmic1-wdt"; 188 status = "disabled"; 189 }; 190 }; 191}; 192 193&iwdg2 { 194 timeout-sec = <32>; 195 status = "okay"; 196}; 197 198&nvmem_layout { 199 nvmem-cells = <&cfg0_otp>, 200 <&part_number_otp>, 201 <&monotonic_otp>, 202 <&nand_otp>, 203 <&uid_otp>, 204 <&package_otp>, 205 <&hw2_otp>, 206 <&board_id>; 207 208 nvmem-cell-names = "cfg0_otp", 209 "part_number_otp", 210 "monotonic_otp", 211 "nand_otp", 212 "uid_otp", 213 "package_otp", 214 "hw2_otp", 215 "board_id"; 216}; 217 218&pwr_regulators { 219 vdd-supply = <&vdd>; 220 vdd_3v3_usbfs-supply = <&vdd_usb>; 221}; 222 223&rcc { 224 secure-status = "disabled"; 225 st,clksrc = < 226 CLK_MPU_PLL1P 227 CLK_AXI_PLL2P 228 CLK_MCU_PLL3P 229 CLK_PLL12_HSE 230 CLK_PLL3_HSE 231 CLK_PLL4_HSE 232 CLK_RTC_LSE 233 CLK_MCO1_DISABLED 234 CLK_MCO2_DISABLED 235 >; 236 237 st,clkdiv = < 238 1 /*MPU*/ 239 0 /*AXI*/ 240 0 /*MCU*/ 241 1 /*APB1*/ 242 1 /*APB2*/ 243 1 /*APB3*/ 244 1 /*APB4*/ 245 2 /*APB5*/ 246 23 /*RTC*/ 247 0 /*MCO1*/ 248 0 /*MCO2*/ 249 >; 250 251 st,pkcs = < 252 CLK_CKPER_HSE 253 CLK_FMC_ACLK 254 CLK_QSPI_ACLK 255 CLK_ETH_PLL4P 256 CLK_SDMMC12_PLL4P 257 CLK_DSI_DSIPLL 258 CLK_STGEN_HSE 259 CLK_USBPHY_HSE 260 CLK_SPI2S1_PLL3Q 261 CLK_SPI2S23_PLL3Q 262 CLK_SPI45_HSI 263 CLK_SPI6_HSI 264 CLK_I2C46_HSI 265 CLK_SDMMC3_PLL4P 266 CLK_USBO_USBPHY 267 CLK_ADC_CKPER 268 CLK_CEC_LSE 269 CLK_I2C12_HSI 270 CLK_I2C35_HSI 271 CLK_UART1_HSI 272 CLK_UART24_HSI 273 CLK_UART35_HSI 274 CLK_UART6_HSI 275 CLK_UART78_HSI 276 CLK_SPDIF_PLL4P 277 CLK_FDCAN_PLL4R 278 CLK_SAI1_PLL3Q 279 CLK_SAI2_PLL3Q 280 CLK_SAI3_PLL3Q 281 CLK_SAI4_PLL3Q 282 CLK_RNG1_LSI 283 CLK_RNG2_LSI 284 CLK_LPTIM1_PCLK1 285 CLK_LPTIM23_PCLK3 286 CLK_LPTIM45_LSE 287 >; 288 289 /* VCO = 1300.0 MHz => P = 650 (CPU) */ 290 pll1: st,pll@0 { 291 compatible = "st,stm32mp1-pll"; 292 reg = <0>; 293 cfg = <2 80 0 0 0 PQR(1,0,0)>; 294 frac = <0x800>; 295 }; 296 297 /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */ 298 pll2: st,pll@1 { 299 compatible = "st,stm32mp1-pll"; 300 reg = <1>; 301 cfg = <2 65 1 0 0 PQR(1,1,1)>; 302 frac = <0x1400>; 303 }; 304 305 /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */ 306 pll3: st,pll@2 { 307 compatible = "st,stm32mp1-pll"; 308 reg = <2>; 309 cfg = <1 33 1 16 36 PQR(1,1,1)>; 310 frac = <0x1a04>; 311 }; 312 313 /* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */ 314 pll4: st,pll@3 { 315 compatible = "st,stm32mp1-pll"; 316 reg = <3>; 317 cfg = <3 98 5 7 7 PQR(1,1,1)>; 318 }; 319}; 320 321&rng1 { 322 status = "okay"; 323}; 324 325&rtc { 326 status = "okay"; 327}; 328 329&sdmmc1 { 330 pinctrl-names = "default"; 331 pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>; 332 disable-wp; 333 st,sig-dir; 334 st,neg-edge; 335 st,use-ckin; 336 bus-width = <4>; 337 vmmc-supply = <&vdd_sd>; 338 sd-uhs-sdr12; 339 sd-uhs-sdr25; 340 sd-uhs-sdr50; 341 sd-uhs-ddr50; 342 status = "okay"; 343}; 344 345&sdmmc2 { 346 pinctrl-names = "default"; 347 pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>; 348 non-removable; 349 no-sd; 350 no-sdio; 351 st,neg-edge; 352 bus-width = <8>; 353 vmmc-supply = <&v3v3>; 354 vqmmc-supply = <&vdd>; 355 mmc-ddr-3_3v; 356 status = "okay"; 357}; 358 359&uart4 { 360 pinctrl-names = "default"; 361 pinctrl-0 = <&uart4_pins_a>; 362 status = "okay"; 363}; 364