1 /* 2 * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 #ifndef ARM_DEF_H 7 #define ARM_DEF_H 8 9 #include <arch.h> 10 #include <common/interrupt_props.h> 11 #include <common/tbbr/tbbr_img_def.h> 12 #include <drivers/arm/gic_common.h> 13 #include <lib/utils_def.h> 14 #include <lib/xlat_tables/xlat_tables_defs.h> 15 #include <plat/arm/common/smccc_def.h> 16 #include <plat/common/common_def.h> 17 18 /****************************************************************************** 19 * Definitions common to all ARM standard platforms 20 *****************************************************************************/ 21 22 /* 23 * Root of trust key hash lengths 24 */ 25 #define ARM_ROTPK_HEADER_LEN 19 26 #define ARM_ROTPK_HASH_LEN 32 27 28 /* Special value used to verify platform parameters from BL2 to BL31 */ 29 #define ARM_BL31_PLAT_PARAM_VAL ULL(0x0f1e2d3c4b5a6978) 30 31 #define ARM_SYSTEM_COUNT U(1) 32 33 #define ARM_CACHE_WRITEBACK_SHIFT 6 34 35 /* 36 * Macros mapping the MPIDR Affinity levels to ARM Platform Power levels. The 37 * power levels have a 1:1 mapping with the MPIDR affinity levels. 38 */ 39 #define ARM_PWR_LVL0 MPIDR_AFFLVL0 40 #define ARM_PWR_LVL1 MPIDR_AFFLVL1 41 #define ARM_PWR_LVL2 MPIDR_AFFLVL2 42 #define ARM_PWR_LVL3 MPIDR_AFFLVL3 43 44 /* 45 * Macros for local power states in ARM platforms encoded by State-ID field 46 * within the power-state parameter. 47 */ 48 /* Local power state for power domains in Run state. */ 49 #define ARM_LOCAL_STATE_RUN U(0) 50 /* Local power state for retention. Valid only for CPU power domains */ 51 #define ARM_LOCAL_STATE_RET U(1) 52 /* Local power state for OFF/power-down. Valid for CPU and cluster power 53 domains */ 54 #define ARM_LOCAL_STATE_OFF U(2) 55 56 /* Memory location options for TSP */ 57 #define ARM_TRUSTED_SRAM_ID 0 58 #define ARM_TRUSTED_DRAM_ID 1 59 #define ARM_DRAM_ID 2 60 61 #ifdef PLAT_ARM_TRUSTED_SRAM_BASE 62 #define ARM_TRUSTED_SRAM_BASE PLAT_ARM_TRUSTED_SRAM_BASE 63 #else 64 #define ARM_TRUSTED_SRAM_BASE UL(0x04000000) 65 #endif /* PLAT_ARM_TRUSTED_SRAM_BASE */ 66 67 #define ARM_SHARED_RAM_BASE ARM_TRUSTED_SRAM_BASE 68 #define ARM_SHARED_RAM_SIZE UL(0x00001000) /* 4 KB */ 69 70 /* The remaining Trusted SRAM is used to load the BL images */ 71 #define ARM_BL_RAM_BASE (ARM_SHARED_RAM_BASE + \ 72 ARM_SHARED_RAM_SIZE) 73 #define ARM_BL_RAM_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ 74 ARM_SHARED_RAM_SIZE) 75 76 /* 77 * The top 16MB (or 64MB if RME is enabled) of DRAM1 is configured as 78 * follows: 79 * - SCP TZC DRAM: If present, DRAM reserved for SCP use 80 * - L1 GPT DRAM: Reserved for L1 GPT if RME is enabled 81 * - REALM DRAM: Reserved for Realm world if RME is enabled 82 * - AP TZC DRAM: The remaining TZC secured DRAM reserved for AP use 83 * 84 * RME enabled(64MB) RME not enabled(16MB) 85 * -------------------- ------------------- 86 * | | | | 87 * | AP TZC (~28MB) | | AP TZC (~14MB) | 88 * -------------------- ------------------- 89 * | | | | 90 * | REALM (32MB) | | EL3 TZC (2MB) | 91 * -------------------- ------------------- 92 * | | | | 93 * | EL3 TZC (3MB) | | SCP TZC | 94 * -------------------- 0xFFFF_FFFF------------------- 95 * | L1 GPT + SCP TZC | 96 * | (~1MB) | 97 * 0xFFFF_FFFF -------------------- 98 */ 99 #if ENABLE_RME 100 #define ARM_TZC_DRAM1_SIZE UL(0x04000000) /* 64MB */ 101 /* 102 * Define a region within the TZC secured DRAM for use by EL3 runtime 103 * firmware. This region is meant to be NOLOAD and will not be zero 104 * initialized. Data sections with the attribute `arm_el3_tzc_dram` will be 105 * placed here. 3MB region is reserved if RME is enabled, 2MB otherwise. 106 */ 107 #define ARM_EL3_TZC_DRAM1_SIZE UL(0x00300000) /* 3MB */ 108 #define ARM_L1_GPT_SIZE UL(0x00100000) /* 1MB */ 109 #define ARM_REALM_SIZE UL(0x02000000) /* 32MB */ 110 #else 111 #define ARM_TZC_DRAM1_SIZE UL(0x01000000) /* 16MB */ 112 #define ARM_EL3_TZC_DRAM1_SIZE UL(0x00200000) /* 2MB */ 113 #define ARM_L1_GPT_SIZE UL(0) 114 #define ARM_REALM_SIZE UL(0) 115 #endif /* ENABLE_RME */ 116 117 #define ARM_SCP_TZC_DRAM1_BASE (ARM_DRAM1_BASE + \ 118 ARM_DRAM1_SIZE - \ 119 (ARM_SCP_TZC_DRAM1_SIZE + \ 120 ARM_L1_GPT_SIZE)) 121 #define ARM_SCP_TZC_DRAM1_SIZE PLAT_ARM_SCP_TZC_DRAM1_SIZE 122 #define ARM_SCP_TZC_DRAM1_END (ARM_SCP_TZC_DRAM1_BASE + \ 123 ARM_SCP_TZC_DRAM1_SIZE - 1U) 124 #if ENABLE_RME 125 #define ARM_L1_GPT_ADDR_BASE (ARM_DRAM1_BASE + \ 126 ARM_DRAM1_SIZE - \ 127 ARM_L1_GPT_SIZE) 128 #define ARM_L1_GPT_END (ARM_L1_GPT_ADDR_BASE + \ 129 ARM_L1_GPT_SIZE - 1U) 130 131 #define ARM_REALM_BASE (ARM_DRAM1_BASE + \ 132 ARM_DRAM1_SIZE - \ 133 (ARM_SCP_TZC_DRAM1_SIZE + \ 134 ARM_EL3_TZC_DRAM1_SIZE + \ 135 ARM_REALM_SIZE + \ 136 ARM_L1_GPT_SIZE)) 137 #define ARM_REALM_END (ARM_REALM_BASE + ARM_REALM_SIZE - 1U) 138 #endif /* ENABLE_RME */ 139 140 #define ARM_EL3_TZC_DRAM1_BASE (ARM_SCP_TZC_DRAM1_BASE - \ 141 ARM_EL3_TZC_DRAM1_SIZE) 142 #define ARM_EL3_TZC_DRAM1_END (ARM_EL3_TZC_DRAM1_BASE + \ 143 ARM_EL3_TZC_DRAM1_SIZE - 1U) 144 145 #define ARM_AP_TZC_DRAM1_BASE (ARM_DRAM1_BASE + \ 146 ARM_DRAM1_SIZE - \ 147 ARM_TZC_DRAM1_SIZE) 148 #define ARM_AP_TZC_DRAM1_SIZE (ARM_TZC_DRAM1_SIZE - \ 149 (ARM_SCP_TZC_DRAM1_SIZE + \ 150 ARM_EL3_TZC_DRAM1_SIZE + \ 151 ARM_REALM_SIZE + \ 152 ARM_L1_GPT_SIZE)) 153 #define ARM_AP_TZC_DRAM1_END (ARM_AP_TZC_DRAM1_BASE + \ 154 ARM_AP_TZC_DRAM1_SIZE - 1U) 155 156 /* Define the Access permissions for Secure peripherals to NS_DRAM */ 157 #if ARM_CRYPTOCELL_INTEG 158 /* 159 * Allow Secure peripheral to read NS DRAM when integrated with CryptoCell. 160 * This is required by CryptoCell to authenticate BL33 which is loaded 161 * into the Non Secure DDR. 162 */ 163 #define ARM_TZC_NS_DRAM_S_ACCESS TZC_REGION_S_RD 164 #else 165 #define ARM_TZC_NS_DRAM_S_ACCESS TZC_REGION_S_NONE 166 #endif 167 168 #ifdef SPD_opteed 169 /* 170 * BL2 needs to map 4MB at the end of TZC_DRAM1 in order to 171 * load/authenticate the trusted os extra image. The first 512KB of 172 * TZC_DRAM1 are reserved for trusted os (OPTEE). The extra image loading 173 * for OPTEE is paged image which only include the paging part using 174 * virtual memory but without "init" data. OPTEE will copy the "init" data 175 * (from pager image) to the first 512KB of TZC_DRAM, and then copy the 176 * extra image behind the "init" data. 177 */ 178 #define ARM_OPTEE_PAGEABLE_LOAD_BASE (ARM_AP_TZC_DRAM1_BASE + \ 179 ARM_AP_TZC_DRAM1_SIZE - \ 180 ARM_OPTEE_PAGEABLE_LOAD_SIZE) 181 #define ARM_OPTEE_PAGEABLE_LOAD_SIZE UL(0x400000) 182 #define ARM_OPTEE_PAGEABLE_LOAD_MEM MAP_REGION_FLAT( \ 183 ARM_OPTEE_PAGEABLE_LOAD_BASE, \ 184 ARM_OPTEE_PAGEABLE_LOAD_SIZE, \ 185 MT_MEMORY | MT_RW | MT_SECURE) 186 187 /* 188 * Map the memory for the OP-TEE core (also known as OP-TEE pager when paging 189 * support is enabled). 190 */ 191 #define ARM_MAP_OPTEE_CORE_MEM MAP_REGION_FLAT( \ 192 BL32_BASE, \ 193 BL32_LIMIT - BL32_BASE, \ 194 MT_MEMORY | MT_RW | MT_SECURE) 195 #endif /* SPD_opteed */ 196 197 #define ARM_NS_DRAM1_BASE ARM_DRAM1_BASE 198 #define ARM_NS_DRAM1_SIZE (ARM_DRAM1_SIZE - \ 199 ARM_TZC_DRAM1_SIZE) 200 #define ARM_NS_DRAM1_END (ARM_NS_DRAM1_BASE + \ 201 ARM_NS_DRAM1_SIZE - 1U) 202 #ifdef PLAT_ARM_DRAM1_BASE 203 #define ARM_DRAM1_BASE PLAT_ARM_DRAM1_BASE 204 #else 205 #define ARM_DRAM1_BASE ULL(0x80000000) 206 #endif /* PLAT_ARM_DRAM1_BASE */ 207 208 #define ARM_DRAM1_SIZE ULL(0x80000000) 209 #define ARM_DRAM1_END (ARM_DRAM1_BASE + \ 210 ARM_DRAM1_SIZE - 1U) 211 212 #define ARM_DRAM2_BASE PLAT_ARM_DRAM2_BASE 213 #define ARM_DRAM2_SIZE PLAT_ARM_DRAM2_SIZE 214 #define ARM_DRAM2_END (ARM_DRAM2_BASE + \ 215 ARM_DRAM2_SIZE - 1U) 216 217 #define ARM_IRQ_SEC_PHY_TIMER 29 218 219 #define ARM_IRQ_SEC_SGI_0 8 220 #define ARM_IRQ_SEC_SGI_1 9 221 #define ARM_IRQ_SEC_SGI_2 10 222 #define ARM_IRQ_SEC_SGI_3 11 223 #define ARM_IRQ_SEC_SGI_4 12 224 #define ARM_IRQ_SEC_SGI_5 13 225 #define ARM_IRQ_SEC_SGI_6 14 226 #define ARM_IRQ_SEC_SGI_7 15 227 228 /* 229 * Define a list of Group 1 Secure and Group 0 interrupt properties as per GICv3 230 * terminology. On a GICv2 system or mode, the lists will be merged and treated 231 * as Group 0 interrupts. 232 */ 233 #define ARM_G1S_IRQ_PROPS(grp) \ 234 INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 235 GIC_INTR_CFG_LEVEL), \ 236 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 237 GIC_INTR_CFG_EDGE), \ 238 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 239 GIC_INTR_CFG_EDGE), \ 240 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 241 GIC_INTR_CFG_EDGE), \ 242 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 243 GIC_INTR_CFG_EDGE), \ 244 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 245 GIC_INTR_CFG_EDGE), \ 246 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 247 GIC_INTR_CFG_EDGE) 248 249 #define ARM_G0_IRQ_PROPS(grp) \ 250 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, PLAT_SDEI_NORMAL_PRI, (grp), \ 251 GIC_INTR_CFG_EDGE), \ 252 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 253 GIC_INTR_CFG_EDGE) 254 255 #define ARM_MAP_SHARED_RAM MAP_REGION_FLAT( \ 256 ARM_SHARED_RAM_BASE, \ 257 ARM_SHARED_RAM_SIZE, \ 258 MT_DEVICE | MT_RW | EL3_PAS) 259 260 #define ARM_MAP_NS_DRAM1 MAP_REGION_FLAT( \ 261 ARM_NS_DRAM1_BASE, \ 262 ARM_NS_DRAM1_SIZE, \ 263 MT_MEMORY | MT_RW | MT_NS) 264 265 #define ARM_MAP_DRAM2 MAP_REGION_FLAT( \ 266 ARM_DRAM2_BASE, \ 267 ARM_DRAM2_SIZE, \ 268 MT_MEMORY | MT_RW | MT_NS) 269 270 #define ARM_MAP_TSP_SEC_MEM MAP_REGION_FLAT( \ 271 TSP_SEC_MEM_BASE, \ 272 TSP_SEC_MEM_SIZE, \ 273 MT_MEMORY | MT_RW | MT_SECURE) 274 275 #if ARM_BL31_IN_DRAM 276 #define ARM_MAP_BL31_SEC_DRAM MAP_REGION_FLAT( \ 277 BL31_BASE, \ 278 PLAT_ARM_MAX_BL31_SIZE, \ 279 MT_MEMORY | MT_RW | MT_SECURE) 280 #endif 281 282 #define ARM_MAP_EL3_TZC_DRAM MAP_REGION_FLAT( \ 283 ARM_EL3_TZC_DRAM1_BASE, \ 284 ARM_EL3_TZC_DRAM1_SIZE, \ 285 MT_MEMORY | MT_RW | EL3_PAS) 286 287 #define ARM_MAP_TRUSTED_DRAM MAP_REGION_FLAT( \ 288 PLAT_ARM_TRUSTED_DRAM_BASE, \ 289 PLAT_ARM_TRUSTED_DRAM_SIZE, \ 290 MT_MEMORY | MT_RW | MT_SECURE) 291 292 #if ENABLE_RME 293 #define ARM_MAP_RMM_DRAM MAP_REGION_FLAT( \ 294 PLAT_ARM_RMM_BASE, \ 295 PLAT_ARM_RMM_SIZE, \ 296 MT_MEMORY | MT_RW | MT_REALM) 297 298 299 #define ARM_MAP_GPT_L1_DRAM MAP_REGION_FLAT( \ 300 ARM_L1_GPT_ADDR_BASE, \ 301 ARM_L1_GPT_SIZE, \ 302 MT_MEMORY | MT_RW | EL3_PAS) 303 304 #endif /* ENABLE_RME */ 305 306 /* 307 * Mapping for the BL1 RW region. This mapping is needed by BL2 in order to 308 * share the Mbed TLS heap. Since the heap is allocated inside BL1, it resides 309 * in the BL1 RW region. Hence, BL2 needs access to the BL1 RW region in order 310 * to be able to access the heap. 311 */ 312 #define ARM_MAP_BL1_RW MAP_REGION_FLAT( \ 313 BL1_RW_BASE, \ 314 BL1_RW_LIMIT - BL1_RW_BASE, \ 315 MT_MEMORY | MT_RW | EL3_PAS) 316 317 /* 318 * If SEPARATE_CODE_AND_RODATA=1 we define a region for each section 319 * otherwise one region is defined containing both. 320 */ 321 #if SEPARATE_CODE_AND_RODATA 322 #define ARM_MAP_BL_RO MAP_REGION_FLAT( \ 323 BL_CODE_BASE, \ 324 BL_CODE_END - BL_CODE_BASE, \ 325 MT_CODE | EL3_PAS), \ 326 MAP_REGION_FLAT( \ 327 BL_RO_DATA_BASE, \ 328 BL_RO_DATA_END \ 329 - BL_RO_DATA_BASE, \ 330 MT_RO_DATA | EL3_PAS) 331 #else 332 #define ARM_MAP_BL_RO MAP_REGION_FLAT( \ 333 BL_CODE_BASE, \ 334 BL_CODE_END - BL_CODE_BASE, \ 335 MT_CODE | EL3_PAS) 336 #endif 337 #if USE_COHERENT_MEM 338 #define ARM_MAP_BL_COHERENT_RAM MAP_REGION_FLAT( \ 339 BL_COHERENT_RAM_BASE, \ 340 BL_COHERENT_RAM_END \ 341 - BL_COHERENT_RAM_BASE, \ 342 MT_DEVICE | MT_RW | EL3_PAS) 343 #endif 344 #if USE_ROMLIB 345 #define ARM_MAP_ROMLIB_CODE MAP_REGION_FLAT( \ 346 ROMLIB_RO_BASE, \ 347 ROMLIB_RO_LIMIT - ROMLIB_RO_BASE,\ 348 MT_CODE | EL3_PAS) 349 350 #define ARM_MAP_ROMLIB_DATA MAP_REGION_FLAT( \ 351 ROMLIB_RW_BASE, \ 352 ROMLIB_RW_END - ROMLIB_RW_BASE,\ 353 MT_MEMORY | MT_RW | EL3_PAS) 354 #endif 355 356 /* 357 * Map mem_protect flash region with read and write permissions 358 */ 359 #define ARM_V2M_MAP_MEM_PROTECT MAP_REGION_FLAT(PLAT_ARM_MEM_PROT_ADDR, \ 360 V2M_FLASH_BLOCK_SIZE, \ 361 MT_DEVICE | MT_RW | MT_SECURE) 362 /* 363 * Map the region for device tree configuration with read and write permissions 364 */ 365 #define ARM_MAP_BL_CONFIG_REGION MAP_REGION_FLAT(ARM_BL_RAM_BASE, \ 366 (ARM_FW_CONFIGS_LIMIT \ 367 - ARM_BL_RAM_BASE), \ 368 MT_MEMORY | MT_RW | EL3_PAS) 369 /* 370 * Map L0_GPT with read and write permissions 371 */ 372 #if ENABLE_RME 373 #define ARM_MAP_L0_GPT_REGION MAP_REGION_FLAT(ARM_L0_GPT_ADDR_BASE, \ 374 ARM_L0_GPT_SIZE, \ 375 MT_MEMORY | MT_RW | MT_ROOT) 376 #endif 377 378 /* 379 * The max number of regions like RO(code), coherent and data required by 380 * different BL stages which need to be mapped in the MMU. 381 */ 382 #define ARM_BL_REGIONS 7 383 384 #define MAX_MMAP_REGIONS (PLAT_ARM_MMAP_ENTRIES + \ 385 ARM_BL_REGIONS) 386 387 /* Memory mapped Generic timer interfaces */ 388 #ifdef PLAT_ARM_SYS_CNTCTL_BASE 389 #define ARM_SYS_CNTCTL_BASE PLAT_ARM_SYS_CNTCTL_BASE 390 #else 391 #define ARM_SYS_CNTCTL_BASE UL(0x2a430000) 392 #endif 393 394 #ifdef PLAT_ARM_SYS_CNTREAD_BASE 395 #define ARM_SYS_CNTREAD_BASE PLAT_ARM_SYS_CNTREAD_BASE 396 #else 397 #define ARM_SYS_CNTREAD_BASE UL(0x2a800000) 398 #endif 399 400 #ifdef PLAT_ARM_SYS_TIMCTL_BASE 401 #define ARM_SYS_TIMCTL_BASE PLAT_ARM_SYS_TIMCTL_BASE 402 #else 403 #define ARM_SYS_TIMCTL_BASE UL(0x2a810000) 404 #endif 405 406 #ifdef PLAT_ARM_SYS_CNT_BASE_S 407 #define ARM_SYS_CNT_BASE_S PLAT_ARM_SYS_CNT_BASE_S 408 #else 409 #define ARM_SYS_CNT_BASE_S UL(0x2a820000) 410 #endif 411 412 #ifdef PLAT_ARM_SYS_CNT_BASE_NS 413 #define ARM_SYS_CNT_BASE_NS PLAT_ARM_SYS_CNT_BASE_NS 414 #else 415 #define ARM_SYS_CNT_BASE_NS UL(0x2a830000) 416 #endif 417 418 #define ARM_CONSOLE_BAUDRATE 115200 419 420 /* Trusted Watchdog constants */ 421 #ifdef PLAT_ARM_SP805_TWDG_BASE 422 #define ARM_SP805_TWDG_BASE PLAT_ARM_SP805_TWDG_BASE 423 #else 424 #define ARM_SP805_TWDG_BASE UL(0x2a490000) 425 #endif 426 #define ARM_SP805_TWDG_CLK_HZ 32768 427 /* The TBBR document specifies a watchdog timeout of 256 seconds. SP805 428 * asserts reset after two consecutive countdowns (2 x 128 = 256 sec) */ 429 #define ARM_TWDG_TIMEOUT_SEC 128 430 #define ARM_TWDG_LOAD_VAL (ARM_SP805_TWDG_CLK_HZ * \ 431 ARM_TWDG_TIMEOUT_SEC) 432 433 /****************************************************************************** 434 * Required platform porting definitions common to all ARM standard platforms 435 *****************************************************************************/ 436 437 /* 438 * This macro defines the deepest retention state possible. A higher state 439 * id will represent an invalid or a power down state. 440 */ 441 #define PLAT_MAX_RET_STATE ARM_LOCAL_STATE_RET 442 443 /* 444 * This macro defines the deepest power down states possible. Any state ID 445 * higher than this is invalid. 446 */ 447 #define PLAT_MAX_OFF_STATE ARM_LOCAL_STATE_OFF 448 449 /* 450 * Some data must be aligned on the biggest cache line size in the platform. 451 * This is known only to the platform as it might have a combination of 452 * integrated and external caches. 453 */ 454 #define CACHE_WRITEBACK_GRANULE (U(1) << ARM_CACHE_WRITEBACK_SHIFT) 455 456 /* 457 * To enable FW_CONFIG to be loaded by BL1, define the corresponding base 458 * and limit. Leave enough space of BL2 meminfo. 459 */ 460 #define ARM_FW_CONFIG_BASE (ARM_BL_RAM_BASE + sizeof(meminfo_t)) 461 #define ARM_FW_CONFIG_LIMIT ((ARM_BL_RAM_BASE + PAGE_SIZE) \ 462 + (PAGE_SIZE / 2U)) 463 464 /* 465 * Boot parameters passed from BL2 to BL31/BL32 are stored here 466 */ 467 #define ARM_BL2_MEM_DESC_BASE (ARM_FW_CONFIG_LIMIT) 468 #define ARM_BL2_MEM_DESC_LIMIT (ARM_BL2_MEM_DESC_BASE \ 469 + (PAGE_SIZE / 2U)) 470 471 /* 472 * Define limit of firmware configuration memory: 473 * ARM_FW_CONFIG + ARM_BL2_MEM_DESC memory 474 */ 475 #define ARM_FW_CONFIGS_LIMIT (ARM_BL_RAM_BASE + (PAGE_SIZE * 2)) 476 477 #if ENABLE_RME 478 /* 479 * Store the L0 GPT on Trusted SRAM next to firmware 480 * configuration memory, 4KB aligned. 481 */ 482 #define ARM_L0_GPT_SIZE (PAGE_SIZE) 483 #define ARM_L0_GPT_ADDR_BASE (ARM_FW_CONFIGS_LIMIT) 484 #define ARM_L0_GPT_LIMIT (ARM_L0_GPT_ADDR_BASE + ARM_L0_GPT_SIZE) 485 #else 486 #define ARM_L0_GPT_SIZE U(0) 487 #endif 488 489 /******************************************************************************* 490 * BL1 specific defines. 491 * BL1 RW data is relocated from ROM to RAM at runtime so we need 2 sets of 492 * addresses. 493 ******************************************************************************/ 494 #define BL1_RO_BASE PLAT_ARM_TRUSTED_ROM_BASE 495 #ifdef PLAT_BL1_RO_LIMIT 496 #define BL1_RO_LIMIT PLAT_BL1_RO_LIMIT 497 #else 498 #define BL1_RO_LIMIT (PLAT_ARM_TRUSTED_ROM_BASE \ 499 + (PLAT_ARM_TRUSTED_ROM_SIZE - \ 500 PLAT_ARM_MAX_ROMLIB_RO_SIZE)) 501 #endif 502 503 /* 504 * Put BL1 RW at the top of the Trusted SRAM. 505 */ 506 #define BL1_RW_BASE (ARM_BL_RAM_BASE + \ 507 ARM_BL_RAM_SIZE - \ 508 (PLAT_ARM_MAX_BL1_RW_SIZE +\ 509 PLAT_ARM_MAX_ROMLIB_RW_SIZE)) 510 #define BL1_RW_LIMIT (ARM_BL_RAM_BASE + \ 511 (ARM_BL_RAM_SIZE - PLAT_ARM_MAX_ROMLIB_RW_SIZE)) 512 513 #define ROMLIB_RO_BASE BL1_RO_LIMIT 514 #define ROMLIB_RO_LIMIT (PLAT_ARM_TRUSTED_ROM_BASE + PLAT_ARM_TRUSTED_ROM_SIZE) 515 516 #define ROMLIB_RW_BASE (BL1_RW_BASE + PLAT_ARM_MAX_BL1_RW_SIZE) 517 #define ROMLIB_RW_END (ROMLIB_RW_BASE + PLAT_ARM_MAX_ROMLIB_RW_SIZE) 518 519 /******************************************************************************* 520 * BL2 specific defines. 521 ******************************************************************************/ 522 #if BL2_AT_EL3 523 /* Put BL2 towards the middle of the Trusted SRAM */ 524 #define BL2_BASE (ARM_TRUSTED_SRAM_BASE + \ 525 (PLAT_ARM_TRUSTED_SRAM_SIZE >> 1) + 0x2000) 526 #define BL2_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) 527 528 #else 529 /* 530 * Put BL2 just below BL1. 531 */ 532 #define BL2_BASE (BL1_RW_BASE - PLAT_ARM_MAX_BL2_SIZE) 533 #define BL2_LIMIT BL1_RW_BASE 534 #endif 535 536 /******************************************************************************* 537 * BL31 specific defines. 538 ******************************************************************************/ 539 #if ARM_BL31_IN_DRAM || SEPARATE_NOBITS_REGION 540 /* 541 * Put BL31 at the bottom of TZC secured DRAM 542 */ 543 #define BL31_BASE ARM_AP_TZC_DRAM1_BASE 544 #define BL31_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ 545 PLAT_ARM_MAX_BL31_SIZE) 546 /* 547 * For SEPARATE_NOBITS_REGION, BL31 PROGBITS are loaded in TZC secured DRAM. 548 * And BL31 NOBITS are loaded in Trusted SRAM such that BL2 is overwritten. 549 */ 550 #if SEPARATE_NOBITS_REGION 551 #define BL31_NOBITS_BASE BL2_BASE 552 #define BL31_NOBITS_LIMIT BL2_LIMIT 553 #endif /* SEPARATE_NOBITS_REGION */ 554 #elif (RESET_TO_BL31) 555 /* Ensure Position Independent support (PIE) is enabled for this config.*/ 556 # if !ENABLE_PIE 557 # error "BL31 must be a PIE if RESET_TO_BL31=1." 558 #endif 559 /* 560 * Since this is PIE, we can define BL31_BASE to 0x0 since this macro is solely 561 * used for building BL31 and not used for loading BL31. 562 */ 563 # define BL31_BASE 0x0 564 # define BL31_LIMIT PLAT_ARM_MAX_BL31_SIZE 565 #else 566 /* Put BL31 below BL2 in the Trusted SRAM.*/ 567 #define BL31_BASE ((ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)\ 568 - PLAT_ARM_MAX_BL31_SIZE) 569 #define BL31_PROGBITS_LIMIT BL2_BASE 570 /* 571 * For BL2_AT_EL3 make sure the BL31 can grow up until BL2_BASE. This is 572 * because in the BL2_AT_EL3 configuration, BL2 is always resident. 573 */ 574 #if BL2_AT_EL3 575 #define BL31_LIMIT BL2_BASE 576 #else 577 #define BL31_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) 578 #endif 579 #endif 580 581 /****************************************************************************** 582 * RMM specific defines 583 *****************************************************************************/ 584 #if ENABLE_RME 585 #define RMM_BASE (ARM_REALM_BASE) 586 #define RMM_LIMIT (RMM_BASE + ARM_REALM_SIZE) 587 #endif 588 589 #if !defined(__aarch64__) || JUNO_AARCH32_EL3_RUNTIME 590 /******************************************************************************* 591 * BL32 specific defines for EL3 runtime in AArch32 mode 592 ******************************************************************************/ 593 # if RESET_TO_SP_MIN && !JUNO_AARCH32_EL3_RUNTIME 594 /* Ensure Position Independent support (PIE) is enabled for this config.*/ 595 # if !ENABLE_PIE 596 # error "BL32 must be a PIE if RESET_TO_SP_MIN=1." 597 #endif 598 /* 599 * Since this is PIE, we can define BL32_BASE to 0x0 since this macro is solely 600 * used for building BL32 and not used for loading BL32. 601 */ 602 # define BL32_BASE 0x0 603 # define BL32_LIMIT PLAT_ARM_MAX_BL32_SIZE 604 # else 605 /* Put BL32 below BL2 in the Trusted SRAM.*/ 606 # define BL32_BASE ((ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)\ 607 - PLAT_ARM_MAX_BL32_SIZE) 608 # define BL32_PROGBITS_LIMIT BL2_BASE 609 # define BL32_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) 610 # endif /* RESET_TO_SP_MIN && !JUNO_AARCH32_EL3_RUNTIME */ 611 612 #else 613 /******************************************************************************* 614 * BL32 specific defines for EL3 runtime in AArch64 mode 615 ******************************************************************************/ 616 /* 617 * On ARM standard platforms, the TSP can execute from Trusted SRAM, 618 * Trusted DRAM (if available) or the DRAM region secured by the TrustZone 619 * controller. 620 */ 621 # if SPM_MM || SPMC_AT_EL3 622 # define TSP_SEC_MEM_BASE (ARM_AP_TZC_DRAM1_BASE + ULL(0x200000)) 623 # define TSP_SEC_MEM_SIZE (ARM_AP_TZC_DRAM1_SIZE - ULL(0x200000)) 624 # define BL32_BASE (ARM_AP_TZC_DRAM1_BASE + ULL(0x200000)) 625 # define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ 626 ARM_AP_TZC_DRAM1_SIZE) 627 # elif defined(SPD_spmd) 628 # define TSP_SEC_MEM_BASE (ARM_AP_TZC_DRAM1_BASE + ULL(0x200000)) 629 # define TSP_SEC_MEM_SIZE (ARM_AP_TZC_DRAM1_SIZE - ULL(0x200000)) 630 # define BL32_BASE PLAT_ARM_SPMC_BASE 631 # define BL32_LIMIT (PLAT_ARM_SPMC_BASE + \ 632 PLAT_ARM_SPMC_SIZE) 633 # elif ARM_BL31_IN_DRAM 634 # define TSP_SEC_MEM_BASE (ARM_AP_TZC_DRAM1_BASE + \ 635 PLAT_ARM_MAX_BL31_SIZE) 636 # define TSP_SEC_MEM_SIZE (ARM_AP_TZC_DRAM1_SIZE - \ 637 PLAT_ARM_MAX_BL31_SIZE) 638 # define BL32_BASE (ARM_AP_TZC_DRAM1_BASE + \ 639 PLAT_ARM_MAX_BL31_SIZE) 640 # define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ 641 ARM_AP_TZC_DRAM1_SIZE) 642 # elif ARM_TSP_RAM_LOCATION_ID == ARM_TRUSTED_SRAM_ID 643 # define TSP_SEC_MEM_BASE ARM_BL_RAM_BASE 644 # define TSP_SEC_MEM_SIZE ARM_BL_RAM_SIZE 645 # define TSP_PROGBITS_LIMIT BL31_BASE 646 # define BL32_BASE ARM_FW_CONFIGS_LIMIT 647 # define BL32_LIMIT BL31_BASE 648 # elif ARM_TSP_RAM_LOCATION_ID == ARM_TRUSTED_DRAM_ID 649 # define TSP_SEC_MEM_BASE PLAT_ARM_TRUSTED_DRAM_BASE 650 # define TSP_SEC_MEM_SIZE PLAT_ARM_TRUSTED_DRAM_SIZE 651 # define BL32_BASE PLAT_ARM_TRUSTED_DRAM_BASE 652 # define BL32_LIMIT (PLAT_ARM_TRUSTED_DRAM_BASE \ 653 + (UL(1) << 21)) 654 # elif ARM_TSP_RAM_LOCATION_ID == ARM_DRAM_ID 655 # define TSP_SEC_MEM_BASE ARM_AP_TZC_DRAM1_BASE 656 # define TSP_SEC_MEM_SIZE ARM_AP_TZC_DRAM1_SIZE 657 # define BL32_BASE ARM_AP_TZC_DRAM1_BASE 658 # define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ 659 ARM_AP_TZC_DRAM1_SIZE) 660 # else 661 # error "Unsupported ARM_TSP_RAM_LOCATION_ID value" 662 # endif 663 #endif /* !__aarch64__ || JUNO_AARCH32_EL3_RUNTIME */ 664 665 /* 666 * BL32 is mandatory in AArch32. In AArch64, undefine BL32_BASE if there is no 667 * SPD and no SPM-MM and no SPMC-AT-EL3, as they are the only ones that can be 668 * used as BL32. 669 */ 670 #if defined(__aarch64__) && !JUNO_AARCH32_EL3_RUNTIME 671 # if defined(SPD_none) && !SPM_MM && !SPMC_AT_EL3 672 # undef BL32_BASE 673 # endif /* defined(SPD_none) && !SPM_MM || !SPMC_AT_EL3 */ 674 #endif /* defined(__aarch64__) && !JUNO_AARCH32_EL3_RUNTIME */ 675 676 /******************************************************************************* 677 * FWU Images: NS_BL1U, BL2U & NS_BL2U defines. 678 ******************************************************************************/ 679 #define BL2U_BASE BL2_BASE 680 #define BL2U_LIMIT BL2_LIMIT 681 682 #define NS_BL2U_BASE ARM_NS_DRAM1_BASE 683 #define NS_BL1U_BASE (PLAT_ARM_NVM_BASE + UL(0x03EB8000)) 684 685 /* 686 * ID of the secure physical generic timer interrupt used by the TSP. 687 */ 688 #define TSP_IRQ_SEC_PHY_TIMER ARM_IRQ_SEC_PHY_TIMER 689 690 691 /* 692 * One cache line needed for bakery locks on ARM platforms 693 */ 694 #define PLAT_PERCPU_BAKERY_LOCK_SIZE (1 * CACHE_WRITEBACK_GRANULE) 695 696 /* Priority levels for ARM platforms */ 697 #define PLAT_RAS_PRI 0x10 698 #define PLAT_SDEI_CRITICAL_PRI 0x60 699 #define PLAT_SDEI_NORMAL_PRI 0x70 700 701 /* ARM platforms use 3 upper bits of secure interrupt priority */ 702 #define PLAT_PRI_BITS 3 703 704 /* SGI used for SDEI signalling */ 705 #define ARM_SDEI_SGI ARM_IRQ_SEC_SGI_0 706 707 #if SDEI_IN_FCONF 708 /* ARM SDEI dynamic private event max count */ 709 #define ARM_SDEI_DP_EVENT_MAX_CNT 3 710 711 /* ARM SDEI dynamic shared event max count */ 712 #define ARM_SDEI_DS_EVENT_MAX_CNT 3 713 #else 714 /* ARM SDEI dynamic private event numbers */ 715 #define ARM_SDEI_DP_EVENT_0 1000 716 #define ARM_SDEI_DP_EVENT_1 1001 717 #define ARM_SDEI_DP_EVENT_2 1002 718 719 /* ARM SDEI dynamic shared event numbers */ 720 #define ARM_SDEI_DS_EVENT_0 2000 721 #define ARM_SDEI_DS_EVENT_1 2001 722 #define ARM_SDEI_DS_EVENT_2 2002 723 724 #define ARM_SDEI_PRIVATE_EVENTS \ 725 SDEI_DEFINE_EVENT_0(ARM_SDEI_SGI), \ 726 SDEI_PRIVATE_EVENT(ARM_SDEI_DP_EVENT_0, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \ 727 SDEI_PRIVATE_EVENT(ARM_SDEI_DP_EVENT_1, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \ 728 SDEI_PRIVATE_EVENT(ARM_SDEI_DP_EVENT_2, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC) 729 730 #define ARM_SDEI_SHARED_EVENTS \ 731 SDEI_SHARED_EVENT(ARM_SDEI_DS_EVENT_0, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \ 732 SDEI_SHARED_EVENT(ARM_SDEI_DS_EVENT_1, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \ 733 SDEI_SHARED_EVENT(ARM_SDEI_DS_EVENT_2, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC) 734 #endif /* SDEI_IN_FCONF */ 735 736 #endif /* ARM_DEF_H */ 737