1 /* 2 * Copyright (C) 2021-2022, STMicroelectronics - All Rights Reserved 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef STM32MP1_FIP_DEF_H 8 #define STM32MP1_FIP_DEF_H 9 10 #define STM32MP_DDR_S_SIZE U(0x01E00000) /* 30 MB */ 11 #define STM32MP_DDR_SHMEM_SIZE U(0x00200000) /* 2 MB */ 12 13 #if STM32MP13 14 #define STM32MP_BL2_RO_SIZE U(0x00015000) /* 84 KB */ 15 #define STM32MP_BL2_SIZE U(0x00017000) /* 92 KB for BL2 */ 16 #define STM32MP_BL2_DTB_SIZE U(0x00004000) /* 16 KB for DTB */ 17 #endif /* STM32MP13 */ 18 #if STM32MP15 19 #define STM32MP_BL2_RO_SIZE U(0x00011000) /* 68 KB */ 20 #define STM32MP_BL2_SIZE U(0x00016000) /* 88 KB for BL2 */ 21 #define STM32MP_BL2_DTB_SIZE U(0x00007000) /* 28 KB for DTB */ 22 #endif /* STM32MP15 */ 23 #define STM32MP_BL32_SIZE U(0x0001B000) /* 108 KB for BL32 */ 24 #define STM32MP_BL32_DTB_SIZE U(0x00005000) /* 20 KB for DTB */ 25 #define STM32MP_FW_CONFIG_MAX_SIZE PAGE_SIZE /* 4 KB for FCONF DTB */ 26 #define STM32MP_HW_CONFIG_MAX_SIZE U(0x40000) /* 256 KB for HW config DTB */ 27 28 #if STM32MP13 29 #define STM32MP_BL2_BASE (STM32MP_BL2_DTB_BASE + \ 30 STM32MP_BL2_DTB_SIZE) 31 #endif /* STM32MP13 */ 32 #if STM32MP15 33 #define STM32MP_BL2_BASE (STM32MP_SEC_SYSRAM_BASE + \ 34 STM32MP_SEC_SYSRAM_SIZE - \ 35 STM32MP_BL2_SIZE) 36 #endif /* STM32MP15 */ 37 38 #define STM32MP_BL2_RO_BASE STM32MP_BL2_BASE 39 40 #define STM32MP_BL2_RW_BASE (STM32MP_BL2_RO_BASE + \ 41 STM32MP_BL2_RO_SIZE) 42 43 #if STM32MP13 44 #define STM32MP_BL2_RW_SIZE (STM32MP_SYSRAM_BASE + \ 45 STM32MP_SYSRAM_SIZE - \ 46 STM32MP_BL2_RW_BASE) 47 48 #define STM32MP_BL2_DTB_BASE STM32MP_SEC_SYSRAM_BASE 49 #endif /* STM32MP13 */ 50 #if STM32MP15 51 #define STM32MP_BL2_RW_SIZE (STM32MP_SEC_SYSRAM_BASE + \ 52 STM32MP_SEC_SYSRAM_SIZE - \ 53 STM32MP_BL2_RW_BASE) 54 55 #define STM32MP_BL2_DTB_BASE (STM32MP_BL2_BASE - \ 56 STM32MP_BL2_DTB_SIZE) 57 #endif /* STM32MP15 */ 58 59 #define STM32MP_BL32_DTB_BASE STM32MP_SYSRAM_BASE 60 61 #define STM32MP_BL32_BASE (STM32MP_BL32_DTB_BASE + \ 62 STM32MP_BL32_DTB_SIZE) 63 64 65 #if defined(IMAGE_BL2) 66 #define STM32MP_DTB_SIZE STM32MP_BL2_DTB_SIZE 67 #define STM32MP_DTB_BASE STM32MP_BL2_DTB_BASE 68 #endif 69 #if defined(IMAGE_BL32) 70 #define STM32MP_DTB_SIZE STM32MP_BL32_DTB_SIZE 71 #define STM32MP_DTB_BASE STM32MP_BL32_DTB_BASE 72 #endif 73 74 #ifdef AARCH32_SP_OPTEE 75 #define STM32MP_OPTEE_BASE STM32MP_SEC_SYSRAM_BASE 76 77 #define STM32MP_OPTEE_SIZE (STM32MP_BL2_DTB_BASE - \ 78 STM32MP_OPTEE_BASE) 79 #endif 80 81 #if STM32MP13 82 #define STM32MP_FW_CONFIG_BASE SRAM3_BASE 83 #endif /* STM32MP13 */ 84 #if STM32MP15 85 #define STM32MP_FW_CONFIG_BASE (STM32MP_SYSRAM_BASE + \ 86 STM32MP_SYSRAM_SIZE - \ 87 PAGE_SIZE) 88 #endif /* STM32MP15 */ 89 #define STM32MP_HW_CONFIG_BASE (STM32MP_BL33_BASE + \ 90 STM32MP_BL33_MAX_SIZE) 91 92 /* 93 * MAX_MMAP_REGIONS is usually: 94 * BL stm32mp1_mmap size + mmap regions in *_plat_arch_setup 95 */ 96 #if defined(IMAGE_BL32) 97 #define MAX_MMAP_REGIONS 10 98 #endif 99 100 /******************************************************************************* 101 * STM32MP1 RAW partition offset for MTD devices 102 ******************************************************************************/ 103 #define STM32MP_NOR_FIP_OFFSET U(0x00080000) 104 #define STM32MP_NAND_FIP_OFFSET U(0x00200000) 105 106 #endif /* STM32MP1_FIP_DEF_H */ 107