1 /* 2 * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 10 #include <arch_helpers.h> 11 #include <common/debug.h> 12 #include <drivers/clk.h> 13 #include <drivers/delay_timer.h> 14 #include <drivers/st/stm32_console.h> 15 #include <drivers/st/stm32mp_clkfunc.h> 16 #include <drivers/st/stm32mp_reset.h> 17 #include <lib/smccc.h> 18 #include <lib/xlat_tables/xlat_tables_v2.h> 19 #include <plat/common/platform.h> 20 #include <services/arm_arch_svc.h> 21 22 #include <platform_def.h> 23 24 #define HEADER_VERSION_MAJOR_MASK GENMASK(23, 16) 25 #define RESET_TIMEOUT_US_1MS 1000U 26 27 static console_t console; 28 29 uintptr_t plat_get_ns_image_entrypoint(void) 30 { 31 return BL33_BASE; 32 } 33 34 unsigned int plat_get_syscnt_freq2(void) 35 { 36 return read_cntfrq_el0(); 37 } 38 39 static uintptr_t boot_ctx_address; 40 static uint16_t boot_itf_selected; 41 42 void stm32mp_save_boot_ctx_address(uintptr_t address) 43 { 44 boot_api_context_t *boot_context = (boot_api_context_t *)address; 45 46 boot_ctx_address = address; 47 boot_itf_selected = boot_context->boot_interface_selected; 48 } 49 50 uintptr_t stm32mp_get_boot_ctx_address(void) 51 { 52 return boot_ctx_address; 53 } 54 55 uint16_t stm32mp_get_boot_itf_selected(void) 56 { 57 return boot_itf_selected; 58 } 59 60 uintptr_t stm32mp_ddrctrl_base(void) 61 { 62 return DDRCTRL_BASE; 63 } 64 65 uintptr_t stm32mp_ddrphyc_base(void) 66 { 67 return DDRPHYC_BASE; 68 } 69 70 uintptr_t stm32mp_pwr_base(void) 71 { 72 return PWR_BASE; 73 } 74 75 uintptr_t stm32mp_rcc_base(void) 76 { 77 return RCC_BASE; 78 } 79 80 bool stm32mp_lock_available(void) 81 { 82 const uint32_t c_m_bits = SCTLR_M_BIT | SCTLR_C_BIT; 83 84 /* The spinlocks are used only when MMU and data cache are enabled */ 85 return (read_sctlr() & c_m_bits) == c_m_bits; 86 } 87 88 int stm32mp_map_ddr_non_cacheable(void) 89 { 90 return mmap_add_dynamic_region(STM32MP_DDR_BASE, STM32MP_DDR_BASE, 91 STM32MP_DDR_MAX_SIZE, 92 MT_NON_CACHEABLE | MT_RW | MT_SECURE); 93 } 94 95 int stm32mp_unmap_ddr(void) 96 { 97 return mmap_remove_dynamic_region(STM32MP_DDR_BASE, 98 STM32MP_DDR_MAX_SIZE); 99 } 100 101 int stm32_get_otp_index(const char *otp_name, uint32_t *otp_idx, 102 uint32_t *otp_len) 103 { 104 assert(otp_name != NULL); 105 assert(otp_idx != NULL); 106 107 return dt_find_otp_name(otp_name, otp_idx, otp_len); 108 } 109 110 int stm32_get_otp_value(const char *otp_name, uint32_t *otp_val) 111 { 112 uint32_t otp_idx; 113 114 assert(otp_name != NULL); 115 assert(otp_val != NULL); 116 117 if (stm32_get_otp_index(otp_name, &otp_idx, NULL) != 0) { 118 return -1; 119 } 120 121 if (stm32_get_otp_value_from_idx(otp_idx, otp_val) != 0) { 122 ERROR("BSEC: %s Read Error\n", otp_name); 123 return -1; 124 } 125 126 return 0; 127 } 128 129 int stm32_get_otp_value_from_idx(const uint32_t otp_idx, uint32_t *otp_val) 130 { 131 uint32_t ret = BSEC_NOT_SUPPORTED; 132 133 assert(otp_val != NULL); 134 135 #if defined(IMAGE_BL2) 136 ret = bsec_shadow_read_otp(otp_val, otp_idx); 137 #elif defined(IMAGE_BL32) 138 ret = bsec_read_otp(otp_val, otp_idx); 139 #else 140 #error "Not supported" 141 #endif 142 if (ret != BSEC_OK) { 143 ERROR("BSEC: idx=%u Read Error\n", otp_idx); 144 return -1; 145 } 146 147 return 0; 148 } 149 150 #if defined(IMAGE_BL2) 151 static void reset_uart(uint32_t reset) 152 { 153 int ret; 154 155 ret = stm32mp_reset_assert(reset, RESET_TIMEOUT_US_1MS); 156 if (ret != 0) { 157 panic(); 158 } 159 160 udelay(2); 161 162 ret = stm32mp_reset_deassert(reset, RESET_TIMEOUT_US_1MS); 163 if (ret != 0) { 164 panic(); 165 } 166 167 mdelay(1); 168 } 169 #endif 170 171 static void set_console(uintptr_t base, uint32_t clk_rate) 172 { 173 unsigned int console_flags; 174 175 if (console_stm32_register(base, clk_rate, 176 (uint32_t)STM32MP_UART_BAUDRATE, &console) == 0) { 177 panic(); 178 } 179 180 console_flags = CONSOLE_FLAG_BOOT | CONSOLE_FLAG_CRASH | 181 CONSOLE_FLAG_TRANSLATE_CRLF; 182 #if !defined(IMAGE_BL2) && defined(DEBUG) 183 console_flags |= CONSOLE_FLAG_RUNTIME; 184 #endif 185 186 console_set_scope(&console, console_flags); 187 } 188 189 int stm32mp_uart_console_setup(void) 190 { 191 struct dt_node_info dt_uart_info; 192 uint32_t clk_rate = 0U; 193 int result; 194 uint32_t boot_itf __unused; 195 uint32_t boot_instance __unused; 196 197 result = dt_get_stdout_uart_info(&dt_uart_info); 198 199 if ((result <= 0) || 200 (dt_uart_info.status == DT_DISABLED)) { 201 return -ENODEV; 202 } 203 204 #if defined(IMAGE_BL2) 205 if ((dt_uart_info.clock < 0) || 206 (dt_uart_info.reset < 0)) { 207 return -ENODEV; 208 } 209 #endif 210 211 #if STM32MP_UART_PROGRAMMER || !defined(IMAGE_BL2) 212 stm32_get_boot_interface(&boot_itf, &boot_instance); 213 214 if ((boot_itf == BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_UART) && 215 (get_uart_address(boot_instance) == dt_uart_info.base)) { 216 return -EACCES; 217 } 218 #endif 219 220 #if defined(IMAGE_BL2) 221 if (dt_set_stdout_pinctrl() != 0) { 222 return -ENODEV; 223 } 224 225 clk_enable((unsigned long)dt_uart_info.clock); 226 227 reset_uart((uint32_t)dt_uart_info.reset); 228 229 clk_rate = clk_get_rate((unsigned long)dt_uart_info.clock); 230 #endif 231 232 set_console(dt_uart_info.base, clk_rate); 233 234 return 0; 235 } 236 237 #if STM32MP_EARLY_CONSOLE 238 void stm32mp_setup_early_console(void) 239 { 240 #if defined(IMAGE_BL2) || STM32MP_RECONFIGURE_CONSOLE 241 plat_crash_console_init(); 242 #endif 243 set_console(STM32MP_DEBUG_USART_BASE, STM32MP_DEBUG_USART_CLK_FRQ); 244 NOTICE("Early console setup\n"); 245 } 246 #endif /* STM32MP_EARLY_CONSOLE */ 247 248 /***************************************************************************** 249 * plat_is_smccc_feature_available() - This function checks whether SMCCC 250 * feature is availabile for platform. 251 * @fid: SMCCC function id 252 * 253 * Return SMC_ARCH_CALL_SUCCESS if SMCCC feature is available and 254 * SMC_ARCH_CALL_NOT_SUPPORTED otherwise. 255 *****************************************************************************/ 256 int32_t plat_is_smccc_feature_available(u_register_t fid) 257 { 258 switch (fid) { 259 case SMCCC_ARCH_SOC_ID: 260 return SMC_ARCH_CALL_SUCCESS; 261 default: 262 return SMC_ARCH_CALL_NOT_SUPPORTED; 263 } 264 } 265 266 /* Get SOC version */ 267 int32_t plat_get_soc_version(void) 268 { 269 uint32_t chip_id = stm32mp_get_chip_dev_id(); 270 uint32_t manfid = SOC_ID_SET_JEP_106(JEDEC_ST_BKID, JEDEC_ST_MFID); 271 272 return (int32_t)(manfid | (chip_id & SOC_ID_IMPL_DEF_MASK)); 273 } 274 275 /* Get SOC revision */ 276 int32_t plat_get_soc_revision(void) 277 { 278 return (int32_t)(stm32mp_get_chip_version() & SOC_ID_REV_MASK); 279 } 280