1 /* 2 * Copyright (c) 2019-2022, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <common/debug.h> 9 #include <common/runtime_svc.h> 10 #include <lib/mmio.h> 11 #include <tools_share/uuid.h> 12 13 #include "socfpga_fcs.h" 14 #include "socfpga_mailbox.h" 15 #include "socfpga_reset_manager.h" 16 #include "socfpga_sip_svc.h" 17 18 19 /* Total buffer the driver can hold */ 20 #define FPGA_CONFIG_BUFFER_SIZE 4 21 22 static config_type request_type = NO_REQUEST; 23 static int current_block, current_buffer; 24 static int read_block, max_blocks; 25 static uint32_t send_id, rcv_id; 26 static uint32_t bytes_per_block, blocks_submitted; 27 static bool bridge_disable; 28 29 /* RSU static variables */ 30 static uint32_t rsu_dcmf_ver[4] = {0}; 31 static uint16_t rsu_dcmf_stat[4] = {0}; 32 static uint32_t rsu_max_retry; 33 34 /* SiP Service UUID */ 35 DEFINE_SVC_UUID2(intl_svc_uid, 36 0xa85273b0, 0xe85a, 0x4862, 0xa6, 0x2a, 37 0xfa, 0x88, 0x88, 0x17, 0x68, 0x81); 38 39 static uint64_t socfpga_sip_handler(uint32_t smc_fid, 40 uint64_t x1, 41 uint64_t x2, 42 uint64_t x3, 43 uint64_t x4, 44 void *cookie, 45 void *handle, 46 uint64_t flags) 47 { 48 ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid); 49 SMC_RET1(handle, SMC_UNK); 50 } 51 52 struct fpga_config_info fpga_config_buffers[FPGA_CONFIG_BUFFER_SIZE]; 53 54 static int intel_fpga_sdm_write_buffer(struct fpga_config_info *buffer) 55 { 56 uint32_t args[3]; 57 58 while (max_blocks > 0 && buffer->size > buffer->size_written) { 59 args[0] = (1<<8); 60 args[1] = buffer->addr + buffer->size_written; 61 if (buffer->size - buffer->size_written <= bytes_per_block) { 62 args[2] = buffer->size - buffer->size_written; 63 current_buffer++; 64 current_buffer %= FPGA_CONFIG_BUFFER_SIZE; 65 } else { 66 args[2] = bytes_per_block; 67 } 68 69 buffer->size_written += args[2]; 70 mailbox_send_cmd_async(&send_id, MBOX_RECONFIG_DATA, args, 71 3U, CMD_INDIRECT); 72 73 buffer->subblocks_sent++; 74 max_blocks--; 75 } 76 77 return !max_blocks; 78 } 79 80 static int intel_fpga_sdm_write_all(void) 81 { 82 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 83 if (intel_fpga_sdm_write_buffer( 84 &fpga_config_buffers[current_buffer])) { 85 break; 86 } 87 } 88 return 0; 89 } 90 91 static uint32_t intel_mailbox_fpga_config_isdone(void) 92 { 93 uint32_t ret; 94 95 switch (request_type) { 96 case RECONFIGURATION: 97 ret = intel_mailbox_get_config_status(MBOX_RECONFIG_STATUS, 98 true); 99 break; 100 case BITSTREAM_AUTH: 101 ret = intel_mailbox_get_config_status(MBOX_RECONFIG_STATUS, 102 false); 103 break; 104 default: 105 ret = intel_mailbox_get_config_status(MBOX_CONFIG_STATUS, 106 false); 107 break; 108 } 109 110 if (ret != 0U) { 111 if (ret == MBOX_CFGSTAT_STATE_CONFIG) { 112 return INTEL_SIP_SMC_STATUS_BUSY; 113 } else { 114 request_type = NO_REQUEST; 115 return INTEL_SIP_SMC_STATUS_ERROR; 116 } 117 } 118 119 if (bridge_disable != 0U) { 120 socfpga_bridges_enable(~0); /* Enable bridge */ 121 bridge_disable = false; 122 } 123 request_type = NO_REQUEST; 124 125 return INTEL_SIP_SMC_STATUS_OK; 126 } 127 128 static int mark_last_buffer_xfer_completed(uint32_t *buffer_addr_completed) 129 { 130 int i; 131 132 for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 133 if (fpga_config_buffers[i].block_number == current_block) { 134 fpga_config_buffers[i].subblocks_sent--; 135 if (fpga_config_buffers[i].subblocks_sent == 0 136 && fpga_config_buffers[i].size <= 137 fpga_config_buffers[i].size_written) { 138 fpga_config_buffers[i].write_requested = 0; 139 current_block++; 140 *buffer_addr_completed = 141 fpga_config_buffers[i].addr; 142 return 0; 143 } 144 } 145 } 146 147 return -1; 148 } 149 150 static int intel_fpga_config_completed_write(uint32_t *completed_addr, 151 uint32_t *count, uint32_t *job_id) 152 { 153 uint32_t resp[5]; 154 unsigned int resp_len = ARRAY_SIZE(resp); 155 int status = INTEL_SIP_SMC_STATUS_OK; 156 int all_completed = 1; 157 *count = 0; 158 159 while (*count < 3) { 160 161 status = mailbox_read_response(job_id, 162 resp, &resp_len); 163 164 if (status < 0) { 165 break; 166 } 167 168 max_blocks++; 169 170 if (mark_last_buffer_xfer_completed( 171 &completed_addr[*count]) == 0) { 172 *count = *count + 1; 173 } else { 174 break; 175 } 176 } 177 178 if (*count <= 0) { 179 if (status != MBOX_NO_RESPONSE && 180 status != MBOX_TIMEOUT && resp_len != 0) { 181 mailbox_clear_response(); 182 request_type = NO_REQUEST; 183 return INTEL_SIP_SMC_STATUS_ERROR; 184 } 185 186 *count = 0; 187 } 188 189 intel_fpga_sdm_write_all(); 190 191 if (*count > 0) { 192 status = INTEL_SIP_SMC_STATUS_OK; 193 } else if (*count == 0) { 194 status = INTEL_SIP_SMC_STATUS_BUSY; 195 } 196 197 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 198 if (fpga_config_buffers[i].write_requested != 0) { 199 all_completed = 0; 200 break; 201 } 202 } 203 204 if (all_completed == 1) { 205 return INTEL_SIP_SMC_STATUS_OK; 206 } 207 208 return status; 209 } 210 211 static int intel_fpga_config_start(uint32_t flag) 212 { 213 uint32_t argument = 0x1; 214 uint32_t response[3]; 215 int status = 0; 216 unsigned int size = 0; 217 unsigned int resp_len = ARRAY_SIZE(response); 218 219 request_type = RECONFIGURATION; 220 221 if (!CONFIG_TEST_FLAG(flag, PARTIAL_CONFIG)) { 222 bridge_disable = true; 223 } 224 225 if (CONFIG_TEST_FLAG(flag, AUTHENTICATION)) { 226 size = 1; 227 bridge_disable = false; 228 request_type = BITSTREAM_AUTH; 229 } 230 231 mailbox_clear_response(); 232 233 mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_CANCEL, NULL, 0U, 234 CMD_CASUAL, NULL, NULL); 235 236 status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_RECONFIG, &argument, size, 237 CMD_CASUAL, response, &resp_len); 238 239 if (status < 0) { 240 bridge_disable = false; 241 request_type = NO_REQUEST; 242 return INTEL_SIP_SMC_STATUS_ERROR; 243 } 244 245 max_blocks = response[0]; 246 bytes_per_block = response[1]; 247 248 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 249 fpga_config_buffers[i].size = 0; 250 fpga_config_buffers[i].size_written = 0; 251 fpga_config_buffers[i].addr = 0; 252 fpga_config_buffers[i].write_requested = 0; 253 fpga_config_buffers[i].block_number = 0; 254 fpga_config_buffers[i].subblocks_sent = 0; 255 } 256 257 blocks_submitted = 0; 258 current_block = 0; 259 read_block = 0; 260 current_buffer = 0; 261 262 /* Disable bridge on full reconfiguration */ 263 if (bridge_disable) { 264 socfpga_bridges_disable(~0); 265 } 266 267 return INTEL_SIP_SMC_STATUS_OK; 268 } 269 270 static bool is_fpga_config_buffer_full(void) 271 { 272 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 273 if (!fpga_config_buffers[i].write_requested) { 274 return false; 275 } 276 } 277 return true; 278 } 279 280 bool is_address_in_ddr_range(uint64_t addr, uint64_t size) 281 { 282 if (!addr && !size) { 283 return true; 284 } 285 if (size > (UINT64_MAX - addr)) { 286 return false; 287 } 288 if (addr < BL31_LIMIT) { 289 return false; 290 } 291 if (addr + size > DRAM_BASE + DRAM_SIZE) { 292 return false; 293 } 294 295 return true; 296 } 297 298 static uint32_t intel_fpga_config_write(uint64_t mem, uint64_t size) 299 { 300 int i; 301 302 intel_fpga_sdm_write_all(); 303 304 if (!is_address_in_ddr_range(mem, size) || 305 is_fpga_config_buffer_full()) { 306 return INTEL_SIP_SMC_STATUS_REJECTED; 307 } 308 309 for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 310 int j = (i + current_buffer) % FPGA_CONFIG_BUFFER_SIZE; 311 312 if (!fpga_config_buffers[j].write_requested) { 313 fpga_config_buffers[j].addr = mem; 314 fpga_config_buffers[j].size = size; 315 fpga_config_buffers[j].size_written = 0; 316 fpga_config_buffers[j].write_requested = 1; 317 fpga_config_buffers[j].block_number = 318 blocks_submitted++; 319 fpga_config_buffers[j].subblocks_sent = 0; 320 break; 321 } 322 } 323 324 if (is_fpga_config_buffer_full()) { 325 return INTEL_SIP_SMC_STATUS_BUSY; 326 } 327 328 return INTEL_SIP_SMC_STATUS_OK; 329 } 330 331 static int is_out_of_sec_range(uint64_t reg_addr) 332 { 333 #if DEBUG 334 return 0; 335 #endif 336 337 switch (reg_addr) { 338 case(0xF8011100): /* ECCCTRL1 */ 339 case(0xF8011104): /* ECCCTRL2 */ 340 case(0xF8011110): /* ERRINTEN */ 341 case(0xF8011114): /* ERRINTENS */ 342 case(0xF8011118): /* ERRINTENR */ 343 case(0xF801111C): /* INTMODE */ 344 case(0xF8011120): /* INTSTAT */ 345 case(0xF8011124): /* DIAGINTTEST */ 346 case(0xF801112C): /* DERRADDRA */ 347 case(0xFFD12028): /* SDMMCGRP_CTRL */ 348 case(0xFFD12044): /* EMAC0 */ 349 case(0xFFD12048): /* EMAC1 */ 350 case(0xFFD1204C): /* EMAC2 */ 351 case(0xFFD12090): /* ECC_INT_MASK_VALUE */ 352 case(0xFFD12094): /* ECC_INT_MASK_SET */ 353 case(0xFFD12098): /* ECC_INT_MASK_CLEAR */ 354 case(0xFFD1209C): /* ECC_INTSTATUS_SERR */ 355 case(0xFFD120A0): /* ECC_INTSTATUS_DERR */ 356 case(0xFFD120C0): /* NOC_TIMEOUT */ 357 case(0xFFD120C4): /* NOC_IDLEREQ_SET */ 358 case(0xFFD120C8): /* NOC_IDLEREQ_CLR */ 359 case(0xFFD120D0): /* NOC_IDLEACK */ 360 case(0xFFD120D4): /* NOC_IDLESTATUS */ 361 case(0xFFD12200): /* BOOT_SCRATCH_COLD0 */ 362 case(0xFFD12204): /* BOOT_SCRATCH_COLD1 */ 363 case(0xFFD12220): /* BOOT_SCRATCH_COLD8 */ 364 case(0xFFD12224): /* BOOT_SCRATCH_COLD9 */ 365 return 0; 366 367 default: 368 break; 369 } 370 371 return -1; 372 } 373 374 /* Secure register access */ 375 uint32_t intel_secure_reg_read(uint64_t reg_addr, uint32_t *retval) 376 { 377 if (is_out_of_sec_range(reg_addr)) { 378 return INTEL_SIP_SMC_STATUS_ERROR; 379 } 380 381 *retval = mmio_read_32(reg_addr); 382 383 return INTEL_SIP_SMC_STATUS_OK; 384 } 385 386 uint32_t intel_secure_reg_write(uint64_t reg_addr, uint32_t val, 387 uint32_t *retval) 388 { 389 if (is_out_of_sec_range(reg_addr)) { 390 return INTEL_SIP_SMC_STATUS_ERROR; 391 } 392 393 mmio_write_32(reg_addr, val); 394 395 return intel_secure_reg_read(reg_addr, retval); 396 } 397 398 uint32_t intel_secure_reg_update(uint64_t reg_addr, uint32_t mask, 399 uint32_t val, uint32_t *retval) 400 { 401 if (!intel_secure_reg_read(reg_addr, retval)) { 402 *retval &= ~mask; 403 *retval |= val & mask; 404 return intel_secure_reg_write(reg_addr, *retval, retval); 405 } 406 407 return INTEL_SIP_SMC_STATUS_ERROR; 408 } 409 410 /* Intel Remote System Update (RSU) services */ 411 uint64_t intel_rsu_update_address; 412 413 static uint32_t intel_rsu_status(uint64_t *respbuf, unsigned int respbuf_sz) 414 { 415 if (mailbox_rsu_status((uint32_t *)respbuf, respbuf_sz) < 0) { 416 return INTEL_SIP_SMC_RSU_ERROR; 417 } 418 419 return INTEL_SIP_SMC_STATUS_OK; 420 } 421 422 static uint32_t intel_rsu_update(uint64_t update_address) 423 { 424 intel_rsu_update_address = update_address; 425 return INTEL_SIP_SMC_STATUS_OK; 426 } 427 428 static uint32_t intel_rsu_notify(uint32_t execution_stage) 429 { 430 if (mailbox_hps_stage_notify(execution_stage) < 0) { 431 return INTEL_SIP_SMC_RSU_ERROR; 432 } 433 434 return INTEL_SIP_SMC_STATUS_OK; 435 } 436 437 static uint32_t intel_rsu_retry_counter(uint32_t *respbuf, uint32_t respbuf_sz, 438 uint32_t *ret_stat) 439 { 440 if (mailbox_rsu_status((uint32_t *)respbuf, respbuf_sz) < 0) { 441 return INTEL_SIP_SMC_RSU_ERROR; 442 } 443 444 *ret_stat = respbuf[8]; 445 return INTEL_SIP_SMC_STATUS_OK; 446 } 447 448 static uint32_t intel_rsu_copy_dcmf_version(uint64_t dcmf_ver_1_0, 449 uint64_t dcmf_ver_3_2) 450 { 451 rsu_dcmf_ver[0] = dcmf_ver_1_0; 452 rsu_dcmf_ver[1] = dcmf_ver_1_0 >> 32; 453 rsu_dcmf_ver[2] = dcmf_ver_3_2; 454 rsu_dcmf_ver[3] = dcmf_ver_3_2 >> 32; 455 456 return INTEL_SIP_SMC_STATUS_OK; 457 } 458 459 static uint32_t intel_rsu_copy_dcmf_status(uint64_t dcmf_stat) 460 { 461 rsu_dcmf_stat[0] = 0xFFFF & (dcmf_stat >> (0 * 16)); 462 rsu_dcmf_stat[1] = 0xFFFF & (dcmf_stat >> (1 * 16)); 463 rsu_dcmf_stat[2] = 0xFFFF & (dcmf_stat >> (2 * 16)); 464 rsu_dcmf_stat[3] = 0xFFFF & (dcmf_stat >> (3 * 16)); 465 466 return INTEL_SIP_SMC_STATUS_OK; 467 } 468 469 /* Intel HWMON services */ 470 static uint32_t intel_hwmon_readtemp(uint32_t chan, uint32_t *retval) 471 { 472 if (mailbox_hwmon_readtemp(chan, retval) < 0) { 473 return INTEL_SIP_SMC_STATUS_ERROR; 474 } 475 476 return INTEL_SIP_SMC_STATUS_OK; 477 } 478 479 static uint32_t intel_hwmon_readvolt(uint32_t chan, uint32_t *retval) 480 { 481 if (mailbox_hwmon_readvolt(chan, retval) < 0) { 482 return INTEL_SIP_SMC_STATUS_ERROR; 483 } 484 485 return INTEL_SIP_SMC_STATUS_OK; 486 } 487 488 /* Mailbox services */ 489 static uint32_t intel_smc_fw_version(uint32_t *fw_version) 490 { 491 int status; 492 unsigned int resp_len = CONFIG_STATUS_WORD_SIZE; 493 uint32_t resp_data[CONFIG_STATUS_WORD_SIZE] = {0U}; 494 495 status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_CONFIG_STATUS, NULL, 0U, 496 CMD_CASUAL, resp_data, &resp_len); 497 498 if (status < 0) { 499 return INTEL_SIP_SMC_STATUS_ERROR; 500 } 501 502 if (resp_len <= CONFIG_STATUS_FW_VER_OFFSET) { 503 return INTEL_SIP_SMC_STATUS_ERROR; 504 } 505 506 *fw_version = resp_data[CONFIG_STATUS_FW_VER_OFFSET] & CONFIG_STATUS_FW_VER_MASK; 507 508 return INTEL_SIP_SMC_STATUS_OK; 509 } 510 511 static uint32_t intel_mbox_send_cmd(uint32_t cmd, uint32_t *args, 512 unsigned int len, uint32_t urgent, uint64_t response, 513 unsigned int resp_len, int *mbox_status, 514 unsigned int *len_in_resp) 515 { 516 *len_in_resp = 0; 517 *mbox_status = GENERIC_RESPONSE_ERROR; 518 519 if (!is_address_in_ddr_range((uint64_t)args, sizeof(uint32_t) * len)) { 520 return INTEL_SIP_SMC_STATUS_REJECTED; 521 } 522 523 int status = mailbox_send_cmd(MBOX_JOB_ID, cmd, args, len, urgent, 524 (uint32_t *) response, &resp_len); 525 526 if (status < 0) { 527 *mbox_status = -status; 528 return INTEL_SIP_SMC_STATUS_ERROR; 529 } 530 531 *mbox_status = 0; 532 *len_in_resp = resp_len; 533 534 flush_dcache_range(response, resp_len * MBOX_WORD_BYTE); 535 536 return INTEL_SIP_SMC_STATUS_OK; 537 } 538 539 static int intel_smc_get_usercode(uint32_t *user_code) 540 { 541 int status; 542 unsigned int resp_len = sizeof(user_code) / MBOX_WORD_BYTE; 543 544 status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_GET_USERCODE, NULL, 545 0U, CMD_CASUAL, user_code, &resp_len); 546 547 if (status < 0) { 548 return INTEL_SIP_SMC_STATUS_ERROR; 549 } 550 551 return INTEL_SIP_SMC_STATUS_OK; 552 } 553 554 uint32_t intel_smc_service_completed(uint64_t addr, uint32_t size, 555 uint32_t mode, uint32_t *job_id, 556 uint32_t *ret_size, uint32_t *mbox_error) 557 { 558 int status = 0; 559 uint32_t resp_len = size / MBOX_WORD_BYTE; 560 561 if (resp_len > MBOX_DATA_MAX_LEN) { 562 return INTEL_SIP_SMC_STATUS_REJECTED; 563 } 564 565 if (!is_address_in_ddr_range(addr, size)) { 566 return INTEL_SIP_SMC_STATUS_REJECTED; 567 } 568 569 if (mode == SERVICE_COMPLETED_MODE_ASYNC) { 570 status = mailbox_read_response_async(job_id, 571 NULL, (uint32_t *) addr, &resp_len, 0); 572 } else { 573 status = mailbox_read_response(job_id, 574 (uint32_t *) addr, &resp_len); 575 576 if (status == MBOX_NO_RESPONSE) { 577 status = MBOX_BUSY; 578 } 579 } 580 581 if (status == MBOX_NO_RESPONSE) { 582 return INTEL_SIP_SMC_STATUS_NO_RESPONSE; 583 } 584 585 if (status == MBOX_BUSY) { 586 return INTEL_SIP_SMC_STATUS_BUSY; 587 } 588 589 *ret_size = resp_len * MBOX_WORD_BYTE; 590 flush_dcache_range(addr, *ret_size); 591 592 if (status != MBOX_RET_OK) { 593 *mbox_error = -status; 594 return INTEL_SIP_SMC_STATUS_ERROR; 595 } 596 597 return INTEL_SIP_SMC_STATUS_OK; 598 } 599 600 /* Miscellaneous HPS services */ 601 uint32_t intel_hps_set_bridges(uint64_t enable, uint64_t mask) 602 { 603 int status = 0; 604 605 if ((enable & SOCFPGA_BRIDGE_ENABLE) != 0U) { 606 if ((enable & SOCFPGA_BRIDGE_HAS_MASK) != 0U) { 607 status = socfpga_bridges_enable((uint32_t)mask); 608 } else { 609 status = socfpga_bridges_enable(~0); 610 } 611 } else { 612 if ((enable & SOCFPGA_BRIDGE_HAS_MASK) != 0U) { 613 status = socfpga_bridges_disable((uint32_t)mask); 614 } else { 615 status = socfpga_bridges_disable(~0); 616 } 617 } 618 619 if (status < 0) { 620 return INTEL_SIP_SMC_STATUS_ERROR; 621 } 622 623 return INTEL_SIP_SMC_STATUS_OK; 624 } 625 626 /* 627 * This function is responsible for handling all SiP calls from the NS world 628 */ 629 630 uintptr_t sip_smc_handler_v1(uint32_t smc_fid, 631 u_register_t x1, 632 u_register_t x2, 633 u_register_t x3, 634 u_register_t x4, 635 void *cookie, 636 void *handle, 637 u_register_t flags) 638 { 639 uint32_t retval = 0, completed_addr[3]; 640 uint32_t retval2 = 0; 641 uint32_t mbox_error = 0; 642 uint64_t retval64, rsu_respbuf[9]; 643 int status = INTEL_SIP_SMC_STATUS_OK; 644 int mbox_status; 645 unsigned int len_in_resp; 646 u_register_t x5, x6, x7; 647 648 switch (smc_fid) { 649 case SIP_SVC_UID: 650 /* Return UID to the caller */ 651 SMC_UUID_RET(handle, intl_svc_uid); 652 653 case INTEL_SIP_SMC_FPGA_CONFIG_ISDONE: 654 status = intel_mailbox_fpga_config_isdone(); 655 SMC_RET4(handle, status, 0, 0, 0); 656 657 case INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM: 658 SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK, 659 INTEL_SIP_SMC_FPGA_CONFIG_ADDR, 660 INTEL_SIP_SMC_FPGA_CONFIG_SIZE - 661 INTEL_SIP_SMC_FPGA_CONFIG_ADDR); 662 663 case INTEL_SIP_SMC_FPGA_CONFIG_START: 664 status = intel_fpga_config_start(x1); 665 SMC_RET4(handle, status, 0, 0, 0); 666 667 case INTEL_SIP_SMC_FPGA_CONFIG_WRITE: 668 status = intel_fpga_config_write(x1, x2); 669 SMC_RET4(handle, status, 0, 0, 0); 670 671 case INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE: 672 status = intel_fpga_config_completed_write(completed_addr, 673 &retval, &rcv_id); 674 switch (retval) { 675 case 1: 676 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, 677 completed_addr[0], 0, 0); 678 679 case 2: 680 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, 681 completed_addr[0], 682 completed_addr[1], 0); 683 684 case 3: 685 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, 686 completed_addr[0], 687 completed_addr[1], 688 completed_addr[2]); 689 690 case 0: 691 SMC_RET4(handle, status, 0, 0, 0); 692 693 default: 694 mailbox_clear_response(); 695 SMC_RET1(handle, INTEL_SIP_SMC_STATUS_ERROR); 696 } 697 698 case INTEL_SIP_SMC_REG_READ: 699 status = intel_secure_reg_read(x1, &retval); 700 SMC_RET3(handle, status, retval, x1); 701 702 case INTEL_SIP_SMC_REG_WRITE: 703 status = intel_secure_reg_write(x1, (uint32_t)x2, &retval); 704 SMC_RET3(handle, status, retval, x1); 705 706 case INTEL_SIP_SMC_REG_UPDATE: 707 status = intel_secure_reg_update(x1, (uint32_t)x2, 708 (uint32_t)x3, &retval); 709 SMC_RET3(handle, status, retval, x1); 710 711 case INTEL_SIP_SMC_RSU_STATUS: 712 status = intel_rsu_status(rsu_respbuf, 713 ARRAY_SIZE(rsu_respbuf)); 714 if (status) { 715 SMC_RET1(handle, status); 716 } else { 717 SMC_RET4(handle, rsu_respbuf[0], rsu_respbuf[1], 718 rsu_respbuf[2], rsu_respbuf[3]); 719 } 720 721 case INTEL_SIP_SMC_RSU_UPDATE: 722 status = intel_rsu_update(x1); 723 SMC_RET1(handle, status); 724 725 case INTEL_SIP_SMC_RSU_NOTIFY: 726 status = intel_rsu_notify(x1); 727 SMC_RET1(handle, status); 728 729 case INTEL_SIP_SMC_RSU_RETRY_COUNTER: 730 status = intel_rsu_retry_counter((uint32_t *)rsu_respbuf, 731 ARRAY_SIZE(rsu_respbuf), &retval); 732 if (status) { 733 SMC_RET1(handle, status); 734 } else { 735 SMC_RET2(handle, status, retval); 736 } 737 738 case INTEL_SIP_SMC_RSU_DCMF_VERSION: 739 SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK, 740 ((uint64_t)rsu_dcmf_ver[1] << 32) | rsu_dcmf_ver[0], 741 ((uint64_t)rsu_dcmf_ver[3] << 32) | rsu_dcmf_ver[2]); 742 743 case INTEL_SIP_SMC_RSU_COPY_DCMF_VERSION: 744 status = intel_rsu_copy_dcmf_version(x1, x2); 745 SMC_RET1(handle, status); 746 747 case INTEL_SIP_SMC_RSU_DCMF_STATUS: 748 SMC_RET2(handle, INTEL_SIP_SMC_STATUS_OK, 749 ((uint64_t)rsu_dcmf_stat[3] << 48) | 750 ((uint64_t)rsu_dcmf_stat[2] << 32) | 751 ((uint64_t)rsu_dcmf_stat[1] << 16) | 752 rsu_dcmf_stat[0]); 753 754 case INTEL_SIP_SMC_RSU_COPY_DCMF_STATUS: 755 status = intel_rsu_copy_dcmf_status(x1); 756 SMC_RET1(handle, status); 757 758 case INTEL_SIP_SMC_RSU_MAX_RETRY: 759 SMC_RET2(handle, INTEL_SIP_SMC_STATUS_OK, rsu_max_retry); 760 761 case INTEL_SIP_SMC_RSU_COPY_MAX_RETRY: 762 rsu_max_retry = x1; 763 SMC_RET1(handle, INTEL_SIP_SMC_STATUS_OK); 764 765 case INTEL_SIP_SMC_ECC_DBE: 766 status = intel_ecc_dbe_notification(x1); 767 SMC_RET1(handle, status); 768 769 case INTEL_SIP_SMC_SERVICE_COMPLETED: 770 status = intel_smc_service_completed(x1, x2, x3, &rcv_id, 771 &len_in_resp, &mbox_error); 772 SMC_RET4(handle, status, mbox_error, x1, len_in_resp); 773 774 case INTEL_SIP_SMC_FIRMWARE_VERSION: 775 status = intel_smc_fw_version(&retval); 776 SMC_RET2(handle, status, retval); 777 778 case INTEL_SIP_SMC_MBOX_SEND_CMD: 779 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 780 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 781 status = intel_mbox_send_cmd(x1, (uint32_t *)x2, x3, x4, x5, x6, 782 &mbox_status, &len_in_resp); 783 SMC_RET3(handle, status, mbox_status, len_in_resp); 784 785 case INTEL_SIP_SMC_GET_USERCODE: 786 status = intel_smc_get_usercode(&retval); 787 SMC_RET2(handle, status, retval); 788 789 case INTEL_SIP_SMC_FCS_CRYPTION: 790 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 791 792 if (x1 == FCS_MODE_DECRYPT) { 793 status = intel_fcs_decryption(x2, x3, x4, x5, &send_id); 794 } else if (x1 == FCS_MODE_ENCRYPT) { 795 status = intel_fcs_encryption(x2, x3, x4, x5, &send_id); 796 } else { 797 status = INTEL_SIP_SMC_STATUS_REJECTED; 798 } 799 800 SMC_RET3(handle, status, x4, x5); 801 802 case INTEL_SIP_SMC_FCS_CRYPTION_EXT: 803 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 804 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 805 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 806 807 if (x3 == FCS_MODE_DECRYPT) { 808 status = intel_fcs_decryption_ext(x1, x2, x4, x5, x6, 809 (uint32_t *) &x7, &mbox_error); 810 } else if (x3 == FCS_MODE_ENCRYPT) { 811 status = intel_fcs_encryption_ext(x1, x2, x4, x5, x6, 812 (uint32_t *) &x7, &mbox_error); 813 } else { 814 status = INTEL_SIP_SMC_STATUS_REJECTED; 815 } 816 817 SMC_RET4(handle, status, mbox_error, x6, x7); 818 819 case INTEL_SIP_SMC_FCS_RANDOM_NUMBER: 820 status = intel_fcs_random_number_gen(x1, &retval64, 821 &mbox_error); 822 SMC_RET4(handle, status, mbox_error, x1, retval64); 823 824 case INTEL_SIP_SMC_FCS_RANDOM_NUMBER_EXT: 825 status = intel_fcs_random_number_gen_ext(x1, x2, x3, 826 &send_id); 827 SMC_RET1(handle, status); 828 829 case INTEL_SIP_SMC_FCS_SEND_CERTIFICATE: 830 status = intel_fcs_send_cert(x1, x2, &send_id); 831 SMC_RET1(handle, status); 832 833 case INTEL_SIP_SMC_FCS_GET_PROVISION_DATA: 834 status = intel_fcs_get_provision_data(&send_id); 835 SMC_RET1(handle, status); 836 837 case INTEL_SIP_SMC_FCS_CNTR_SET_PREAUTH: 838 status = intel_fcs_cntr_set_preauth(x1, x2, x3, 839 &mbox_error); 840 SMC_RET2(handle, status, mbox_error); 841 842 case INTEL_SIP_SMC_HPS_SET_BRIDGES: 843 status = intel_hps_set_bridges(x1, x2); 844 SMC_RET1(handle, status); 845 846 case INTEL_SIP_SMC_HWMON_READTEMP: 847 status = intel_hwmon_readtemp(x1, &retval); 848 SMC_RET2(handle, status, retval); 849 850 case INTEL_SIP_SMC_HWMON_READVOLT: 851 status = intel_hwmon_readvolt(x1, &retval); 852 SMC_RET2(handle, status, retval); 853 854 case INTEL_SIP_SMC_FCS_PSGSIGMA_TEARDOWN: 855 status = intel_fcs_sigma_teardown(x1, &mbox_error); 856 SMC_RET2(handle, status, mbox_error); 857 858 case INTEL_SIP_SMC_FCS_CHIP_ID: 859 status = intel_fcs_chip_id(&retval, &retval2, &mbox_error); 860 SMC_RET4(handle, status, mbox_error, retval, retval2); 861 862 case INTEL_SIP_SMC_FCS_ATTESTATION_SUBKEY: 863 status = intel_fcs_attestation_subkey(x1, x2, x3, 864 (uint32_t *) &x4, &mbox_error); 865 SMC_RET4(handle, status, mbox_error, x3, x4); 866 867 case INTEL_SIP_SMC_FCS_ATTESTATION_MEASUREMENTS: 868 status = intel_fcs_get_measurement(x1, x2, x3, 869 (uint32_t *) &x4, &mbox_error); 870 SMC_RET4(handle, status, mbox_error, x3, x4); 871 872 case INTEL_SIP_SMC_FCS_GET_ATTESTATION_CERT: 873 status = intel_fcs_get_attestation_cert(x1, x2, 874 (uint32_t *) &x3, &mbox_error); 875 SMC_RET4(handle, status, mbox_error, x2, x3); 876 877 case INTEL_SIP_SMC_FCS_CREATE_CERT_ON_RELOAD: 878 status = intel_fcs_create_cert_on_reload(x1, &mbox_error); 879 SMC_RET2(handle, status, mbox_error); 880 881 case INTEL_SIP_SMC_FCS_OPEN_CS_SESSION: 882 status = intel_fcs_open_crypto_service_session(&retval, &mbox_error); 883 SMC_RET3(handle, status, mbox_error, retval); 884 885 case INTEL_SIP_SMC_FCS_CLOSE_CS_SESSION: 886 status = intel_fcs_close_crypto_service_session(x1, &mbox_error); 887 SMC_RET2(handle, status, mbox_error); 888 889 case INTEL_SIP_SMC_FCS_IMPORT_CS_KEY: 890 status = intel_fcs_import_crypto_service_key(x1, x2, &send_id); 891 SMC_RET1(handle, status); 892 893 case INTEL_SIP_SMC_FCS_EXPORT_CS_KEY: 894 status = intel_fcs_export_crypto_service_key(x1, x2, x3, 895 (uint32_t *) &x4, &mbox_error); 896 SMC_RET4(handle, status, mbox_error, x3, x4); 897 898 case INTEL_SIP_SMC_FCS_REMOVE_CS_KEY: 899 status = intel_fcs_remove_crypto_service_key(x1, x2, 900 &mbox_error); 901 SMC_RET2(handle, status, mbox_error); 902 903 case INTEL_SIP_SMC_FCS_GET_CS_KEY_INFO: 904 status = intel_fcs_get_crypto_service_key_info(x1, x2, x3, 905 (uint32_t *) &x4, &mbox_error); 906 SMC_RET4(handle, status, mbox_error, x3, x4); 907 908 case INTEL_SIP_SMC_FCS_GET_DIGEST_INIT: 909 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 910 status = intel_fcs_get_digest_init(x1, x2, x3, 911 x4, x5, &mbox_error); 912 SMC_RET2(handle, status, mbox_error); 913 914 case INTEL_SIP_SMC_FCS_GET_DIGEST_UPDATE: 915 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 916 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 917 status = intel_fcs_get_digest_update_finalize(x1, x2, x3, 918 x4, x5, (uint32_t *) &x6, false, 919 &mbox_error); 920 SMC_RET4(handle, status, mbox_error, x5, x6); 921 922 case INTEL_SIP_SMC_FCS_GET_DIGEST_FINALIZE: 923 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 924 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 925 status = intel_fcs_get_digest_update_finalize(x1, x2, x3, 926 x4, x5, (uint32_t *) &x6, true, 927 &mbox_error); 928 SMC_RET4(handle, status, mbox_error, x5, x6); 929 930 case INTEL_SIP_SMC_FCS_MAC_VERIFY_INIT: 931 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 932 status = intel_fcs_mac_verify_init(x1, x2, x3, 933 x4, x5, &mbox_error); 934 SMC_RET2(handle, status, mbox_error); 935 936 case INTEL_SIP_SMC_FCS_MAC_VERIFY_UPDATE: 937 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 938 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 939 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 940 status = intel_fcs_mac_verify_update_finalize(x1, x2, x3, 941 x4, x5, (uint32_t *) &x6, x7, 942 false, &mbox_error); 943 SMC_RET4(handle, status, mbox_error, x5, x6); 944 945 case INTEL_SIP_SMC_FCS_MAC_VERIFY_FINALIZE: 946 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 947 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 948 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 949 status = intel_fcs_mac_verify_update_finalize(x1, x2, x3, 950 x4, x5, (uint32_t *) &x6, x7, 951 true, &mbox_error); 952 SMC_RET4(handle, status, mbox_error, x5, x6); 953 954 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_INIT: 955 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 956 status = intel_fcs_ecdsa_sha2_data_sign_init(x1, x2, x3, 957 x4, x5, &mbox_error); 958 SMC_RET2(handle, status, mbox_error); 959 960 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_UPDATE: 961 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 962 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 963 status = intel_fcs_ecdsa_sha2_data_sign_update_finalize(x1, x2, 964 x3, x4, x5, (uint32_t *) &x6, false, 965 &mbox_error); 966 SMC_RET4(handle, status, mbox_error, x5, x6); 967 968 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_FINALIZE: 969 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 970 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 971 status = intel_fcs_ecdsa_sha2_data_sign_update_finalize(x1, x2, 972 x3, x4, x5, (uint32_t *) &x6, true, 973 &mbox_error); 974 SMC_RET4(handle, status, mbox_error, x5, x6); 975 976 case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIGN_INIT: 977 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 978 status = intel_fcs_ecdsa_hash_sign_init(x1, x2, x3, 979 x4, x5, &mbox_error); 980 SMC_RET2(handle, status, mbox_error); 981 982 case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIGN_FINALIZE: 983 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 984 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 985 status = intel_fcs_ecdsa_hash_sign_finalize(x1, x2, x3, 986 x4, x5, (uint32_t *) &x6, &mbox_error); 987 SMC_RET4(handle, status, mbox_error, x5, x6); 988 989 case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIG_VERIFY_INIT: 990 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 991 status = intel_fcs_ecdsa_hash_sig_verify_init(x1, x2, x3, 992 x4, x5, &mbox_error); 993 SMC_RET2(handle, status, mbox_error); 994 995 case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIG_VERIFY_FINALIZE: 996 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 997 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 998 status = intel_fcs_ecdsa_hash_sig_verify_finalize(x1, x2, x3, 999 x4, x5, (uint32_t *) &x6, &mbox_error); 1000 SMC_RET4(handle, status, mbox_error, x5, x6); 1001 1002 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_INIT: 1003 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1004 status = intel_fcs_ecdsa_sha2_data_sig_verify_init(x1, x2, x3, 1005 x4, x5, &mbox_error); 1006 SMC_RET2(handle, status, mbox_error); 1007 1008 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_UPDATE: 1009 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1010 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1011 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 1012 status = intel_fcs_ecdsa_sha2_data_sig_verify_update_finalize( 1013 x1, x2, x3, x4, x5, (uint32_t *) &x6, 1014 x7, false, &mbox_error); 1015 SMC_RET4(handle, status, mbox_error, x5, x6); 1016 1017 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_FINALIZE: 1018 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1019 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1020 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 1021 status = intel_fcs_ecdsa_sha2_data_sig_verify_update_finalize( 1022 x1, x2, x3, x4, x5, (uint32_t *) &x6, 1023 x7, true, &mbox_error); 1024 SMC_RET4(handle, status, mbox_error, x5, x6); 1025 1026 case INTEL_SIP_SMC_FCS_ECDSA_GET_PUBKEY_INIT: 1027 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1028 status = intel_fcs_ecdsa_get_pubkey_init(x1, x2, x3, 1029 x4, x5, &mbox_error); 1030 SMC_RET2(handle, status, mbox_error); 1031 1032 case INTEL_SIP_SMC_FCS_ECDSA_GET_PUBKEY_FINALIZE: 1033 status = intel_fcs_ecdsa_get_pubkey_finalize(x1, x2, x3, 1034 (uint32_t *) &x4, &mbox_error); 1035 SMC_RET4(handle, status, mbox_error, x3, x4); 1036 1037 case INTEL_SIP_SMC_FCS_ECDH_REQUEST_INIT: 1038 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1039 status = intel_fcs_ecdh_request_init(x1, x2, x3, 1040 x4, x5, &mbox_error); 1041 SMC_RET2(handle, status, mbox_error); 1042 1043 case INTEL_SIP_SMC_FCS_ECDH_REQUEST_FINALIZE: 1044 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1045 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1046 status = intel_fcs_ecdh_request_finalize(x1, x2, x3, 1047 x4, x5, (uint32_t *) &x6, &mbox_error); 1048 SMC_RET4(handle, status, mbox_error, x5, x6); 1049 1050 case INTEL_SIP_SMC_FCS_AES_CRYPT_INIT: 1051 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1052 status = intel_fcs_aes_crypt_init(x1, x2, x3, x4, x5, 1053 &mbox_error); 1054 SMC_RET2(handle, status, mbox_error); 1055 1056 case INTEL_SIP_SMC_FCS_AES_CRYPT_UPDATE: 1057 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1058 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1059 status = intel_fcs_aes_crypt_update_finalize(x1, x2, x3, x4, 1060 x5, x6, false, &send_id); 1061 SMC_RET1(handle, status); 1062 1063 case INTEL_SIP_SMC_FCS_AES_CRYPT_FINALIZE: 1064 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1065 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1066 status = intel_fcs_aes_crypt_update_finalize(x1, x2, x3, x4, 1067 x5, x6, true, &send_id); 1068 SMC_RET1(handle, status); 1069 1070 case INTEL_SIP_SMC_GET_ROM_PATCH_SHA384: 1071 status = intel_fcs_get_rom_patch_sha384(x1, &retval64, 1072 &mbox_error); 1073 SMC_RET4(handle, status, mbox_error, x1, retval64); 1074 1075 case INTEL_SIP_SMC_SVC_VERSION: 1076 SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK, 1077 SIP_SVC_VERSION_MAJOR, 1078 SIP_SVC_VERSION_MINOR); 1079 1080 default: 1081 return socfpga_sip_handler(smc_fid, x1, x2, x3, x4, 1082 cookie, handle, flags); 1083 } 1084 } 1085 1086 uintptr_t sip_smc_handler(uint32_t smc_fid, 1087 u_register_t x1, 1088 u_register_t x2, 1089 u_register_t x3, 1090 u_register_t x4, 1091 void *cookie, 1092 void *handle, 1093 u_register_t flags) 1094 { 1095 uint32_t cmd = smc_fid & INTEL_SIP_SMC_CMD_MASK; 1096 1097 if (cmd >= INTEL_SIP_SMC_CMD_V2_RANGE_BEGIN && 1098 cmd <= INTEL_SIP_SMC_CMD_V2_RANGE_END) { 1099 return sip_smc_handler_v2(smc_fid, x1, x2, x3, x4, 1100 cookie, handle, flags); 1101 } else { 1102 return sip_smc_handler_v1(smc_fid, x1, x2, x3, x4, 1103 cookie, handle, flags); 1104 } 1105 } 1106 1107 DECLARE_RT_SVC( 1108 socfpga_sip_svc, 1109 OEN_SIP_START, 1110 OEN_SIP_END, 1111 SMC_TYPE_FAST, 1112 NULL, 1113 sip_smc_handler 1114 ); 1115 1116 DECLARE_RT_SVC( 1117 socfpga_sip_svc_std, 1118 OEN_SIP_START, 1119 OEN_SIP_END, 1120 SMC_TYPE_YIELD, 1121 NULL, 1122 sip_smc_handler 1123 ); 1124