1 /* 2 * Copyright 2018-2022 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <arch.h> 10 #include <caam.h> 11 #include <cassert.h> 12 #include <cci.h> 13 #include <common/debug.h> 14 #include <dcfg.h> 15 #ifdef I2C_INIT 16 #include <i2c.h> 17 #endif 18 #include <lib/mmio.h> 19 #include <lib/xlat_tables/xlat_tables_v2.h> 20 #include <ls_interconnect.h> 21 #ifdef POLICY_FUSE_PROVISION 22 #include <nxp_gpio.h> 23 #endif 24 #if TRUSTED_BOARD_BOOT 25 #include <nxp_smmu.h> 26 #endif 27 #include <nxp_timer.h> 28 #include <plat_console.h> 29 #include <plat_gic.h> 30 #include <plat_tzc400.h> 31 #include <scfg.h> 32 #if defined(NXP_SFP_ENABLED) 33 #include <sfp.h> 34 #endif 35 36 #include <errata.h> 37 #include <ns_access.h> 38 #ifdef CONFIG_OCRAM_ECC_EN 39 #include <ocram.h> 40 #endif 41 #include <plat_common.h> 42 #include <platform_def.h> 43 #include <soc.h> 44 45 static dcfg_init_info_t dcfg_init_data = { 46 .g_nxp_dcfg_addr = NXP_DCFG_ADDR, 47 .nxp_sysclk_freq = NXP_SYSCLK_FREQ, 48 .nxp_ddrclk_freq = NXP_DDRCLK_FREQ, 49 .nxp_plat_clk_divider = NXP_PLATFORM_CLK_DIVIDER, 50 }; 51 52 /* Function to return the SoC SYS CLK */ 53 static unsigned int get_sys_clk(void) 54 { 55 return NXP_SYSCLK_FREQ; 56 } 57 58 /* 59 * Function returns the base counter frequency 60 * after reading the first entry at CNTFID0 (0x20 offset). 61 * 62 * Function is used by: 63 * 1. ARM common code for PSCI management. 64 * 2. ARM Generic Timer init. 65 * 66 */ 67 unsigned int plat_get_syscnt_freq2(void) 68 { 69 unsigned int counter_base_frequency; 70 71 counter_base_frequency = get_sys_clk() / 4; 72 73 return counter_base_frequency; 74 } 75 76 #ifdef IMAGE_BL2 77 /* Functions for BL2 */ 78 79 static struct soc_type soc_list[] = { 80 SOC_ENTRY(LS1046A, LS1046A, 1, 4), 81 SOC_ENTRY(LS1046AE, LS1046AE, 1, 4), 82 SOC_ENTRY(LS1026A, LS1026A, 1, 2), 83 SOC_ENTRY(LS1026AE, LS1026AE, 1, 2), 84 }; 85 86 #ifdef POLICY_FUSE_PROVISION 87 static gpio_init_info_t gpio_init_data = { 88 .gpio1_base_addr = NXP_GPIO1_ADDR, 89 .gpio2_base_addr = NXP_GPIO2_ADDR, 90 .gpio3_base_addr = NXP_GPIO3_ADDR, 91 .gpio4_base_addr = NXP_GPIO4_ADDR, 92 }; 93 #endif 94 95 /* 96 * Function to set the base counter frequency at 97 * the first entry of the Frequency Mode Table, 98 * at CNTFID0 (0x20 offset). 99 * 100 * Set the value of the pirmary core register cntfrq_el0. 101 */ 102 static void set_base_freq_CNTFID0(void) 103 { 104 /* 105 * Below register specifies the base frequency of the system counter. 106 * As per NXP Board Manuals: 107 * The system counter always works with SYS_REF_CLK/4 frequency clock. 108 */ 109 unsigned int counter_base_frequency = get_sys_clk() / 4; 110 111 /* Setting the frequency in the Frequency modes table. 112 * 113 * Note: The value for ls1046ardb board at this offset 114 * is not RW as stated. This offset have the 115 * fixed value of 100000400 Hz. 116 * 117 * The below code line has no effect. 118 * Keeping it for other platforms where it has effect. 119 */ 120 mmio_write_32(NXP_TIMER_ADDR + CNTFID_OFF, counter_base_frequency); 121 122 write_cntfrq_el0(counter_base_frequency); 123 } 124 125 void soc_preload_setup(void) 126 { 127 128 } 129 130 /* 131 * This function implements soc specific erratas 132 * This is called before DDR is initialized or MMU is enabled 133 */ 134 void soc_early_init(void) 135 { 136 uint8_t num_clusters, cores_per_cluster; 137 dram_regions_info_t *dram_regions_info = get_dram_regions_info(); 138 139 #ifdef CONFIG_OCRAM_ECC_EN 140 ocram_init(NXP_OCRAM_ADDR, NXP_OCRAM_SIZE); 141 #endif 142 dcfg_init(&dcfg_init_data); 143 #ifdef POLICY_FUSE_PROVISION 144 gpio_init(&gpio_init_data); 145 sec_init(NXP_CAAM_ADDR); 146 #endif 147 #if LOG_LEVEL > 0 148 /* Initialize the console to provide early debug support */ 149 150 plat_console_init(NXP_CONSOLE_ADDR, 151 NXP_UART_CLK_DIVIDER, NXP_CONSOLE_BAUDRATE); 152 #endif 153 set_base_freq_CNTFID0(); 154 155 /* Enable snooping on SEC read and write transactions */ 156 scfg_setbits32((void *)(NXP_SCFG_ADDR + SCFG_SNPCNFGCR_OFFSET), 157 SCFG_SNPCNFGCR_SECRDSNP | SCFG_SNPCNFGCR_SECWRSNP); 158 159 /* 160 * Initialize Interconnect for this cluster during cold boot. 161 * No need for locks as no other CPU is active. 162 */ 163 cci_init(NXP_CCI_ADDR, cci_map, ARRAY_SIZE(cci_map)); 164 165 /* 166 * Enable Interconnect coherency for the primary CPU's cluster. 167 */ 168 get_cluster_info(soc_list, ARRAY_SIZE(soc_list), &num_clusters, &cores_per_cluster); 169 plat_ls_interconnect_enter_coherency(num_clusters); 170 171 #if TRUSTED_BOARD_BOOT 172 uint32_t mode; 173 174 sfp_init(NXP_SFP_ADDR); 175 /* 176 * For secure boot disable SMMU. 177 * Later when platform security policy comes in picture, 178 * this might get modified based on the policy 179 */ 180 if (check_boot_mode_secure(&mode) == true) { 181 bypass_smmu(NXP_SMMU_ADDR); 182 } 183 184 /* 185 * For Mbedtls currently crypto is not supported via CAAM 186 * enable it when that support is there. In tbbr.mk 187 * the CAAM_INTEG is set as 0. 188 */ 189 #ifndef MBEDTLS_X509 190 /* Initialize the crypto accelerator if enabled */ 191 if (is_sec_enabled() == false) { 192 INFO("SEC is disabled.\n"); 193 } else { 194 sec_init(NXP_CAAM_ADDR); 195 } 196 #endif 197 #elif defined(POLICY_FUSE_PROVISION) 198 gpio_init(&gpio_init_data); 199 sfp_init(NXP_SFP_ADDR); 200 sec_init(NXP_CAAM_ADDR); 201 #endif 202 203 soc_errata(); 204 205 /* Initialize system level generic timer for Layerscape Socs. */ 206 delay_timer_init(NXP_TIMER_ADDR); 207 208 #ifdef DDR_INIT 209 i2c_init(NXP_I2C_ADDR); 210 dram_regions_info->total_dram_size = init_ddr(); 211 #endif 212 } 213 214 void soc_bl2_prepare_exit(void) 215 { 216 #if defined(NXP_SFP_ENABLED) && defined(DISABLE_FUSE_WRITE) 217 set_sfp_wr_disable(); 218 #endif 219 } 220 221 /* This function returns the boot device based on RCW_SRC */ 222 enum boot_device get_boot_dev(void) 223 { 224 enum boot_device src = BOOT_DEVICE_NONE; 225 uint32_t porsr1; 226 uint32_t rcw_src, val; 227 228 porsr1 = read_reg_porsr1(); 229 230 rcw_src = (porsr1 & PORSR1_RCW_MASK) >> PORSR1_RCW_SHIFT; 231 232 val = rcw_src & RCW_SRC_NAND_MASK; 233 234 if (val == RCW_SRC_NAND_VAL) { 235 val = rcw_src & NAND_RESERVED_MASK; 236 if ((val != NAND_RESERVED_1) && (val != NAND_RESERVED_2)) { 237 src = BOOT_DEVICE_IFC_NAND; 238 INFO("RCW BOOT SRC is IFC NAND\n"); 239 } 240 } else { 241 /* RCW SRC NOR */ 242 val = rcw_src & RCW_SRC_NOR_MASK; 243 if (val == NOR_8B_VAL || val == NOR_16B_VAL) { 244 src = BOOT_DEVICE_IFC_NOR; 245 INFO("RCW BOOT SRC is IFC NOR\n"); 246 } else { 247 switch (rcw_src) { 248 case QSPI_VAL1: 249 case QSPI_VAL2: 250 src = BOOT_DEVICE_QSPI; 251 INFO("RCW BOOT SRC is QSPI\n"); 252 break; 253 case SD_VAL: 254 src = BOOT_DEVICE_EMMC; 255 INFO("RCW BOOT SRC is SD/EMMC\n"); 256 break; 257 default: 258 src = BOOT_DEVICE_NONE; 259 } 260 } 261 } 262 263 return src; 264 } 265 266 /* This function sets up access permissions on memory regions */ 267 void soc_mem_access(void) 268 { 269 dram_regions_info_t *info_dram_regions = get_dram_regions_info(); 270 struct tzc400_reg tzc400_reg_list[MAX_NUM_TZC_REGION]; 271 unsigned int dram_idx, index = 0U; 272 273 for (dram_idx = 0U; dram_idx < info_dram_regions->num_dram_regions; 274 dram_idx++) { 275 if (info_dram_regions->region[dram_idx].size == 0) { 276 ERROR("DDR init failure, or"); 277 ERROR("DRAM regions not populated correctly.\n"); 278 break; 279 } 280 281 index = populate_tzc400_reg_list(tzc400_reg_list, 282 dram_idx, index, 283 info_dram_regions->region[dram_idx].addr, 284 info_dram_regions->region[dram_idx].size, 285 NXP_SECURE_DRAM_SIZE, NXP_SP_SHRD_DRAM_SIZE); 286 } 287 288 mem_access_setup(NXP_TZC_ADDR, index, tzc400_reg_list); 289 } 290 291 #else /* IMAGE_BL2 */ 292 /* Functions for BL31 */ 293 294 const unsigned char _power_domain_tree_desc[] = {1, 1, 4}; 295 296 CASSERT(NUMBER_OF_CLUSTERS && NUMBER_OF_CLUSTERS <= 256, 297 assert_invalid_ls1046_cluster_count); 298 299 /* This function returns the SoC topology */ 300 const unsigned char *plat_get_power_domain_tree_desc(void) 301 { 302 return _power_domain_tree_desc; 303 } 304 305 /* 306 * This function returns the core count within the cluster corresponding to 307 * `mpidr`. 308 */ 309 unsigned int plat_ls_get_cluster_core_count(u_register_t mpidr) 310 { 311 return CORES_PER_CLUSTER; 312 } 313 314 void soc_early_platform_setup2(void) 315 { 316 dcfg_init(&dcfg_init_data); 317 /* Initialize system level generic timer for SoCs */ 318 delay_timer_init(NXP_TIMER_ADDR); 319 320 #if LOG_LEVEL > 0 321 /* Initialize the console to provide early debug support */ 322 plat_console_init(NXP_CONSOLE_ADDR, 323 NXP_UART_CLK_DIVIDER, NXP_CONSOLE_BAUDRATE); 324 #endif 325 } 326 327 void soc_platform_setup(void) 328 { 329 static uint32_t target_mask_array[PLATFORM_CORE_COUNT]; 330 /* 331 * On a GICv2 system, the Group 1 secure interrupts are treated 332 * as Group 0 interrupts. 333 */ 334 static interrupt_prop_t ls_interrupt_props[] = { 335 PLAT_LS_G1S_IRQ_PROPS(GICV2_INTR_GROUP0), 336 PLAT_LS_G0_IRQ_PROPS(GICV2_INTR_GROUP0) 337 }; 338 339 plat_ls_gic_driver_init( 340 #if (TEST_BL31) 341 /* Defect in simulator - GIC base addresses (4Kb aligned) */ 342 NXP_GICD_4K_ADDR, 343 NXP_GICC_4K_ADDR, 344 #else 345 NXP_GICD_64K_ADDR, 346 NXP_GICC_64K_ADDR, 347 #endif 348 PLATFORM_CORE_COUNT, 349 ls_interrupt_props, 350 ARRAY_SIZE(ls_interrupt_props), 351 target_mask_array); 352 353 plat_ls_gic_init(); 354 enable_init_timer(); 355 } 356 357 /* This function initializes the soc from the BL31 module */ 358 void soc_init(void) 359 { 360 /* low-level init of the soc */ 361 soc_init_lowlevel(); 362 _init_global_data(); 363 soc_init_percpu(); 364 _initialize_psci(); 365 366 /* 367 * Initialize the interconnect during cold boot. 368 * No need for locks as no other CPU is active. 369 */ 370 cci_init(NXP_CCI_ADDR, cci_map, ARRAY_SIZE(cci_map)); 371 372 /* 373 * Enable coherency in interconnect for the primary CPU's cluster. 374 * Earlier bootloader stages might already do this but we can't 375 * assume so. No harm in executing this code twice. 376 */ 377 cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr())); 378 379 /* Init CSU to enable non-secure access to peripherals */ 380 enable_layerscape_ns_access(ns_dev, ARRAY_SIZE(ns_dev), NXP_CSU_ADDR); 381 382 /* Initialize the crypto accelerator if enabled */ 383 if (is_sec_enabled() == false) { 384 INFO("SEC is disabled.\n"); 385 } else { 386 sec_init(NXP_CAAM_ADDR); 387 } 388 } 389 390 void soc_runtime_setup(void) 391 { 392 393 } 394 395 #endif /* IMAGE_BL2 */ 396