1 /* 2 * Copyright 2020-2025 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef DDR_UTILS_H 8 #define DDR_UTILS_H 9 10 #include <stdbool.h> 11 #include <stdlib.h> 12 13 #include <lib/mmio.h> 14 15 #include <platform_def.h> 16 17 /* Possible errors */ 18 #define NO_ERR 0x00000000U 19 #define TIMEOUT_ERR 0x00000002U 20 #define TRAINING_FAILED 0x00000003U 21 #define BITFIELD_EXCEEDED 0x00000004U 22 #define DEASSERT_FAILED 0x00000005U 23 24 /* DDRC related */ 25 #define DDRC_BASE 0x403C0000U 26 #define OFFSET_DDRC_SWCTL 0x320U 27 #define OFFSET_DDRC_DFIMISC 0x1B0U 28 #define OFFSET_DDRC_PWRCTL 0x30U 29 #define OFFSET_DDRC_SWSTAT 0x324U 30 #define OFFSET_DDRC_DFITMG0 0x190U 31 #define OFFSET_DDRC_DBG1 0x304U 32 33 /* DDRC masks and values */ 34 #define MSTR_LPDDR4_VAL 0x20U 35 #define SWSTAT_SW_DONE 1U 36 #define SWSTAT_SW_NOT_DONE 0U 37 #define SWCTL_SWDONE_DONE 0x1U 38 #define SWCTL_SWDONE_ENABLE 0x0U 39 #define SWSTAT_SWDONE_ACK_MASK GENMASK_32(1U, 0U) 40 41 #define MSTR_DRAM_MASK GENMASK_32(5U, 0U) 42 #define MSTR_ACT_RANKS_MASK GENMASK_32(25U, 24U) 43 #define MSTR_DUAL_RANK_VAL 0x3000000U 44 #define MSTR_BURST_RDWR_POS 16 45 #define MSTR_BURST_RDWR_MASK 0xFU 46 #define DFITMG0_PHY_CLK_POS 15 47 #define DFITMG0_PHY_CLK_MASK 0x1U 48 49 #define DDR_SS_AXI_PARITY_ENABLE_MASK GENMASK_32(12U, 4U) 50 #define DDR_SS_AXI_PARITY_TYPE_MASK GENMASK_32(24U, 16U) 51 #define DDR_SS_DFI_1_ENABLED 0x1U 52 #define DBG1_DISABLE_DE_QUEUEING 0x0U 53 #define RFSHCTL3_DISABLE_AUTO_REFRESH 0x1U 54 55 #define PWRCTL_POWER_DOWN_ENABLE_MASK BIT_32(1) 56 #define PWRCTL_SELF_REFRESH_ENABLE_MASK BIT_32(0) 57 #define PWRCTL_EN_DFI_DRAM_CLOCK_DIS_MASK BIT_32(3) 58 #define DFIMISC_DFI_INIT_COMPLETE_EN_MASK BIT_32(0) 59 60 #define TRAINING_OK_MSG 0x07U 61 #define TRAINING_FAILED_MSG 0xFFU 62 63 #define APBONLY_DCTWRITEPROT_ACK_EN 0U 64 #define APBONLY_DCTWRITEPROT_ACK_DIS 1U 65 66 /* PHY related */ 67 #define DDR_PHYA_APBONLY_UCTSHADOWREGS 0x40380404U 68 #define UCT_WRITE_PROT_SHADOW_MASK 0x1U 69 #define DDR_PHYA_DCTWRITEPROT 0x4038040CU 70 #define DDR_PHYA_APBONLY_UCTWRITEONLYSHADOW 0x40380410U 71 #define OFFSET_DDRC_RFSHCTL3 0x60U 72 #define UCT_WRITE_PROT_SHADOW_ACK 0x0U 73 #define TXDQDLY_COARSE 6U 74 #define DDRPHY_PIPE_DFI_MISC 1U 75 #define ARDPTR_INITVAL_ADDR 0x40381494U 76 77 #define CDD_CHA_RR_1_0 0x403B004CU 78 #define CDD_CHA_RR_0_1 0x403B004DU 79 #define CDD_CHA_RW_1_1 0x403B0050U 80 #define CDD_CHA_RW_1_0 0x403B0051U 81 #define CDD_CHA_RW_0_1 0x403B0054U 82 #define CDD_CHA_RW_0_0 0x403B0055U 83 #define CDD_CHA_WR_1_1 0x403B0058U 84 #define CDD_CHA_WR_1_0 0x403B0059U 85 #define CDD_CHA_WR_0_1 0x403B005CU 86 #define CDD_CHA_WR_0_0 0x403B005DU 87 #define CDD_CHA_WW_1_0 0x403B0060U 88 #define CDD_CHA_WW_0_1 0x403B0061U 89 90 #define CDD_CHB_RR_1_0 0x403B00B1U 91 #define CDD_CHB_RR_0_1 0x403B00B4U 92 #define CDD_CHB_RW_1_1 0x403B00B5U 93 #define CDD_CHB_RW_1_0 0x403B00B8U 94 #define CDD_CHB_RW_0_1 0x403B00B9U 95 #define CDD_CHB_RW_0_0 0x403B00BCU 96 #define CDD_CHB_WR_1_1 0x403B00BDU 97 #define CDD_CHB_WR_1_0 0x403B00C0U 98 #define CDD_CHB_WR_0_1 0x403B00C1U 99 #define CDD_CHB_WR_0_0 0x403B00C4U 100 #define CDD_CHB_WW_1_0 0x403B00C5U 101 #define CDD_CHB_WW_0_1 0x403B00C8U 102 103 #define CDD_CHA_RR_1_0_DDR3 0x403B0059U 104 #define CDD_CHA_RR_0_1_DDR3 0x403B0060U 105 #define CDD_CHA_RW_1_1_DDR3 0x403B008DU 106 #define CDD_CHA_RW_1_0_DDR3 0x403B0090U 107 #define CDD_CHA_RW_0_1_DDR3 0x403B0095U 108 #define CDD_CHA_RW_0_0_DDR3 0x403B0098U 109 #define CDD_CHA_WR_1_1_DDR3 0x403B00ADU 110 #define CDD_CHA_WR_1_0_DDR3 0x403B00B0U 111 #define CDD_CHA_WR_0_1_DDR3 0x403B00B5U 112 #define CDD_CHA_WR_0_0_DDR3 0x403B00B8U 113 #define CDD_CHA_WW_1_0_DDR3 0x403B0071U 114 #define CDD_CHA_WW_0_1_DDR3 0x403B0078U 115 116 #define DBYTE0_TXDQSDLYTG0_U0 0x40394B4CU 117 #define DBYTE0_TXDQSDLYTG0_U1 0x40394B50U 118 #define DBYTE1_TXDQSDLYTG0_U0 0x40396B4CU 119 #define DBYTE1_TXDQSDLYTG0_U1 0x40396B50U 120 #define DBYTE2_TXDQSDLYTG0_U0 0x40398B4CU 121 #define DBYTE2_TXDQSDLYTG0_U1 0x40398B50U 122 #define DBYTE3_TXDQSDLYTG0_U0 0x4039AB4CU 123 #define DBYTE3_TXDQSDLYTG0_U1 0x4039AB50U 124 125 #define DBYTE0_TXDQSDLYTG1_U0 0x40394B6CU 126 #define DBYTE0_TXDQSDLYTG1_U1 0x40394B70U 127 #define DBYTE1_TXDQSDLYTG1_U0 0x40396B6CU 128 #define DBYTE1_TXDQSDLYTG1_U1 0x40396B70U 129 #define DBYTE2_TXDQSDLYTG1_U0 0x40398B6CU 130 #define DBYTE2_TXDQSDLYTG1_U1 0x40398B70U 131 #define DBYTE3_TXDQSDLYTG1_U0 0x4039AB6CU 132 #define DBYTE3_TXDQSDLYTG1_U1 0x4039AB70U 133 134 #define VREF_CA_A0 0x403B0095U 135 #define VREF_CA_A1 0x403B0098U 136 #define VREF_CA_B0 0x403B00FCU 137 #define VREF_CA_B1 0x403B00FDU 138 139 #define VREF_DQ_A0 0x403B0099U 140 #define VREF_DQ_A1 0x403B009CU 141 #define VREF_DQ_B0 0x403B0100U 142 #define VREF_DQ_B1 0x403B0101U 143 144 /* DDR Subsystem */ 145 #define DDR_SS_REG 0x403D0000U 146 147 /* Default timeout for DDR PHY operations */ 148 #define DEFAULT_TIMEOUT_US 1000000U 149 150 struct cdd_type { 151 uint8_t rr; 152 uint8_t rw; 153 uint8_t wr; 154 uint8_t ww; 155 }; 156 157 struct space_timing_params { 158 struct cdd_type cdd; 159 uint8_t vref_ca; 160 uint8_t vref_dq; 161 uint16_t tphy_wrdata_delay; 162 }; 163 164 /* Wait until firmware finishes execution and return training result */ 165 uint32_t wait_firmware_execution(void); 166 167 /* Set default AXI parity. */ 168 uint32_t set_axi_parity(void); 169 170 /* Modify bitfield value with delta, given bitfield position and mask */ 171 bool update_bf(uint32_t *v, uint8_t pos, uint32_t mask, int32_t delta); 172 173 /* Read Critical Delay Differences from message block and store max values */ 174 void read_cdds(void); 175 176 /* Read trained VrefCA from message block and store average value */ 177 void read_vref_ca(void); 178 179 /* Read trained VrefDQ from message block and store average value */ 180 void read_vref_dq(void); 181 182 /* Calculate DFITMG1.dfi_t_wrdata_delay */ 183 void compute_tphy_wrdata_delay(void); 184 185 #endif /* DDR_UTILS_H */ 186