1# 2# Copyright (c) 2016-2022, Arm Limited. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7# Default, static values for build variables, listed in alphabetic order. 8# Dependencies between build options, if any, are handled in the top-level 9# Makefile, after this file is included. This ensures that the former is better 10# poised to handle dependencies, as all build variables would have a default 11# value by then. 12 13# Use T32 by default 14AARCH32_INSTRUCTION_SET := T32 15 16# The AArch32 Secure Payload to be built as BL32 image 17AARCH32_SP := none 18 19# The Target build architecture. Supported values are: aarch64, aarch32. 20ARCH := aarch64 21 22# ARM Architecture feature modifiers: none by default 23ARM_ARCH_FEATURE := none 24 25# ARM Architecture major and minor versions: 8.0 by default. 26ARM_ARCH_MAJOR := 8 27ARM_ARCH_MINOR := 0 28 29# Base commit to perform code check on 30BASE_COMMIT := origin/master 31 32# Execute BL2 at EL3 33BL2_AT_EL3 := 0 34 35# Only use SP packages if SP layout JSON is defined 36BL2_ENABLE_SP_LOAD := 0 37 38# BL2 image is stored in XIP memory, for now, this option is only supported 39# when BL2_AT_EL3 is 1. 40BL2_IN_XIP_MEM := 0 41 42# Do dcache invalidate upon BL2 entry at EL3 43BL2_INV_DCACHE := 1 44 45# Select the branch protection features to use. 46BRANCH_PROTECTION := 0 47 48# By default, consider that the platform may release several CPUs out of reset. 49# The platform Makefile is free to override this value. 50COLD_BOOT_SINGLE_CPU := 0 51 52# Flag to compile in coreboot support code. Exclude by default. The coreboot 53# Makefile system will set this when compiling TF as part of a coreboot image. 54COREBOOT := 0 55 56# For Chain of Trust 57CREATE_KEYS := 1 58 59# Build flag to include AArch32 registers in cpu context save and restore during 60# world switch. This flag must be set to 0 for AArch64-only platforms. 61CTX_INCLUDE_AARCH32_REGS := 1 62 63# Include FP registers in cpu context 64CTX_INCLUDE_FPREGS := 0 65 66# Include pointer authentication (ARMv8.3-PAuth) registers in cpu context. This 67# must be set to 1 if the platform wants to use this feature in the Secure 68# world. It is not needed to use it in the Non-secure world. 69CTX_INCLUDE_PAUTH_REGS := 0 70 71# Include Nested virtualization control (Armv8.4-NV) registers in cpu context. 72# This must be set to 1 if architecture implements Nested Virtualization 73# Extension and platform wants to use this feature in the Secure world 74CTX_INCLUDE_NEVE_REGS := 0 75 76# Debug build 77DEBUG := 0 78 79# By default disable authenticated decryption support. 80DECRYPTION_SUPPORT := none 81 82# Build platform 83DEFAULT_PLAT := fvp 84 85# Disable the generation of the binary image (ELF only). 86DISABLE_BIN_GENERATION := 0 87 88# Disable MTPMU if FEAT_MTPMU is supported. Default is 0 to keep backwards 89# compatibility. 90DISABLE_MTPMU := 0 91 92# Enable capability to disable authentication dynamically. Only meant for 93# development platforms. 94DYN_DISABLE_AUTH := 0 95 96# Build option to enable MPAM for lower ELs 97ENABLE_MPAM_FOR_LOWER_ELS := 0 98 99# Enable the Maximum Power Mitigation Mechanism on supporting cores. 100ENABLE_MPMM := 0 101 102# Enable MPMM configuration via FCONF. 103ENABLE_MPMM_FCONF := 0 104 105# Flag to Enable Position Independant support (PIE) 106ENABLE_PIE := 0 107 108# Flag to enable Performance Measurement Framework 109ENABLE_PMF := 0 110 111# Flag to enable PSCI STATs functionality 112ENABLE_PSCI_STAT := 0 113 114# Flag to enable Realm Management Extension (FEAT_RME) 115ENABLE_RME := 0 116 117# Flag to enable runtime instrumentation using PMF 118ENABLE_RUNTIME_INSTRUMENTATION := 0 119 120# Flag to enable stack corruption protection 121ENABLE_STACK_PROTECTOR := 0 122 123# Flag to enable exception handling in EL3 124EL3_EXCEPTION_HANDLING := 0 125 126# Flag to enable Branch Target Identification. 127# Internal flag not meant for direct setting. 128# Use BRANCH_PROTECTION to enable BTI. 129ENABLE_BTI := 0 130 131# Flag to enable Pointer Authentication. 132# Internal flag not meant for direct setting. 133# Use BRANCH_PROTECTION to enable PAUTH. 134ENABLE_PAUTH := 0 135 136# Flag to enable access to the HCRX_EL2 register by setting SCR_EL3.HXEn. 137ENABLE_FEAT_HCX := 0 138 139# Flag to enable access to the HAFGRTR_EL2 register 140ENABLE_FEAT_AMUv1 := 0 141 142# Flag to enable access to the HDFGRTR_EL2 register 143ENABLE_FEAT_FGT := 0 144 145# Flag to enable access to the CNTPOFF_EL2 register 146ENABLE_FEAT_ECV := 0 147 148# Flag to enable use of the DIT feature. 149ENABLE_FEAT_DIT := 0 150 151# By default BL31 encryption disabled 152ENCRYPT_BL31 := 0 153 154# By default BL32 encryption disabled 155ENCRYPT_BL32 := 0 156 157# Default dummy firmware encryption key 158ENC_KEY := 1234567890abcdef1234567890abcdef1234567890abcdef1234567890abcdef 159 160# Default dummy nonce for firmware encryption 161ENC_NONCE := 1234567890abcdef12345678 162 163# Build flag to treat usage of deprecated platform and framework APIs as error. 164ERROR_DEPRECATED := 0 165 166# Fault injection support 167FAULT_INJECTION_SUPPORT := 0 168 169# Byte alignment that each component in FIP is aligned to 170FIP_ALIGN := 0 171 172# Default FIP file name 173FIP_NAME := fip.bin 174 175# Default FWU_FIP file name 176FWU_FIP_NAME := fwu_fip.bin 177 178# By default firmware encryption with SSK 179FW_ENC_STATUS := 0 180 181# For Chain of Trust 182GENERATE_COT := 0 183 184# Hint platform interrupt control layer that Group 0 interrupts are for EL3. By 185# default, they are for Secure EL1. 186GICV2_G0_FOR_EL3 := 0 187 188# Route External Aborts to EL3. Disabled by default; External Aborts are handled 189# by lower ELs. 190HANDLE_EA_EL3_FIRST := 0 191 192# Secure hash algorithm flag, accepts 3 values: sha256, sha384 and sha512. 193# The default value is sha256. 194HASH_ALG := sha256 195 196# Whether system coherency is managed in hardware, without explicit software 197# operations. 198HW_ASSISTED_COHERENCY := 0 199 200# Set the default algorithm for the generation of Trusted Board Boot keys 201KEY_ALG := rsa 202 203# Set the default key size in case KEY_ALG is rsa 204ifeq ($(KEY_ALG),rsa) 205KEY_SIZE := 2048 206endif 207 208# Option to build TF with Measured Boot support 209MEASURED_BOOT := 0 210 211# NS timer register save and restore 212NS_TIMER_SWITCH := 0 213 214# Include lib/libc in the final image 215OVERRIDE_LIBC := 0 216 217# Build PL011 UART driver in minimal generic UART mode 218PL011_GENERIC_UART := 0 219 220# By default, consider that the platform's reset address is not programmable. 221# The platform Makefile is free to override this value. 222PROGRAMMABLE_RESET_ADDRESS := 0 223 224# Flag used to choose the power state format: Extended State-ID or Original 225PSCI_EXTENDED_STATE_ID := 0 226 227# Enable RAS support 228RAS_EXTENSION := 0 229 230# By default, BL1 acts as the reset handler, not BL31 231RESET_TO_BL31 := 0 232 233# For Chain of Trust 234SAVE_KEYS := 0 235 236# Software Delegated Exception support 237SDEI_SUPPORT := 0 238 239# True Random Number firmware Interface 240TRNG_SUPPORT := 0 241 242# SMCCC PCI support 243SMC_PCI_SUPPORT := 0 244 245# Whether code and read-only data should be put on separate memory pages. The 246# platform Makefile is free to override this value. 247SEPARATE_CODE_AND_RODATA := 0 248 249# Put NOBITS sections (.bss, stacks, page tables, and coherent memory) in a 250# separate memory region, which may be discontiguous from the rest of BL31. 251SEPARATE_NOBITS_REGION := 0 252 253# Put BL2 NOLOAD sections (.bss, stacks, page tables) in a separate memory 254# region, platform Makefile is free to override this value. 255SEPARATE_BL2_NOLOAD_REGION := 0 256 257# If the BL31 image initialisation code is recalimed after use for the secondary 258# cores stack 259RECLAIM_INIT_CODE := 0 260 261# SPD choice 262SPD := none 263 264# Enable the Management Mode (MM)-based Secure Partition Manager implementation 265SPM_MM := 0 266 267# Use SPM at S-EL2 as a default config for SPMD 268SPMD_SPM_AT_SEL2 := 1 269 270# Flag to introduce an infinite loop in BL1 just before it exits into the next 271# image. This is meant to help debugging the post-BL2 phase. 272SPIN_ON_BL1_EXIT := 0 273 274# Flags to build TF with Trusted Boot support 275TRUSTED_BOARD_BOOT := 0 276 277# Build option to choose whether Trusted Firmware uses Coherent memory or not. 278USE_COHERENT_MEM := 1 279 280# Build option to add debugfs support 281USE_DEBUGFS := 0 282 283# Build option to fconf based io 284ARM_IO_IN_DTB := 0 285 286# Build option to support SDEI through fconf 287SDEI_IN_FCONF := 0 288 289# Build option to support Secure Interrupt descriptors through fconf 290SEC_INT_DESC_IN_FCONF := 0 291 292# Build option to choose whether Trusted Firmware uses library at ROM 293USE_ROMLIB := 0 294 295# Build option to choose whether the xlat tables of BL images can be read-only. 296# Note that this only serves as a higher level option to PLAT_RO_XLAT_TABLES, 297# which is the per BL-image option that actually enables the read-only tables 298# API. The reason for having this additional option is to have a common high 299# level makefile where we can check for incompatible features/build options. 300ALLOW_RO_XLAT_TABLES := 0 301 302# Chain of trust. 303COT := tbbr 304 305# Use tbbr_oid.h instead of platform_oid.h 306USE_TBBR_DEFS := 1 307 308# Build verbosity 309V := 0 310 311# Whether to enable D-Cache early during warm boot. This is usually 312# applicable for platforms wherein interconnect programming is not 313# required to enable cache coherency after warm reset (eg: single cluster 314# platforms). 315WARMBOOT_ENABLE_DCACHE_EARLY := 0 316 317# Build option to enable/disable the Statistical Profiling Extensions 318ENABLE_SPE_FOR_LOWER_ELS := 1 319 320# SPE is only supported on AArch64 so disable it on AArch32. 321ifeq (${ARCH},aarch32) 322 override ENABLE_SPE_FOR_LOWER_ELS := 0 323endif 324 325# Include Memory Tagging Extension registers in cpu context. This must be set 326# to 1 if the platform wants to use this feature in the Secure world and MTE is 327# enabled at ELX. 328CTX_INCLUDE_MTE_REGS := 0 329 330ENABLE_AMU := 0 331ENABLE_AMU_AUXILIARY_COUNTERS := 0 332ENABLE_AMU_FCONF := 0 333AMU_RESTRICT_COUNTERS := 0 334 335# Enable SVE for non-secure world by default 336ENABLE_SVE_FOR_NS := 1 337# SVE is only supported on AArch64 so disable it on AArch32. 338ifeq (${ARCH},aarch32) 339 override ENABLE_SVE_FOR_NS := 0 340endif 341ENABLE_SVE_FOR_SWD := 0 342 343# SME defaults to disabled 344ENABLE_SME_FOR_NS := 0 345ENABLE_SME_FOR_SWD := 0 346 347# If SME is enabled then force SVE off 348ifeq (${ENABLE_SME_FOR_NS},1) 349 override ENABLE_SVE_FOR_NS := 0 350 override ENABLE_SVE_FOR_SWD := 0 351endif 352 353SANITIZE_UB := off 354 355# For ARMv8.1 (AArch64) platforms, enabling this option selects the spinlock 356# implementation variant using the ARMv8.1-LSE compare-and-swap instruction. 357# Default: disabled 358USE_SPINLOCK_CAS := 0 359 360# Enable Link Time Optimization 361ENABLE_LTO := 0 362 363# Build flag to include EL2 registers in cpu context save and restore during 364# S-EL2 firmware entry/exit. This flag is to be used with SPD=spmd option. 365# Default is 0. 366CTX_INCLUDE_EL2_REGS := 0 367 368# Enable Memory tag extension which is supported for architecture greater 369# than Armv8.5-A 370# By default it is set to "no" 371SUPPORT_STACK_MEMTAG := no 372 373# Select workaround for AT speculative behaviour. 374ERRATA_SPECULATIVE_AT := 0 375 376# Trap RAS error record access from lower EL 377RAS_TRAP_LOWER_EL_ERR_ACCESS := 0 378 379# Build option to create cot descriptors using fconf 380COT_DESC_IN_DTB := 0 381 382# Build option to provide openssl directory path 383OPENSSL_DIR := /usr 384 385# Build option to use the SP804 timer instead of the generic one 386USE_SP804_TIMER := 0 387 388# Build option to define number of firmware banks, used in firmware update 389# metadata structure. 390NR_OF_FW_BANKS := 2 391 392# Build option to define number of images in firmware bank, used in firmware 393# update metadata structure. 394NR_OF_IMAGES_IN_FW_BANK := 1 395 396# Disable Firmware update support by default 397PSA_FWU_SUPPORT := 0 398 399# By default, disable access of trace buffer control registers from NS 400# lower ELs i.e. NS-EL2, or NS-EL1 if NS-EL2 implemented but unused 401# if FEAT_TRBE is implemented. 402# Note FEAT_TRBE is only supported on AArch64 - therefore do not enable in 403# AArch32. 404ifneq (${ARCH},aarch32) 405 ENABLE_TRBE_FOR_NS := 0 406else 407 override ENABLE_TRBE_FOR_NS := 0 408endif 409 410# By default, disable access of trace system registers from NS lower 411# ELs i.e. NS-EL2, or NS-EL1 if NS-EL2 implemented but unused if 412# system register trace is implemented. 413ENABLE_SYS_REG_TRACE_FOR_NS := 0 414 415# By default, disable trace filter control registers access to NS 416# lower ELs, i.e. NS-EL2, or NS-EL1 if NS-EL2 implemented but unused 417# if FEAT_TRF is implemented. 418ENABLE_TRF_FOR_NS := 0 419