1 /* 2 * Copyright (c) 2018-2022, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <plat/arm/board/common/v2m_def.h> 11 #include <plat/arm/common/arm_def.h> 12 #include <plat/arm/css/common/css_def.h> 13 14 /* UART related constants */ 15 #define PLAT_ARM_BOOT_UART_BASE 0x2A400000 16 #define PLAT_ARM_BOOT_UART_CLK_IN_HZ 50000000 17 18 #define PLAT_ARM_RUN_UART_BASE 0x2A410000 19 #define PLAT_ARM_RUN_UART_CLK_IN_HZ 50000000 20 21 #define PLAT_ARM_SP_MIN_RUN_UART_BASE 0x2A410000 22 #define PLAT_ARM_SP_MIN_RUN_UART_CLK_IN_HZ 50000000 23 24 #define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_RUN_UART_BASE 25 #define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_RUN_UART_CLK_IN_HZ 26 27 #define PLAT_ARM_DRAM2_BASE ULL(0x8080000000) 28 #define PLAT_ARM_DRAM2_SIZE ULL(0xF80000000) 29 30 #define MAX_IO_DEVICES U(3) 31 #define MAX_IO_HANDLES U(4) 32 33 #define PLAT_ARM_FLASH_IMAGE_BASE 0x18200000 34 #define PLAT_ARM_FLASH_IMAGE_MAX_SIZE 0x00800000 35 36 #define PLAT_ARM_NVM_BASE 0x18200000 37 #define PLAT_ARM_NVM_SIZE 0x00800000 38 39 #if defined NS_BL1U_BASE 40 # undef NS_BL1U_BASE 41 # define NS_BL1U_BASE (PLAT_ARM_NVM_BASE + UL(0x00800000)) 42 #endif 43 44 /* Non-volatile counters */ 45 #define SOC_TRUSTED_NVCTR_BASE 0x7fe70000 46 #define TFW_NVCTR_BASE (SOC_TRUSTED_NVCTR_BASE) 47 #define TFW_NVCTR_SIZE U(4) 48 #define NTFW_CTR_BASE (SOC_TRUSTED_NVCTR_BASE + 0x0004) 49 #define NTFW_CTR_SIZE U(4) 50 51 /* N1SDP remote chip at 4 TB offset */ 52 #define PLAT_ARM_REMOTE_CHIP_OFFSET (ULL(1) << 42) 53 54 #define N1SDP_REMOTE_DRAM1_BASE ARM_DRAM1_BASE + \ 55 PLAT_ARM_REMOTE_CHIP_OFFSET 56 #define N1SDP_REMOTE_DRAM1_SIZE ARM_DRAM1_SIZE 57 58 #define N1SDP_REMOTE_DRAM2_BASE PLAT_ARM_DRAM2_BASE + \ 59 PLAT_ARM_REMOTE_CHIP_OFFSET 60 #define N1SDP_REMOTE_DRAM2_SIZE PLAT_ARM_DRAM2_SIZE 61 62 /* 63 * N1SDP platform supports RDIMMs with ECC capability. To use the ECC 64 * capability, the entire DDR memory space has to be zeroed out before 65 * enabling the ECC bits in DMC620. To access the complete DDR memory 66 * along with remote chip's DDR memory, which is at 4 TB offset, physical 67 * and virtual address space limits are extended to 43-bits. 68 */ 69 #ifdef __aarch64__ 70 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 43) 71 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 43) 72 #else 73 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 74 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 75 #endif 76 77 #if CSS_USE_SCMI_SDS_DRIVER 78 #define N1SDP_SCMI_PAYLOAD_BASE 0x45400000 79 #else 80 #define PLAT_CSS_SCP_COM_SHARED_MEM_BASE 0x45400000 81 #endif 82 83 /* 84 * Trusted SRAM in N1SDP is 512 KB but only the bottom 384 KB 85 * is used for trusted board boot flow. The top 128 KB is used 86 * to load AP-BL1 image. 87 */ 88 #define PLAT_ARM_TRUSTED_SRAM_SIZE 0x00060000 /* 384 KB */ 89 90 /* 91 * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size 92 * plus a little space for growth. 93 */ 94 #define PLAT_ARM_MAX_BL1_RW_SIZE 0xE000 95 96 /* 97 * PLAT_ARM_MAX_ROMLIB_RW_SIZE is define to use a full page 98 */ 99 100 #if USE_ROMLIB 101 # define PLAT_ARM_MAX_ROMLIB_RW_SIZE 0x1000 102 # define PLAT_ARM_MAX_ROMLIB_RO_SIZE 0xe000 103 #else 104 # define PLAT_ARM_MAX_ROMLIB_RW_SIZE U(0) 105 # define PLAT_ARM_MAX_ROMLIB_RO_SIZE U(0) 106 #endif 107 108 /* 109 * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a 110 * little space for growth. 111 */ 112 #if TRUSTED_BOARD_BOOT 113 # define PLAT_ARM_MAX_BL2_SIZE 0x20000 114 #else 115 # define PLAT_ARM_MAX_BL2_SIZE 0x14000 116 #endif 117 118 #define PLAT_ARM_MAX_BL31_SIZE UL(0x3B000) 119 120 /******************************************************************************* 121 * N1SDP topology related constants 122 ******************************************************************************/ 123 #define N1SDP_MAX_CPUS_PER_CLUSTER U(2) 124 #define PLAT_ARM_CLUSTER_COUNT U(2) 125 #define PLAT_N1SDP_CHIP_COUNT U(2) 126 #define N1SDP_MAX_CLUSTERS_PER_CHIP U(2) 127 #define N1SDP_MAX_PE_PER_CPU U(1) 128 129 #define PLATFORM_CORE_COUNT (PLAT_N1SDP_CHIP_COUNT * \ 130 PLAT_ARM_CLUSTER_COUNT * \ 131 N1SDP_MAX_CPUS_PER_CLUSTER * \ 132 N1SDP_MAX_PE_PER_CPU) 133 134 /* System power domain level */ 135 #define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL3 136 137 /* 138 * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the 139 * plat_arm_mmap array defined for each BL stage. 140 */ 141 142 #ifdef IMAGE_BL1 143 # define PLAT_ARM_MMAP_ENTRIES U(6) 144 # define MAX_XLAT_TABLES U(5) 145 #endif 146 147 #ifdef IMAGE_BL2 148 # define PLAT_ARM_MMAP_ENTRIES U(11) 149 # define MAX_XLAT_TABLES U(10) 150 #endif 151 152 #ifdef IMAGE_BL31 153 # define PLAT_ARM_MMAP_ENTRIES U(12) 154 # define MAX_XLAT_TABLES U(12) 155 #endif 156 157 /* 158 * Size of cacheable stacks 159 */ 160 #if defined(IMAGE_BL1) 161 # if TRUSTED_BOARD_BOOT 162 # define PLATFORM_STACK_SIZE 0x1000 163 # else 164 # define PLATFORM_STACK_SIZE 0x440 165 # endif 166 #elif defined(IMAGE_BL2) 167 # if TRUSTED_BOARD_BOOT 168 # define PLATFORM_STACK_SIZE 0x1000 169 # else 170 # define PLATFORM_STACK_SIZE 0x400 171 # endif 172 #elif defined(IMAGE_BL2U) 173 # define PLATFORM_STACK_SIZE 0x400 174 #elif defined(IMAGE_BL31) 175 # if SPM_MM 176 # define PLATFORM_STACK_SIZE 0x500 177 # else 178 # define PLATFORM_STACK_SIZE 0x400 179 # endif 180 #elif defined(IMAGE_BL32) 181 # define PLATFORM_STACK_SIZE 0x440 182 #endif 183 184 #define PLAT_ARM_NSTIMER_FRAME_ID 0 185 #define PLAT_CSS_MHU_BASE 0x45000000 186 #define PLAT_MAX_PWR_LVL 2 187 188 #define PLAT_ARM_G1S_IRQS ARM_G1S_IRQS, \ 189 CSS_IRQ_MHU 190 #define PLAT_ARM_G0_IRQS ARM_G0_IRQS 191 192 #define PLAT_ARM_G1S_IRQ_PROPS(grp) CSS_G1S_IRQ_PROPS(grp) 193 #define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp) 194 195 196 #define N1SDP_DEVICE_BASE ULL(0x08000000) 197 #define N1SDP_DEVICE_SIZE ULL(0x48000000) 198 #define N1SDP_REMOTE_DEVICE_BASE N1SDP_DEVICE_BASE + \ 199 PLAT_ARM_REMOTE_CHIP_OFFSET 200 #define N1SDP_REMOTE_DEVICE_SIZE N1SDP_DEVICE_SIZE 201 202 /* Real base is 0x0. Changed to load BL1 at this address */ 203 # define PLAT_ARM_TRUSTED_ROM_BASE 0x04060000 204 # define PLAT_ARM_TRUSTED_ROM_SIZE 0x00020000 /* 128KB */ 205 206 #define N1SDP_MAP_DEVICE MAP_REGION_FLAT( \ 207 N1SDP_DEVICE_BASE, \ 208 N1SDP_DEVICE_SIZE, \ 209 MT_DEVICE | MT_RW | MT_SECURE) 210 211 #define ARM_MAP_DRAM1 MAP_REGION_FLAT( \ 212 ARM_DRAM1_BASE, \ 213 ARM_DRAM1_SIZE, \ 214 MT_MEMORY | MT_RW | MT_NS) 215 216 #define N1SDP_MAP_REMOTE_DEVICE MAP_REGION_FLAT( \ 217 N1SDP_REMOTE_DEVICE_BASE, \ 218 N1SDP_REMOTE_DEVICE_SIZE, \ 219 MT_DEVICE | MT_RW | MT_SECURE) 220 221 #define N1SDP_MAP_REMOTE_DRAM1 MAP_REGION_FLAT( \ 222 N1SDP_REMOTE_DRAM1_BASE, \ 223 N1SDP_REMOTE_DRAM1_SIZE, \ 224 MT_MEMORY | MT_RW | MT_NS) 225 226 #define N1SDP_MAP_REMOTE_DRAM2 MAP_REGION_FLAT( \ 227 N1SDP_REMOTE_DRAM2_BASE, \ 228 N1SDP_REMOTE_DRAM2_SIZE, \ 229 MT_MEMORY | MT_RW | MT_NS) 230 231 /* GIC related constants */ 232 #define PLAT_ARM_GICD_BASE 0x30000000 233 #define PLAT_ARM_GICC_BASE 0x2C000000 234 #define PLAT_ARM_GICR_BASE 0x300C0000 235 236 /* Platform ID address */ 237 #define SSC_VERSION (SSC_REG_BASE + SSC_VERSION_OFFSET) 238 239 /* Secure Watchdog Constants */ 240 #define SBSA_SECURE_WDOG_BASE UL(0x2A480000) 241 #define SBSA_SECURE_WDOG_TIMEOUT UL(100) 242 243 /* Number of SCMI channels on the platform */ 244 #define PLAT_ARM_SCMI_CHANNEL_COUNT U(1) 245 246 #endif /* PLATFORM_DEF_H */ 247