1NXP SoCs - Overview 2===================== 3.. section-numbering:: 4 :suffix: . 5 6The QorIQ family of ARM based SoCs that are supported on TF-A are: 7 81. LX2160A 9 10- SoC Overview: 11 12The LX2160A multicore processor, the highest-performance member of the 13Layerscape family, combines FinFET process technology's low power and 14sixteen Arm® Cortex®-A72 cores with datapath acceleration optimized for 15L2/3 packet processing, together with security offload, robust traffic 16management and quality of service. 17 18Details about LX2160A can be found at `lx2160a`_. 19 20- LX2160ARDB Board: 21 22The LX2160A reference design board provides a comprehensive platform 23that enables design and evaluation of the LX2160A or LX2162A processors. It 24comes preloaded with a board support package (BSP) based on a standard Linux 25kernel. 26 27Board details can be fetched from the link: `lx2160ardb`_. 28 292. LS1028A 30 31- SoC Overview: 32 33The Layerscape LS1028A applications processor for industrial and 34automotive includes a time-sensitive networking (TSN) -enabled Ethernet 35switch and Ethernet controllers to support converged IT and OT networks. 36Two powerful 64-bit Arm®v8 cores support real-time processing for 37industrial control and virtual machines for edge computing in the IoT. 38The integrated GPU and LCD controller enable Human-Machine Interface 39(HMI) systems with next-generation interfaces. 40 41Details about LS1028A can be found at `ls1028a`_. 42 43- LS1028ARDB Board: 44 45The LS1028A reference design board (RDB) is a computing, evaluation, 46and development platform that supports industrial IoT applications, human 47machine interface solutions, and industrial networking. 48 49Details about LS1028A RDB board can be found at `ls1028ardb`_. 50 513. LS1043A 52 53- SoC Overview: 54 55The Layerscape LS1043A processor is NXP's first quad-core, 64-bit Arm®-based 56processor for embedded networking. The LS1023A (two core version) and the 57LS1043A (four core version) deliver greater than 10 Gbps of performance 58in a flexible I/O package supporting fanless designs. This SoC is a 59purpose-built solution for small-form-factor networking and industrial 60applications with BOM optimizations for economic low layer PCB, lower cost 61power supply and single clock design. The new 0.9V versions of the LS1043A 62and LS1023A deliver addition power savings for applications such as Wireless 63LAN and to Power over Ethernet systems. 64 65Details about LS1043A can be found at `ls1043a`_. 66 67- LS1043ARDB Board: 68 69The LS1043A reference design board (RDB) is a computing, evaluation, and 70development platform that supports the Layerscape LS1043A architecture 71processor. The LS1043A-RDB can help shorten your time to market by providing 72the following features: 73 74Memory subsystem: 75 * 2GByte DDR4 SDRAM (32bit bus) 76 * 128 Mbyte NOR flash single-chip memory 77 * 512 Mbyte NAND flash 78 * 16 Mbyte high-speed SPI flash 79 * SD connector to interface with the SD memory card 80 81Ethernet: 82 * XFI 10G port 83 * QSGMII with 4x 1G ports 84 * Two RGMII ports 85 86PCIe: 87 * PCIe2 (Lanes C) to mini-PCIe slot 88 * PCIe3 (Lanes D) to PCIe slot 89 90USB 3.0: two super speed USB 3.0 type A ports 91 92UART: supports two UARTs up to 115200 bps for console 93 94Details about LS1043A RDB board can be found at `ls1043ardb`_. 95 964. LS1046A 97 98- SoC Overview: 99 100The LS1046A is a cost-effective, power-efficient, and highly integrated 101system-on-chip (SoC) design that extends the reach of the NXP value-performance 102line of QorIQ communications processors. Featuring power-efficient 64-bit 103Arm Cortex-A72 cores with ECC-protected L1 and L2 cache memories for high 104reliability, running up to 1.8 GHz. 105 106Details about LS1043A can be found at `ls1046a`_. 107 108- LS1046ARDB Board: 109 110The LS1046A reference design board (RDB) is a high-performance computing, 111evaluation, and development platform that supports the Layerscape LS1046A 112architecture processor. The LS1046ARDB board supports the Layerscape LS1046A 113processor and is optimized to support the DDR4 memory and a full complement 114of high-speed SerDes ports. 115 116Details about LS1043A RDB board can be found at `ls1046ardb`_. 117 118- LS1046AFRWY Board: 119 120The LS1046A Freeway board (FRWY) is a high-performance computing, evaluation, 121and development platform that supports the LS1046A architecture processor 122capable of support more than 32,000 CoreMark performance. The FRWY-LS1046A 123board supports the LS1046A processor, onboard DDR4 memory, multiple Gigabit 124Ethernet, USB3.0 and M2_Type_E interfaces for Wi-Fi, FRWY-LS1046A-AC includes 125the Wi-Fi card. 126 127Details about LS1043A RDB board can be found at `ls1046afrwy`_. 128 129Table of supported boot-modes by each platform & platform that needs FIP-DDR: 130----------------------------------------------------------------------------- 131 132+---------------------+---------------------------------------------------------------------+-----------------+ 133| | BOOT_MODE | | 134| PLAT +-------+--------+-------+-------+-------+-------------+--------------+ fip_ddr_needed | 135| | sd | qspi | nor | nand | emmc | flexspi_nor | flexspi_nand | | 136+=====================+=======+========+=======+=======+=======+=============+==============+=================+ 137| lx2160ardb | yes | | | | yes | yes | | yes | 138+---------------------+-------+--------+-------+-------+-------+-------------+--------------+-----------------+ 139| ls1028ardb | yes | | | | yes | yes | | no | 140+---------------------+-------+--------+-------+-------+-------+-------------+--------------+-----------------+ 141| ls1043ardb | yes | | yes | yes | | | | no | 142+---------------------+-------+--------+-------+-------+-------+-------------+--------------+-----------------+ 143| ls1046ardb | yes | yes | | | yes | | | no | 144+---------------------+-------+--------+-------+-------+-------+-------------+--------------+-----------------+ 145| ls1046afrwy | yes | yes | | | | | | no | 146+---------------------+-------+--------+-------+-------+-------+-------------+--------------+-----------------+ 147 148 149Boot Sequence 150------------- 151:: 152 153+ Secure World | Normal World 154+ EL0 | 155+ | 156+ EL1 BL32(Tee OS) | kernel 157+ ^ | | ^ 158+ | | | | 159+ EL2 | | | BL33(u-boot) 160+ | | | ^ 161+ | v | / 162+ EL3 BootROM --> BL2 --> BL31 ---------------/ 163+ 164 165Boot Sequence with FIP-DDR 166-------------------------- 167:: 168 169+ Secure World | Normal World 170+ EL0 | 171+ | 172+ EL1 fip-ddr BL32(Tee OS) | kernel 173+ ^ | ^ | | ^ 174+ | | | | | | 175+ EL2 | | | | | BL33(u-boot) 176+ | | | | | ^ 177+ | v | v | / 178+ EL3 BootROM --> BL2 -----> BL31 ---------------/ 179+ 180 181DDR Memory Layout 182-------------------------- 183 184NXP Platforms divide DRAM into banks: 185 186- DRAM0 Bank: Maximum size of this bank is fixed to 2GB, DRAM0 size is defined in platform_def.h if it is less than 2GB. 187 188- DRAM1 ~ DRAMn Bank: Greater than 2GB belongs to DRAM1 and following banks, and size of DRAMn Bank varies for one platform to others. 189 190The following diagram is default DRAM0 memory layout in which secure memory is at top of DRAM0. 191 192:: 193 194 high +---------------------------------------------+ 195 | | 196 | Secure EL1 Payload Shared Memory (2 MB) | 197 | | 198 +---------------------------------------------+ 199 | | 200 | Secure Memory (64 MB) | 201 | | 202 +---------------------------------------------+ 203 | | 204 | Non Secure Memory | 205 | | 206 low +---------------------------------------------+ 207 208How to build 209============= 210 211Code Locations 212-------------- 213 214- OP-TEE: 215 `link <https://source.codeaurora.org/external/qoriq/qoriq-components/optee_os>`__ 216 217- U-Boot: 218 `link <https://source.codeaurora.org/external/qoriq/qoriq-components/u-boot>`__ 219 220- RCW: 221 `link <https://source.codeaurora.org/external/qoriq/qoriq-components/rcw>`__ 222 223- ddr-phy-binary: Required by platforms that need fip-ddr. 224 `link <https:://github.com/NXP/ddr-phy-binary>`__ 225 226- cst: Required for TBBR. 227 `link <https:://source.codeaurora.org/external/qoriq/qoriq-components/cst>`__ 228 229Build Procedure 230--------------- 231 232- Fetch all the above repositories into local host. 233 234- Prepare AARCH64 toolchain and set the environment variable "CROSS_COMPILE". 235 236 .. code:: shell 237 238 export CROSS_COMPILE=.../bin/aarch64-linux-gnu- 239 240- Build RCW. Refer README from the respective cloned folder for more details. 241 242- Build u-boot and OPTee firstly, and get binary images: u-boot.bin and tee.bin. 243 For u-boot you can use the <platform>_tfa_defconfig for build. 244 245- Copy/clone the repo "ddr-phy-binary" to the tfa directory for platform needing ddr-fip. 246 247- Below are the steps to build TF-A images for the supported platforms. 248 249Compilation steps without BL32 250~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 251 252BUILD BL2: 253 254-To compile 255 .. code:: shell 256 257 make PLAT=$PLAT \ 258 BOOT_MODE=<platform_supported_boot_mode> \ 259 RCW=$RCW_BIN \ 260 pbl 261 262BUILD FIP: 263 264 .. code:: shell 265 266 make PLAT=$PLAT \ 267 BOOT_MODE=<platform_supported_boot_mode> \ 268 RCW=$RCW_BIN \ 269 BL33=$UBOOT_SECURE_BIN \ 270 pbl \ 271 fip 272 273Compilation steps with BL32 274~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 275 276BUILD BL2: 277 278-To compile 279 .. code:: shell 280 281 make PLAT=$PLAT \ 282 BOOT_MODE=<platform_supported_boot_mode> \ 283 RCW=$RCW_BIN \ 284 BL32=$TEE_BIN SPD=opteed\ 285 pbl 286 287BUILD FIP: 288 289 .. code:: shell 290 291 make PLAT=$PLAT \ 292 BOOT_MODE=<platform_supported_boot_mode> \ 293 RCW=$RCW_BIN \ 294 BL32=$TEE_BIN SPD=opteed\ 295 BL33=$UBOOT_SECURE_BIN \ 296 pbl \ 297 fip 298 299 300BUILD fip-ddr (Mandatory for certain platforms, refer table above): 301~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 302 303-To compile additional fip-ddr for selected platforms(Refer above table if the platform needs fip-ddr). 304 .. code:: shell 305 306 make PLAT=<platform_name> fip-ddr 307 308 309Deploy ATF Images 310================= 311 312Note: The size in the standard uboot commands for copy to nor, qspi, nand or sd 313should be modified based on the binary size of the image to be copied. 314 315- Deploy ATF images on flexspi-Nor or QSPI flash Alt Bank from U-Boot prompt. 316 317 -- Commands to flash images for bl2_xxx.pbl and fip.bin 318 319 Notes: ls1028ardb has no flexspi-Nor Alt Bank, so use "sf probe 0:0" for current bank. 320 321 .. code:: shell 322 323 tftp 82000000 $path/bl2_xxx.pbl; 324 325 i2c mw 66 50 20;sf probe 0:1; sf erase 0 +$filesize; sf write 0x82000000 0x0 $filesize; 326 327 tftp 82000000 $path/fip.bin; 328 i2c mw 66 50 20;sf probe 0:1; sf erase 0x100000 +$filesize; sf write 0x82000000 0x100000 $filesize; 329 330 -- Next step is valid for platform where FIP-DDR is needed. 331 332 .. code:: shell 333 334 tftp 82000000 $path/ddr_fip.bin; 335 i2c mw 66 50 20;sf probe 0:1; sf erase 0x800000 +$filesize; sf write 0x82000000 0x800000 $filesize; 336 337 -- Then reset to alternate bank to boot up ATF. 338 339 Command for lx2160a and ls1028a platforms: 340 341 .. code:: shell 342 343 qixisreset altbank; 344 345 Command for ls1046a platforms: 346 347 .. code:: shell 348 349 cpld reset altbank; 350 351- Deploy ATF images on SD/eMMC from U-Boot prompt. 352 -- file_size_in_block_sizeof_512 = (Size_of_bytes_tftp / 512) 353 354 .. code:: shell 355 356 mmc dev <idx>; (idx = 1 for eMMC; idx = 0 for SD) 357 358 tftp 82000000 $path/bl2_<sd>_or_<emmc>.pbl; 359 mmc write 82000000 8 <file_size_in_block_sizeof_512>; 360 361 tftp 82000000 $path/fip.bin; 362 mmc write 82000000 0x800 <file_size_in_block_sizeof_512>; 363 364 -- Next step is valid for platform that needs FIP-DDR. 365 366 .. code:: shell 367 368 tftp 82000000 $path/ddr_fip.bin; 369 mmc write 82000000 0x4000 <file_size_in_block_sizeof_512>; 370 371 -- Then reset to sd/emmc to boot up ATF from sd/emmc as boot-source. 372 373 Command for lx2160A and ls1028a platforms: 374 375 .. code:: shell 376 377 qixisreset <sd or emmc>; 378 379 Command for ls1043a and ls1046a platform: 380 381 .. code:: shell 382 383 cpld reset <sd or emmc>; 384 385- Deploy ATF images on IFC nor flash from U-Boot prompt. 386 387 .. code:: shell 388 389 tftp 82000000 $path/bl2_nor.pbl; 390 protect off 64000000 +$filesize; erase 64000000 +$filesize; cp.b 82000000 64000000 $filesize; 391 392 tftp 82000000 $path/fip.bin; 393 protect off 64100000 +$filesize; erase 64100000 +$filesize; cp.b 82000000 64100000 $filesize; 394 395 -- Then reset to alternate bank to boot up ATF. 396 397 Command for ls1043a platform: 398 399 .. code:: shell 400 401 cpld reset altbank; 402 403- Deploy ATF images on IFC nand flash from U-Boot prompt. 404 405 .. code:: shell 406 407 tftp 82000000 $path/bl2_nand.pbl; 408 nand erase 0x0 $filesize; nand write 82000000 0x0 $filesize; 409 410 tftp 82000000 $path/fip.bin; 411 nand erase 0x100000 $filesize;nand write 82000000 0x100000 $filesize; 412 413 -- Then reset to nand flash to boot up ATF. 414 415 Command for ls1043a platform: 416 417 .. code:: shell 418 419 cpld reset nand; 420 421 422 423Trusted Board Boot: 424=================== 425 426For TBBR, the binary name changes: 427 428+-------------+--------------------------+---------+-------------------+ 429| Boot Type | BL2 | FIP | FIP-DDR | 430+=============+==========================+=========+===================+ 431| Normal Boot | bl2_<boot_mode>.pbl | fip.bin | ddr_fip.bin | 432+-------------+--------------------------+---------+-------------------+ 433| TBBR Boot | bl2_<boot_mode>_sec.pbl | fip.bin | ddr_fip_sec.bin | 434+-------------+--------------------------+---------+-------------------+ 435 436Refer `nxp-ls-tbbr.rst`_ for detailed user steps. 437 438 439.. _lx2160a: https://www.nxp.com/products/processors-and-microcontrollers/arm-processors/layerscape-processors/layerscape-lx2160a-lx2120a-lx2080a-processors:LX2160A 440.. _lx2160ardb: https://www.nxp.com/products/processors-and-microcontrollers/arm-processors/layerscape-communication-process/layerscape-lx2160a-multicore-communications-processor:LX2160A 441.. _ls1028a: https://www.nxp.com/products/processors-and-microcontrollers/arm-processors/layerscape-processors/layerscape-1028a-applications-processor:LS1028A 442.. _ls1028ardb: https://www.nxp.com/design/qoriq-developer-resources/layerscape-ls1028a-reference-design-board:LS1028ARDB 443.. _ls1043a: https://www.nxp.com/products/processors-and-microcontrollers/arm-processors/layerscape-processors/layerscape-1043a-and-1023a-processors:LS1043A 444.. _ls1043ardb: https://www.nxp.com/design/qoriq-developer-resources/layerscape-ls1043a-reference-design-board:LS1043A-RDB 445.. _ls1046a: https://www.nxp.com/products/processors-and-microcontrollers/arm-processors/layerscape-processors/layerscape-1046a-and-1026a-processors:LS1046A 446.. _ls1046ardb: https://www.nxp.com/design/qoriq-developer-resources/layerscape-ls1046a-reference-design-board:LS1046A-RDB 447.. _ls1046afrwy: https://www.nxp.com/design/qoriq-developer-resources/ls1046a-freeway-board:FRWY-LS1046A 448.. _nxp-ls-tbbr.rst: ./nxp-ls-tbbr.rst 449