1 /* 2 * Copyright 2018-2021 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <endian.h> 8 9 #include <arch.h> 10 #include <caam.h> 11 #include <cassert.h> 12 #include <cci.h> 13 #include <common/debug.h> 14 #include <dcfg.h> 15 #include <i2c.h> 16 #include <lib/xlat_tables/xlat_tables_v2.h> 17 #include <ls_interconnect.h> 18 #include <mmio.h> 19 #ifdef POLICY_FUSE_PROVISION 20 #include <nxp_gpio.h> 21 #endif 22 #if TRUSTED_BOARD_BOOT 23 #include <nxp_smmu.h> 24 #endif 25 #include <nxp_timer.h> 26 #include <plat_console.h> 27 #include <plat_gic.h> 28 #include <plat_tzc400.h> 29 #include <pmu.h> 30 #include <scfg.h> 31 #if defined(NXP_SFP_ENABLED) 32 #include <sfp.h> 33 #endif 34 35 #include <errata.h> 36 #ifdef CONFIG_OCRAM_ECC_EN 37 #include <ocram.h> 38 #endif 39 #include "plat_common.h" 40 #include "platform_def.h" 41 #include "soc.h" 42 43 static dcfg_init_info_t dcfg_init_data = { 44 .g_nxp_dcfg_addr = NXP_DCFG_ADDR, 45 .nxp_sysclk_freq = NXP_SYSCLK_FREQ, 46 .nxp_ddrclk_freq = NXP_DDRCLK_FREQ, 47 .nxp_plat_clk_divider = NXP_PLATFORM_CLK_DIVIDER, 48 }; 49 50 static struct soc_type soc_list[] = { 51 SOC_ENTRY(LS1017AN, LS1017AN, 1, 1), 52 SOC_ENTRY(LS1017AE, LS1017AE, 1, 1), 53 SOC_ENTRY(LS1018AN, LS1018AN, 1, 1), 54 SOC_ENTRY(LS1018AE, LS1018AE, 1, 1), 55 SOC_ENTRY(LS1027AN, LS1027AN, 1, 2), 56 SOC_ENTRY(LS1027AE, LS1027AE, 1, 2), 57 SOC_ENTRY(LS1028AN, LS1028AN, 1, 2), 58 SOC_ENTRY(LS1028AE, LS1028AE, 1, 2), 59 }; 60 61 CASSERT(NUMBER_OF_CLUSTERS && NUMBER_OF_CLUSTERS <= 256, 62 assert_invalid_ls1028a_cluster_count); 63 64 /* 65 * Function returns the base counter frequency 66 * after reading the first entry at CNTFID0 (0x20 offset). 67 * 68 * Function is used by: 69 * 1. ARM common code for PSCI management. 70 * 2. ARM Generic Timer init. 71 * 72 */ 73 unsigned int plat_get_syscnt_freq2(void) 74 { 75 unsigned int counter_base_frequency; 76 /* 77 * Below register specifies the base frequency of the system counter. 78 * As per NXP Board Manuals: 79 * The system counter always works with SYS_REF_CLK/4 frequency clock. 80 */ 81 counter_base_frequency = mmio_read_32(NXP_TIMER_ADDR + CNTFID_OFF); 82 83 return counter_base_frequency; 84 } 85 86 #ifdef IMAGE_BL2 87 88 #ifdef POLICY_FUSE_PROVISION 89 static gpio_init_info_t gpio_init_data = { 90 .gpio1_base_addr = NXP_GPIO1_ADDR, 91 .gpio2_base_addr = NXP_GPIO2_ADDR, 92 .gpio3_base_addr = NXP_GPIO3_ADDR, 93 }; 94 #endif 95 96 void soc_preload_setup(void) 97 { 98 } 99 100 void soc_early_init(void) 101 { 102 uint8_t num_clusters, cores_per_cluster; 103 104 #ifdef CONFIG_OCRAM_ECC_EN 105 ocram_init(NXP_OCRAM_ADDR, NXP_OCRAM_SIZE); 106 #endif 107 dcfg_init(&dcfg_init_data); 108 enable_timer_base_to_cluster(NXP_PMU_ADDR); 109 enable_core_tb(NXP_PMU_ADDR); 110 dram_regions_info_t *dram_regions_info = get_dram_regions_info(); 111 112 #ifdef POLICY_FUSE_PROVISION 113 gpio_init(&gpio_init_data); 114 sec_init(NXP_CAAM_ADDR); 115 #endif 116 117 #if LOG_LEVEL > 0 118 /* Initialize the console to provide early debug support */ 119 plat_console_init(NXP_CONSOLE_ADDR, 120 NXP_UART_CLK_DIVIDER, NXP_CONSOLE_BAUDRATE); 121 #endif 122 enum boot_device dev = get_boot_dev(); 123 /* 124 * Mark the buffer for SD in OCRAM as non secure. 125 * The buffer is assumed to be at end of OCRAM for 126 * the logic below to calculate TZPC programming 127 */ 128 if (dev == BOOT_DEVICE_EMMC || dev == BOOT_DEVICE_SDHC2_EMMC) { 129 /* 130 * Calculate the region in OCRAM which is secure 131 * The buffer for SD needs to be marked non-secure 132 * to allow SD to do DMA operations on it 133 */ 134 uint32_t secure_region = (NXP_OCRAM_SIZE - NXP_SD_BLOCK_BUF_SIZE); 135 uint32_t mask = secure_region/TZPC_BLOCK_SIZE; 136 137 mmio_write_32(NXP_OCRAM_TZPC_ADDR, mask); 138 139 /* Add the entry for buffer in MMU Table */ 140 mmap_add_region(NXP_SD_BLOCK_BUF_ADDR, NXP_SD_BLOCK_BUF_ADDR, 141 NXP_SD_BLOCK_BUF_SIZE, MT_DEVICE | MT_RW | MT_NS); 142 } 143 144 #if TRUSTED_BOARD_BOOT 145 uint32_t mode; 146 147 sfp_init(NXP_SFP_ADDR); 148 149 /* 150 * For secure boot disable SMMU. 151 * Later when platform security policy comes in picture, 152 * this might get modified based on the policy 153 */ 154 if (check_boot_mode_secure(&mode) == true) { 155 bypass_smmu(NXP_SMMU_ADDR); 156 } 157 158 /* 159 * For Mbedtls currently crypto is not supported via CAAM 160 * enable it when that support is there. In tbbr.mk 161 * the CAAM_INTEG is set as 0. 162 */ 163 #ifndef MBEDTLS_X509 164 /* Initialize the crypto accelerator if enabled */ 165 if (is_sec_enabled()) { 166 sec_init(NXP_CAAM_ADDR); 167 } else { 168 INFO("SEC is disabled.\n"); 169 } 170 #endif 171 #endif 172 173 /* Set eDDRTQ for DDR performance */ 174 scfg_setbits32((void *)(NXP_SCFG_ADDR + 0x210), 0x1f1f1f1f); 175 176 soc_errata(); 177 178 /* 179 * Initialize Interconnect for this cluster during cold boot. 180 * No need for locks as no other CPU is active. 181 */ 182 cci_init(NXP_CCI_ADDR, cci_map, ARRAY_SIZE(cci_map)); 183 184 /* 185 * Enable Interconnect coherency for the primary CPU's cluster. 186 */ 187 get_cluster_info(soc_list, ARRAY_SIZE(soc_list), &num_clusters, &cores_per_cluster); 188 plat_ls_interconnect_enter_coherency(num_clusters); 189 190 delay_timer_init(NXP_TIMER_ADDR); 191 i2c_init(NXP_I2C_ADDR); 192 dram_regions_info->total_dram_size = init_ddr(); 193 } 194 195 void soc_bl2_prepare_exit(void) 196 { 197 #if defined(NXP_SFP_ENABLED) && defined(DISABLE_FUSE_WRITE) 198 set_sfp_wr_disable(); 199 #endif 200 } 201 202 /* 203 * This function returns the boot device based on RCW_SRC 204 */ 205 enum boot_device get_boot_dev(void) 206 { 207 enum boot_device src = BOOT_DEVICE_NONE; 208 uint32_t porsr1; 209 uint32_t rcw_src; 210 211 porsr1 = read_reg_porsr1(); 212 213 rcw_src = (porsr1 & PORSR1_RCW_MASK) >> PORSR1_RCW_SHIFT; 214 switch (rcw_src) { 215 case FLEXSPI_NOR: 216 src = BOOT_DEVICE_FLEXSPI_NOR; 217 INFO("RCW BOOT SRC is FLEXSPI NOR\n"); 218 break; 219 case FLEXSPI_NAND2K_VAL: 220 case FLEXSPI_NAND4K_VAL: 221 INFO("RCW BOOT SRC is FLEXSPI NAND\n"); 222 src = BOOT_DEVICE_FLEXSPI_NAND; 223 break; 224 case SDHC1_VAL: 225 src = BOOT_DEVICE_EMMC; 226 INFO("RCW BOOT SRC is SD\n"); 227 break; 228 case SDHC2_VAL: 229 src = BOOT_DEVICE_SDHC2_EMMC; 230 INFO("RCW BOOT SRC is EMMC\n"); 231 break; 232 default: 233 break; 234 } 235 236 return src; 237 } 238 239 /* 240 * This function sets up access permissions on memory regions 241 ****************************************************************************/ 242 void soc_mem_access(void) 243 { 244 dram_regions_info_t *info_dram_regions = get_dram_regions_info(); 245 struct tzc400_reg tzc400_reg_list[MAX_NUM_TZC_REGION]; 246 int dram_idx = 0; 247 /* index 0 is reserved for region-0 */ 248 int index = 1; 249 250 for (dram_idx = 0; dram_idx < info_dram_regions->num_dram_regions; 251 dram_idx++) { 252 if (info_dram_regions->region[dram_idx].size == 0) { 253 ERROR("DDR init failure, or"); 254 ERROR("DRAM regions not populated correctly.\n"); 255 break; 256 } 257 258 index = populate_tzc400_reg_list(tzc400_reg_list, 259 dram_idx, index, 260 info_dram_regions->region[dram_idx].addr, 261 info_dram_regions->region[dram_idx].size, 262 NXP_SECURE_DRAM_SIZE, NXP_SP_SHRD_DRAM_SIZE); 263 } 264 265 mem_access_setup(NXP_TZC_ADDR, index, tzc400_reg_list); 266 } 267 268 #else 269 270 static unsigned char _power_domain_tree_desc[NUMBER_OF_CLUSTERS + 2]; 271 /* 272 * This function dynamically constructs the topology according to 273 * SoC Flavor and returns it. 274 */ 275 const unsigned char *plat_get_power_domain_tree_desc(void) 276 { 277 uint8_t num_clusters, cores_per_cluster; 278 unsigned int i; 279 280 get_cluster_info(soc_list, ARRAY_SIZE(soc_list), &num_clusters, &cores_per_cluster); 281 /* 282 * The highest level is the system level. The next level is constituted 283 * by clusters and then cores in clusters. 284 */ 285 _power_domain_tree_desc[0] = 1; 286 _power_domain_tree_desc[1] = num_clusters; 287 288 for (i = 0; i < _power_domain_tree_desc[1]; i++) 289 _power_domain_tree_desc[i + 2] = cores_per_cluster; 290 291 return _power_domain_tree_desc; 292 } 293 294 /* 295 * This function returns the core count within the cluster corresponding to 296 * `mpidr`. 297 */ 298 unsigned int plat_ls_get_cluster_core_count(u_register_t mpidr) 299 { 300 uint8_t num_clusters, cores_per_cluster; 301 302 get_cluster_info(soc_list, ARRAY_SIZE(soc_list), &num_clusters, &cores_per_cluster); 303 return num_clusters; 304 } 305 306 void soc_early_platform_setup2(void) 307 { 308 dcfg_init(&dcfg_init_data); 309 /* Initialize system level generic timer for Socs */ 310 delay_timer_init(NXP_TIMER_ADDR); 311 312 #if LOG_LEVEL > 0 313 /* Initialize the console to provide early debug support */ 314 plat_console_init(NXP_CONSOLE_ADDR, 315 NXP_UART_CLK_DIVIDER, NXP_CONSOLE_BAUDRATE); 316 #endif 317 } 318 319 void soc_platform_setup(void) 320 { 321 /* Initialize the GIC driver, cpu and distributor interfaces */ 322 static uintptr_t target_mask_array[PLATFORM_CORE_COUNT]; 323 static interrupt_prop_t ls_interrupt_props[] = { 324 PLAT_LS_G1S_IRQ_PROPS(INTR_GROUP1S), 325 PLAT_LS_G0_IRQ_PROPS(INTR_GROUP0) 326 }; 327 328 plat_ls_gic_driver_init(NXP_GICD_ADDR, NXP_GICR_ADDR, 329 PLATFORM_CORE_COUNT, 330 ls_interrupt_props, 331 ARRAY_SIZE(ls_interrupt_props), 332 target_mask_array, 333 plat_core_pos); 334 335 plat_ls_gic_init(); 336 enable_init_timer(); 337 } 338 339 /* This function initializes the soc from the BL31 module */ 340 void soc_init(void) 341 { 342 uint8_t num_clusters, cores_per_cluster; 343 344 get_cluster_info(soc_list, ARRAY_SIZE(soc_list), &num_clusters, &cores_per_cluster); 345 346 /* Low-level init of the soc */ 347 soc_init_lowlevel(); 348 _init_global_data(); 349 soc_init_percpu(); 350 _initialize_psci(); 351 352 /* 353 * Initialize Interconnect for this cluster during cold boot. 354 * No need for locks as no other CPU is active. 355 */ 356 cci_init(NXP_CCI_ADDR, cci_map, ARRAY_SIZE(cci_map)); 357 358 /* Enable Interconnect coherency for the primary CPU's cluster. */ 359 plat_ls_interconnect_enter_coherency(num_clusters); 360 361 /* Set platform security policies */ 362 _set_platform_security(); 363 364 /* Init SEC Engine which will be used by SiP */ 365 if (is_sec_enabled()) { 366 sec_init(NXP_CAAM_ADDR); 367 } else { 368 INFO("SEC is disabled.\n"); 369 } 370 } 371 372 #ifdef NXP_WDOG_RESTART 373 static uint64_t wdog_interrupt_handler(uint32_t id, uint32_t flags, 374 void *handle, void *cookie) 375 { 376 uint8_t data = WDOG_RESET_FLAG; 377 378 wr_nv_app_data(WDT_RESET_FLAG_OFFSET, 379 (uint8_t *)&data, sizeof(data)); 380 381 mmio_write_32(NXP_RST_ADDR + RSTCNTL_OFFSET, SW_RST_REQ_INIT); 382 383 return 0; 384 } 385 #endif 386 387 void soc_runtime_setup(void) 388 { 389 #ifdef NXP_WDOG_RESTART 390 request_intr_type_el3(BL31_NS_WDOG_WS1, wdog_interrupt_handler); 391 #endif 392 } 393 394 /* This function returns the total number of cores in the SoC. */ 395 unsigned int get_tot_num_cores(void) 396 { 397 uint8_t num_clusters, cores_per_cluster; 398 399 get_cluster_info(soc_list, ARRAY_SIZE(soc_list), &num_clusters, &cores_per_cluster); 400 return (num_clusters * cores_per_cluster); 401 } 402 403 /* This function returns the PMU IDLE Cluster mask. */ 404 unsigned int get_pmu_idle_cluster_mask(void) 405 { 406 uint8_t num_clusters, cores_per_cluster; 407 408 get_cluster_info(soc_list, ARRAY_SIZE(soc_list), &num_clusters, &cores_per_cluster); 409 return ((1 << num_clusters) - 2); 410 } 411 412 /* This function returns the PMU Flush Cluster mask. */ 413 unsigned int get_pmu_flush_cluster_mask(void) 414 { 415 uint8_t num_clusters, cores_per_cluster; 416 417 get_cluster_info(soc_list, ARRAY_SIZE(soc_list), &num_clusters, &cores_per_cluster); 418 return ((1 << num_clusters) - 2); 419 } 420 421 /* This function returns the PMU idle core mask. */ 422 unsigned int get_pmu_idle_core_mask(void) 423 { 424 return ((1 << get_tot_num_cores()) - 2); 425 } 426 427 /* Function to return the SoC SYS CLK */ 428 unsigned int get_sys_clk(void) 429 { 430 return NXP_SYSCLK_FREQ; 431 } 432 #endif 433