xref: /rk3399_ARM-atf/plat/st/stm32mp1/stm32mp1_private.c (revision 4ce3e99a336b74611349595ea7fd5ed0277c3eeb) 
1 /*
2  * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #include <assert.h>
8 
9 #include <libfdt.h>
10 
11 #include <platform_def.h>
12 
13 #include <drivers/st/stm32_iwdg.h>
14 #include <lib/xlat_tables/xlat_tables_v2.h>
15 
16 /* Internal layout of the 32bit OTP word board_id */
17 #define BOARD_ID_BOARD_NB_MASK		GENMASK(31, 16)
18 #define BOARD_ID_BOARD_NB_SHIFT		16
19 #define BOARD_ID_VARCPN_MASK		GENMASK(15, 12)
20 #define BOARD_ID_VARCPN_SHIFT		12
21 #define BOARD_ID_REVISION_MASK		GENMASK(11, 8)
22 #define BOARD_ID_REVISION_SHIFT		8
23 #define BOARD_ID_VARFG_MASK		GENMASK(7, 4)
24 #define BOARD_ID_VARFG_SHIFT		4
25 #define BOARD_ID_BOM_MASK		GENMASK(3, 0)
26 
27 #define BOARD_ID2NB(_id)		(((_id) & BOARD_ID_BOARD_NB_MASK) >> \
28 					 BOARD_ID_BOARD_NB_SHIFT)
29 #define BOARD_ID2VARCPN(_id)		(((_id) & BOARD_ID_VARCPN_MASK) >> \
30 					 BOARD_ID_VARCPN_SHIFT)
31 #define BOARD_ID2REV(_id)		(((_id) & BOARD_ID_REVISION_MASK) >> \
32 					 BOARD_ID_REVISION_SHIFT)
33 #define BOARD_ID2VARFG(_id)		(((_id) & BOARD_ID_VARFG_MASK) >> \
34 					 BOARD_ID_VARFG_SHIFT)
35 #define BOARD_ID2BOM(_id)		((_id) & BOARD_ID_BOM_MASK)
36 
37 #if defined(IMAGE_BL2)
38 #define MAP_SEC_SYSRAM	MAP_REGION_FLAT(STM32MP_SYSRAM_BASE, \
39 					STM32MP_SYSRAM_SIZE, \
40 					MT_MEMORY | \
41 					MT_RW | \
42 					MT_SECURE | \
43 					MT_EXECUTE_NEVER)
44 #elif defined(IMAGE_BL32)
45 #define MAP_SEC_SYSRAM	MAP_REGION_FLAT(STM32MP_SEC_SYSRAM_BASE, \
46 					STM32MP_SEC_SYSRAM_SIZE, \
47 					MT_MEMORY | \
48 					MT_RW | \
49 					MT_SECURE | \
50 					MT_EXECUTE_NEVER)
51 
52 /* Non-secure SYSRAM is used a uncached memory for SCMI message transfer */
53 #define MAP_NS_SYSRAM	MAP_REGION_FLAT(STM32MP_NS_SYSRAM_BASE, \
54 					STM32MP_NS_SYSRAM_SIZE, \
55 					MT_DEVICE | \
56 					MT_RW | \
57 					MT_NS | \
58 					MT_EXECUTE_NEVER)
59 #endif
60 
61 #define MAP_DEVICE1	MAP_REGION_FLAT(STM32MP1_DEVICE1_BASE, \
62 					STM32MP1_DEVICE1_SIZE, \
63 					MT_DEVICE | \
64 					MT_RW | \
65 					MT_SECURE | \
66 					MT_EXECUTE_NEVER)
67 
68 #define MAP_DEVICE2	MAP_REGION_FLAT(STM32MP1_DEVICE2_BASE, \
69 					STM32MP1_DEVICE2_SIZE, \
70 					MT_DEVICE | \
71 					MT_RW | \
72 					MT_SECURE | \
73 					MT_EXECUTE_NEVER)
74 
75 #if defined(IMAGE_BL2)
76 static const mmap_region_t stm32mp1_mmap[] = {
77 	MAP_SEC_SYSRAM,
78 	MAP_DEVICE1,
79 	MAP_DEVICE2,
80 	{0}
81 };
82 #endif
83 #if defined(IMAGE_BL32)
84 static const mmap_region_t stm32mp1_mmap[] = {
85 	MAP_SEC_SYSRAM,
86 	MAP_NS_SYSRAM,
87 	MAP_DEVICE1,
88 	MAP_DEVICE2,
89 	{0}
90 };
91 #endif
92 
93 void configure_mmu(void)
94 {
95 	mmap_add(stm32mp1_mmap);
96 	init_xlat_tables();
97 
98 	enable_mmu_svc_mon(0);
99 }
100 
101 uintptr_t stm32_get_gpio_bank_base(unsigned int bank)
102 {
103 	if (bank == GPIO_BANK_Z) {
104 		return GPIOZ_BASE;
105 	}
106 
107 	assert(GPIO_BANK_A == 0 && bank <= GPIO_BANK_K);
108 
109 	return GPIOA_BASE + (bank * GPIO_BANK_OFFSET);
110 }
111 
112 uint32_t stm32_get_gpio_bank_offset(unsigned int bank)
113 {
114 	if (bank == GPIO_BANK_Z) {
115 		return 0;
116 	}
117 
118 	assert(GPIO_BANK_A == 0 && bank <= GPIO_BANK_K);
119 
120 	return bank * GPIO_BANK_OFFSET;
121 }
122 
123 unsigned long stm32_get_gpio_bank_clock(unsigned int bank)
124 {
125 	if (bank == GPIO_BANK_Z) {
126 		return GPIOZ;
127 	}
128 
129 	assert(GPIO_BANK_A == 0 && bank <= GPIO_BANK_K);
130 
131 	return GPIOA + (bank - GPIO_BANK_A);
132 }
133 
134 int stm32_get_gpio_bank_pinctrl_node(void *fdt, unsigned int bank)
135 {
136 	switch (bank) {
137 	case GPIO_BANK_A:
138 	case GPIO_BANK_B:
139 	case GPIO_BANK_C:
140 	case GPIO_BANK_D:
141 	case GPIO_BANK_E:
142 	case GPIO_BANK_F:
143 	case GPIO_BANK_G:
144 	case GPIO_BANK_H:
145 	case GPIO_BANK_I:
146 	case GPIO_BANK_J:
147 	case GPIO_BANK_K:
148 		return fdt_path_offset(fdt, "/soc/pin-controller");
149 	case GPIO_BANK_Z:
150 		return fdt_path_offset(fdt, "/soc/pin-controller-z");
151 	default:
152 		panic();
153 	}
154 }
155 
156 uint32_t stm32mp_get_chip_version(void)
157 {
158 	uint32_t version = 0U;
159 
160 	if (stm32mp1_dbgmcu_get_chip_version(&version) < 0) {
161 		INFO("Cannot get CPU version, debug disabled\n");
162 		return 0U;
163 	}
164 
165 	return version;
166 }
167 
168 uint32_t stm32mp_get_chip_dev_id(void)
169 {
170 	uint32_t dev_id;
171 
172 	if (stm32mp1_dbgmcu_get_chip_dev_id(&dev_id) < 0) {
173 		INFO("Use default chip ID, debug disabled\n");
174 		dev_id = STM32MP1_CHIP_ID;
175 	}
176 
177 	return dev_id;
178 }
179 
180 static uint32_t get_part_number(void)
181 {
182 	static uint32_t part_number;
183 
184 	if (part_number != 0U) {
185 		return part_number;
186 	}
187 
188 	if (bsec_shadow_read_otp(&part_number, PART_NUMBER_OTP) != BSEC_OK) {
189 		panic();
190 	}
191 
192 	part_number = (part_number & PART_NUMBER_OTP_PART_MASK) >>
193 		PART_NUMBER_OTP_PART_SHIFT;
194 
195 	part_number |= stm32mp_get_chip_dev_id() << 16;
196 
197 	return part_number;
198 }
199 
200 static uint32_t get_cpu_package(void)
201 {
202 	uint32_t package;
203 
204 	if (bsec_shadow_read_otp(&package, PACKAGE_OTP) != BSEC_OK) {
205 		panic();
206 	}
207 
208 	package = (package & PACKAGE_OTP_PKG_MASK) >>
209 		PACKAGE_OTP_PKG_SHIFT;
210 
211 	return package;
212 }
213 
214 void stm32mp_get_soc_name(char name[STM32_SOC_NAME_SIZE])
215 {
216 	char *cpu_s, *cpu_r, *pkg;
217 
218 	/* MPUs Part Numbers */
219 	switch (get_part_number()) {
220 	case STM32MP157C_PART_NB:
221 		cpu_s = "157C";
222 		break;
223 	case STM32MP157A_PART_NB:
224 		cpu_s = "157A";
225 		break;
226 	case STM32MP153C_PART_NB:
227 		cpu_s = "153C";
228 		break;
229 	case STM32MP153A_PART_NB:
230 		cpu_s = "153A";
231 		break;
232 	case STM32MP151C_PART_NB:
233 		cpu_s = "151C";
234 		break;
235 	case STM32MP151A_PART_NB:
236 		cpu_s = "151A";
237 		break;
238 	case STM32MP157F_PART_NB:
239 		cpu_s = "157F";
240 		break;
241 	case STM32MP157D_PART_NB:
242 		cpu_s = "157D";
243 		break;
244 	case STM32MP153F_PART_NB:
245 		cpu_s = "153F";
246 		break;
247 	case STM32MP153D_PART_NB:
248 		cpu_s = "153D";
249 		break;
250 	case STM32MP151F_PART_NB:
251 		cpu_s = "151F";
252 		break;
253 	case STM32MP151D_PART_NB:
254 		cpu_s = "151D";
255 		break;
256 	default:
257 		cpu_s = "????";
258 		break;
259 	}
260 
261 	/* Package */
262 	switch (get_cpu_package()) {
263 	case PKG_AA_LFBGA448:
264 		pkg = "AA";
265 		break;
266 	case PKG_AB_LFBGA354:
267 		pkg = "AB";
268 		break;
269 	case PKG_AC_TFBGA361:
270 		pkg = "AC";
271 		break;
272 	case PKG_AD_TFBGA257:
273 		pkg = "AD";
274 		break;
275 	default:
276 		pkg = "??";
277 		break;
278 	}
279 
280 	/* REVISION */
281 	switch (stm32mp_get_chip_version()) {
282 	case STM32MP1_REV_B:
283 		cpu_r = "B";
284 		break;
285 	case STM32MP1_REV_Z:
286 		cpu_r = "Z";
287 		break;
288 	default:
289 		cpu_r = "?";
290 		break;
291 	}
292 
293 	snprintf(name, STM32_SOC_NAME_SIZE,
294 		 "STM32MP%s%s Rev.%s", cpu_s, pkg, cpu_r);
295 }
296 
297 void stm32mp_print_cpuinfo(void)
298 {
299 	char name[STM32_SOC_NAME_SIZE];
300 
301 	stm32mp_get_soc_name(name);
302 	NOTICE("CPU: %s\n", name);
303 }
304 
305 void stm32mp_print_boardinfo(void)
306 {
307 	uint32_t board_id;
308 	uint32_t board_otp;
309 	int bsec_node, bsec_board_id_node;
310 	void *fdt;
311 	const fdt32_t *cuint;
312 
313 	if (fdt_get_address(&fdt) == 0) {
314 		panic();
315 	}
316 
317 	bsec_node = fdt_node_offset_by_compatible(fdt, -1, DT_BSEC_COMPAT);
318 	if (bsec_node < 0) {
319 		return;
320 	}
321 
322 	bsec_board_id_node = fdt_subnode_offset(fdt, bsec_node, "board_id");
323 	if (bsec_board_id_node <= 0) {
324 		return;
325 	}
326 
327 	cuint = fdt_getprop(fdt, bsec_board_id_node, "reg", NULL);
328 	if (cuint == NULL) {
329 		panic();
330 	}
331 
332 	board_otp = fdt32_to_cpu(*cuint) / sizeof(uint32_t);
333 
334 	if (bsec_shadow_read_otp(&board_id, board_otp) != BSEC_OK) {
335 		ERROR("BSEC: PART_NUMBER_OTP Error\n");
336 		return;
337 	}
338 
339 	if (board_id != 0U) {
340 		char rev[2];
341 
342 		rev[0] = BOARD_ID2REV(board_id) - 1 + 'A';
343 		rev[1] = '\0';
344 		NOTICE("Board: MB%04x Var%u.%u Rev.%s-%02u\n",
345 		       BOARD_ID2NB(board_id),
346 		       BOARD_ID2VARCPN(board_id),
347 		       BOARD_ID2VARFG(board_id),
348 		       rev,
349 		       BOARD_ID2BOM(board_id));
350 	}
351 }
352 
353 /* Return true when SoC provides a single Cortex-A7 core, and false otherwise */
354 bool stm32mp_is_single_core(void)
355 {
356 	switch (get_part_number()) {
357 	case STM32MP151A_PART_NB:
358 	case STM32MP151C_PART_NB:
359 	case STM32MP151D_PART_NB:
360 	case STM32MP151F_PART_NB:
361 		return true;
362 	default:
363 		return false;
364 	}
365 }
366 
367 /* Return true when device is in closed state */
368 bool stm32mp_is_closed_device(void)
369 {
370 	uint32_t value;
371 
372 	if ((bsec_shadow_register(DATA0_OTP) != BSEC_OK) ||
373 	    (bsec_read_otp(&value, DATA0_OTP) != BSEC_OK)) {
374 		return true;
375 	}
376 
377 	return (value & DATA0_OTP_SECURED) == DATA0_OTP_SECURED;
378 }
379 
380 uint32_t stm32_iwdg_get_instance(uintptr_t base)
381 {
382 	switch (base) {
383 	case IWDG1_BASE:
384 		return IWDG1_INST;
385 	case IWDG2_BASE:
386 		return IWDG2_INST;
387 	default:
388 		panic();
389 	}
390 }
391 
392 uint32_t stm32_iwdg_get_otp_config(uint32_t iwdg_inst)
393 {
394 	uint32_t iwdg_cfg = 0U;
395 	uint32_t otp_value;
396 
397 #if defined(IMAGE_BL2)
398 	if (bsec_shadow_register(HW2_OTP) != BSEC_OK) {
399 		panic();
400 	}
401 #endif
402 
403 	if (bsec_read_otp(&otp_value, HW2_OTP) != BSEC_OK) {
404 		panic();
405 	}
406 
407 	if ((otp_value & BIT(iwdg_inst + HW2_OTP_IWDG_HW_POS)) != 0U) {
408 		iwdg_cfg |= IWDG_HW_ENABLED;
409 	}
410 
411 	if ((otp_value & BIT(iwdg_inst + HW2_OTP_IWDG_FZ_STOP_POS)) != 0U) {
412 		iwdg_cfg |= IWDG_DISABLE_ON_STOP;
413 	}
414 
415 	if ((otp_value & BIT(iwdg_inst + HW2_OTP_IWDG_FZ_STANDBY_POS)) != 0U) {
416 		iwdg_cfg |= IWDG_DISABLE_ON_STANDBY;
417 	}
418 
419 	return iwdg_cfg;
420 }
421 
422 #if defined(IMAGE_BL2)
423 uint32_t stm32_iwdg_shadow_update(uint32_t iwdg_inst, uint32_t flags)
424 {
425 	uint32_t otp;
426 	uint32_t result;
427 
428 	if (bsec_shadow_read_otp(&otp, HW2_OTP) != BSEC_OK) {
429 		panic();
430 	}
431 
432 	if ((flags & IWDG_DISABLE_ON_STOP) != 0U) {
433 		otp |= BIT(iwdg_inst + HW2_OTP_IWDG_FZ_STOP_POS);
434 	}
435 
436 	if ((flags & IWDG_DISABLE_ON_STANDBY) != 0U) {
437 		otp |= BIT(iwdg_inst + HW2_OTP_IWDG_FZ_STANDBY_POS);
438 	}
439 
440 	result = bsec_write_otp(otp, HW2_OTP);
441 	if (result != BSEC_OK) {
442 		return result;
443 	}
444 
445 	/* Sticky lock OTP_IWDG (read and write) */
446 	if (!bsec_write_sr_lock(HW2_OTP, 1U) ||
447 	    !bsec_write_sw_lock(HW2_OTP, 1U)) {
448 		return BSEC_LOCK_FAIL;
449 	}
450 
451 	return BSEC_OK;
452 }
453 #endif
454 
455 #if STM32MP_USE_STM32IMAGE
456 /* Get the non-secure DDR size */
457 uint32_t stm32mp_get_ddr_ns_size(void)
458 {
459 	static uint32_t ddr_ns_size;
460 	uint32_t ddr_size;
461 
462 	if (ddr_ns_size != 0U) {
463 		return ddr_ns_size;
464 	}
465 
466 	ddr_size = dt_get_ddr_size();
467 	if ((ddr_size <= (STM32MP_DDR_S_SIZE + STM32MP_DDR_SHMEM_SIZE)) ||
468 	    (ddr_size > STM32MP_DDR_MAX_SIZE)) {
469 		panic();
470 	}
471 
472 	ddr_ns_size = ddr_size - (STM32MP_DDR_S_SIZE + STM32MP_DDR_SHMEM_SIZE);
473 
474 	return ddr_ns_size;
475 }
476 #endif /* STM32MP_USE_STM32IMAGE */
477